CN202068397U - High-voltage to low-voltage conversion circuit using low-voltage technology to resist high voltage - Google Patents
High-voltage to low-voltage conversion circuit using low-voltage technology to resist high voltage Download PDFInfo
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- CN202068397U CN202068397U CN2011201606364U CN201120160636U CN202068397U CN 202068397 U CN202068397 U CN 202068397U CN 2011201606364 U CN2011201606364 U CN 2011201606364U CN 201120160636 U CN201120160636 U CN 201120160636U CN 202068397 U CN202068397 U CN 202068397U
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Abstract
The utility model is suitable for the field of integrated circuits and provides a high-voltage to low-voltage conversion circuit using a low-voltage technology to resist high voltage. The circuit comprises a low-voltage power generating unit which outputs stable low-voltage power and a biasing unit which provides voltage bias and current bias, wherein the biasing unit is connected with the low-voltage power generating unit, the biasing unit comprises a first current mirror and a second current mirror which are serially connected, and the low-voltage power generating unit comprises a series voltage dividing element, a level conversion element and a voltage stabilizing capacitor which are sequentially connected. Compared with the prior art, the high-voltage to low-voltage conversion circuit using the low-voltage technology to resist high voltage has the beneficial effects that on one hand, a Zener diode is not required to be used and to be customized additionally, and the chip cost and the debugging expense are reduced; and on the other hand, all components used in the circuit are low-voltage components, the circuit can be realized through the standard low-voltage technology, the chip area is reduced and the production cost is decreased.
Description
Technical field
The utility model belongs to integrated circuit fields, relates in particular to a kind of with the high voltage bearing level shifter circuit of low pressure process.
Background technology
In power management IC, the situation of multiple operating voltage coexistence often appears, and be 10V as input voltage, and inner Digital Logical Circuits adopt low pressure process to realize, as 3.3V or 5V.The voltage endurance capability of low-voltage device is lower, for example, and the low-voltage device of 0.35um is withstand voltage about 3.7V, the low-voltage device of 0.5um is withstand voltage about 6V.Therefore, need convert high-tension electricity to low tension by level shifter circuit.In the production of integrated circuits field, the selection of technology is directly connected to cost, R﹠D cycle, and circuit design has determined the selection of technology.
Consult Fig. 1, be existing level shifter circuit schematic diagram.Wherein, I0 provides bias current by current source, input voltage is high pressure HVDD, after the zener Z120 voltage stabilizing, current mirror output through metal-oxide-semiconductor M101 and M102 composition, output voltage LVDD is approximately equal to the pressure drop of zener Z120, after capacitor C 110 voltage stabilizings, can be used as the low-voltage module power supply and uses.In this circuit, need to use zener, high-voltage tube.Because zener is not a normal component, customizing this device needs the long period, and debugging charge is higher; Use high-voltage tube, can cause chip area bigger, and the high-pressure process cost is higher.
The utility model content
In order to solve the aforementioned problems in the prior, it is a kind of with the high voltage bearing level shifter circuit of low pressure process that the purpose of the utility model embodiment is to provide.
The utility model embodiment realizes like this, a kind of with the high voltage bearing level shifter circuit of low pressure process, described circuit comprises: the low-tension supply generation unit of LVPS is stablized in output, and, the bias unit of voltage bias, current offset is provided, described bias unit links to each other with described low-tension supply generation unit
Described bias unit comprises first current mirror and second current mirror of series connection, and described low-tension supply generation unit comprises series connection sectional pressure element, level conversion element and the electric capacity of voltage regulation that connects successively.
Further, first current mirror of described voltage bias is telescopic common-source common-gate current mirror, comprises nine PMOS pipes M201, M202, M203, M204, M205, M206, M213, M214, M215, and the body end of each PMOS is connected with source end separately; Described second current mirror comprises six NMOS pipes M207, M208, M209, M210, M211, M212, and the body end of each NMOS is connected with P type substrate; Also be connected with triode Q240, resistance R 230, R231 between the source electrode of NMOS pipe M209 and the ground, and described resistance R 230 is with in parallel with resistance R 231 again after Q240 connects; Also be connected with triode Q241 and resistance R 232 between the source electrode of NMOS pipe M212 and the ground, and described resistance R 232 is in parallel with triode Q241; Described PMOS pipe M215 also links to each other with NMOS pipe M216, and also has been connected in series resistance R 233 between the source electrode of M216 and the ground.
Further, described low-tension supply generation unit comprises series connection sectional pressure element, level conversion element, electric capacity of voltage regulation, and described series connection sectional pressure element comprises PMOS pipe M217, M218, the M219 of three series connection, and the body end of each PMOS is connected with source end separately; The level conversion element comprises NMOS pipe M220; Electric capacity of voltage regulation adopts capacitor C 250.
Further, first current mirror of described bias unit comprises 3 PMOS pipes M201, M204, M213, and the body end of each PMOS is connected with source end separately; And first current mirror also comprises resistance R 234, R235, the R236 that links to each other with M201, M204, M213 respectively.
Further, described series connection sectional pressure element adopts triode Q242, Q243, the Q244 of 3 serial connections.
Further, described level conversion element adopts triode Q250.
The utility model compared with prior art can be achieved as follows beneficial effect: on the one hand, level shifter circuit described in the utility model does not need to use zener, does not need additional customized, has reduced chip cost and debugging cost; On the other hand, all used low-voltage device in the circuit, can realize, reduced chip area, reduced production costs by the low pressure process of standard.
Description of drawings
Fig. 1 is the structure chart of the level shifter circuit that provides of prior art;
Fig. 2 is the structure chart of the level shifter circuit that provides of the utility model first embodiment;
Fig. 3 is the structure chart of the level shifter circuit that provides of the utility model second embodiment;
Fig. 4 is the structure chart of the level shifter circuit that provides of the utility model the 3rd embodiment;
Fig. 5 is the structure chart of the level shifter circuit that provides of the utility model the 4th embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer,, the utility model is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
Fig. 2 shows the structure of the level shifter circuit that the utility model first embodiment provides, and this level shifter circuit comprises bias unit 21, low-tension supply generation unit 22.Wherein, the stable LVPS (LVDD among the figure) of described low-tension supply generation unit 22 outputs.Bias unit 21 provides voltage bias (VREG among the figure), current offset for low-tension supply generation unit 22.
As embodiment of the present utility model, this bias unit 21 comprises: first current mirror, second current mirror, triode and resistance.Wherein, first current mirror is telescopic common-source common-gate current mirror, comprises nine PMOS pipes M201, M202, M203, M204, M205, M206, M213, M214, M215, and the body end of each PMOS is connected with source end separately.
Second current mirror comprises six NMOS pipes M207, M208, M209, M210, M211, M212, and the body end of each NMOS is connected with P type substrate.Also be connected with triode Q240, resistance R 230, R231 between the source electrode of NMOS pipe M209 and the ground, and described resistance R 230 is with in parallel with resistance R 231 again after Q240 connects.
Also be connected with triode Q241 and resistance R 232 between the source electrode of NMOS pipe M212 and the ground, and described resistance R 232 is in parallel with triode Q241.Described triode Q240 and Q241 all connect into the diode form.
Described PMOS pipe M215 also links to each other with NMOS pipe M216, and also has been connected in series resistance R 233 between the source electrode of M216 and the ground.Bias unit 21 provides bias voltage VREG for low-tension supply generation unit 22.
Low-tension supply generation unit 22 adopts following structure: comprise series connection sectional pressure element, level conversion element, electric capacity of voltage regulation.Wherein, the series connection sectional pressure element is shared the part pressure drop, and described series connection sectional pressure element comprises PMOS pipe M217, M218, the M219 of three series connection, and the body end of each PMOS is connected with source end separately.The level conversion element is converted to LVDD to bias voltage VREG, and the level conversion element comprises NMOS pipe M220, and LVDD is approximately equal to the pressure drop on the resistance R 233; Electric capacity of voltage regulation C250 stablizes LVDD.
Suppose that each PMOS pipe is measure-alike in first current mirror, each NMOS pipe is measure-alike in second current mirror, and triode Q240 is n:1 with the number ratio of Q241, and resistance R 231 equates that with the resistance of R232 the electric current I that then flows through resistance R 233 can be expressed as:
Because the voltage of LVDD is approximately equal to the pressure drop on the resistance R 233, then its expression formula is as follows:
（2）
Wherein, k is a Boltzmann constant, and T is temperature (K), and q is an electronic charge.
Expression formula (2) by LVDD can be seen, selects for use resistance of the same type can make resistance R 233 temperature independent with the ratio of R232; First is negative temperature coefficient in the bracket, and second is positive temperature coefficient, and by regulating resistance R 230, R232, R233 and n, we can obtain the low-tension supply LVDD of the low-temperature coefficient that has nothing to do with supply voltage HVDD and have.
In the present embodiment, do not need Zener diode and high tension apparatus, all use low-voltage device to realize that bias unit, low-tension supply generation unit are by constituting between mos, pnp, npn, resistance, the electric capacity.
Consult Fig. 3, this second embodiment and first embodiment are similar substantially, and its difference is that first current mirror comprises 3 PMOS pipes M201, M204, M213, and the body end of each PMOS is connected with source end separately.In addition, first current mirror also comprises resistance R 234, R235, the R236 that links to each other with M201, M204, M213 respectively.In addition, described series connection sectional pressure element adopts triode Q242, Q243, the Q244 of 3 serial connections.
Consult Fig. 4, the 3rd embodiment compares with first embodiment, and its difference is that second current mirror comprises six triode Q244, Q245, Q246, Q242, Q243, Q247.In addition, described level conversion element adopts triode Q250, and resistance R 233 also has been connected in series triode Q249.In addition, remove resistance R 231, R232.
Consult Fig. 5, this embodiment mainly forms in conjunction with above-mentioned several embodiment, and the 4th embodiment compares with first embodiment, and its difference is that first current mirror comprises 3 PMOS pipes M201, M204, M213, and the body end of each PMOS is connected with source end separately.In addition, first current mirror also comprises resistance R 234, R235, the R236 that links to each other with M201, M204, M213 respectively.Second current mirror comprises 2 triode Q244, Q242, and, between triode Q241 and triode Q242, also be connected resistance R 238.In addition, remove resistance R 231, R232.In addition, described level conversion element adopts triode Q250, and resistance R 233 also has been connected in series triode Q249.
In the utility model, utilize low-voltage device to carry out the voltage dividing potential drop, each voltage between terminals difference of device is not more than the rated operational voltage value by the technology decision.
The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.
Claims (6)
1. one kind with the high voltage bearing level shifter circuit of low pressure process, it is characterized in that described circuit comprises: the low-tension supply generation unit of LVPS is stablized in output, and, the bias unit of voltage bias, current offset is provided, and described bias unit links to each other with described low-tension supply generation unit
Described bias unit comprises first current mirror and second current mirror of series connection, and described low-tension supply generation unit comprises series connection sectional pressure element, level conversion element and the electric capacity of voltage regulation that connects successively.
2. according to claim 1 with the high voltage bearing level shifter circuit of low pressure process, it is characterized in that, first current mirror of described voltage bias is telescopic common-source common-gate current mirror, comprise nine PMOS pipes M201, M202, M203, M204, M205, M206, M213, M214, M215, the body end of each PMOS is connected with source end separately; Described second current mirror comprises six NMOS pipes M207, M208, M209, M210, M211, M212, and the body end of each NMOS is connected with P type substrate; Also be connected with triode Q240, resistance R 230, R231 between the source electrode of NMOS pipe M209 and the ground, and described resistance R 230 is with in parallel with resistance R 231 again after Q240 connects; Also be connected with triode Q241 and resistance R 232 between the source electrode of NMOS pipe M212 and the ground, and described resistance R 232 is in parallel with triode Q241; Described PMOS pipe M215 also links to each other with NMOS pipe M216, and also has been connected in series resistance R 233 between the source electrode of M216 and the ground.
3. according to claim 1 with the high voltage bearing level shifter circuit of low pressure process, it is characterized in that, described low-tension supply generation unit comprises series connection sectional pressure element, level conversion element, electric capacity of voltage regulation, described series connection sectional pressure element comprises PMOS pipe M217, M218, the M219 of three series connection, and the body end of each PMOS is connected with source end separately; The level conversion element comprises NMOS pipe M220; Electric capacity of voltage regulation adopts capacitor C 250.
4. the high voltage bearing level shifter circuit of low pressure process of using according to claim 1 is characterized in that, first current mirror of described bias unit comprises 3 PMOS pipes M201, M204, M213, and the body end of each PMOS is connected with source end separately; And first current mirror also comprises resistance R 234, R235, the R236 that links to each other with M201, M204, M213 respectively.
5. the high voltage bearing level shifter circuit of low pressure process of using according to claim 1 is characterized in that described series connection sectional pressure element adopts triode Q242, Q243, the Q244 of 3 serial connections.
6. the high voltage bearing level shifter circuit of low pressure process of using according to claim 1 is characterized in that described level conversion element adopts triode Q250.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201606364U CN202068397U (en) | 2011-05-19 | 2011-05-19 | High-voltage to low-voltage conversion circuit using low-voltage technology to resist high voltage |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201606364U CN202068397U (en) | 2011-05-19 | 2011-05-19 | High-voltage to low-voltage conversion circuit using low-voltage technology to resist high voltage |
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| CN202068397U true CN202068397U (en) | 2011-12-07 |
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| CN2011201606364U Expired - Fee Related CN202068397U (en) | 2011-05-19 | 2011-05-19 | High-voltage to low-voltage conversion circuit using low-voltage technology to resist high voltage |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104242909A (en) * | 2014-10-22 | 2014-12-24 | 上海芯导电子科技有限公司 | Level conversion circuit |
| JP2018186400A (en) * | 2017-04-26 | 2018-11-22 | ラピスセミコンダクタ株式会社 | Level shift circuit |
-
2011
- 2011-05-19 CN CN2011201606364U patent/CN202068397U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104242909A (en) * | 2014-10-22 | 2014-12-24 | 上海芯导电子科技有限公司 | Level conversion circuit |
| CN104242909B (en) * | 2014-10-22 | 2017-09-05 | 上海芯导电子科技有限公司 | A kind of level shifting circuit |
| JP2018186400A (en) * | 2017-04-26 | 2018-11-22 | ラピスセミコンダクタ株式会社 | Level shift circuit |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111207 Termination date: 20150519 |
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| EXPY | Termination of patent right or utility model |