CN202042102U

CN202042102U - Multimedia field-programmable gate array (FPGA) education developing machine

Info

Publication number: CN202042102U
Application number: CN2011200910723U
Authority: CN
Inventors: 罗晶; 孙俊影
Original assignee: SHANGHAI RONGKEJIA INFORMATION TECHNOLOGY CO LTD
Current assignee: SHANGHAI RONGKEJIA INFORMATION TECHNOLOGY CO LTD
Priority date: 2011-03-31
Filing date: 2011-03-31
Publication date: 2011-11-16
Anticipated expiration: 2021-03-31

Abstract

The utility model provides a multimedia field-programmable gate array (FPGA) education developing machine. The multimedia FPGA education developing machine is provided with a system FPGA chip, a wireless communication interface, a double-rate synchronous dynamic random access memory, a non-volatile flash memory, a display module, an image sensor, a robot controller general interface, a video coding chip, a video decoding chip and an audio coding and decoding chip which are connected with different pins of the FPGA chip respectively. In the multimedia FPGA education developing machine, a plurality of interfaces and elements are integrated, so that students can design various circuits conveniently. Moreover, a wireless communication interface is adopted, so that real-time communication and high-speed data transmission can be realized; and a double complementary metal-oxide-semiconductor (CMOS) sensor expansion structure is supported, and multi-dimensional static target analysis can be realized.

Description

A kind of multimedia FPGA education developing engine

Technical field

The utility model relates to instructional device, relates in particular to a kind of multimedia FPGA education developing engine.

Background technology

At present in school instruction, begun to promote successively E-learning, and emphasize students'ability for practice, school is in default of related experiment equipment at present, still lay particular emphasis on theory teaching mostly,, only limit to the realization of some ball bearing made using though some experiment courses are also arranged, and need provide different electronic equipment and elements to use according to different experiment contents for the student, be not very convenient.

The utility model then provides a kind of multimedia FPGA education developing engine in order to improve or to solve the above problems.

The utility model content

The utility model provides a kind of multimedia FPGA education developing engine, and it can be convenient to student's autonomous Design circuit.

For solving the problems of the technologies described above, the utility model provides a kind of multimedia FPGA education developing engine, it is provided with system programmable logic array fpga chip, the wireless communication interface that different pins with fpga chip connect respectively, Double Data Rate synchronous DRAM, nonvolatile flash memory, display module, imageing sensor, robot controller general-purpose interface, video coding chip, video decoding chip and audio encoding and decoding chip.

As further improvement, fpga chip connects FPGA dedicated serial config memory, and also being connected with USB simultaneously changes the serial paralled interface control chip, and it can be connected with a download cable.

As further improvement, the fpga chip pin connects a USB interface chip.

As further improvement, described imageing sensor is a cmos sensor.

As further improvement, described video coding chip connects the VGA output terminal.

As further improvement, video decoding chip is used to connect a television decoder.

As further improvement, the pin of fpga chip connects the SD card.

The utility model is integrated much an interface and element is convenient to the student and designed various types of circuit.In addition, the utility model has adopted wireless communication interface, can realize real-time communication and high speed data transfer; Support two cmos sensor expansion structures, can realize the analysis of multidimensional static target.

Description of drawings

Fig. 1 is the connection diagram of the utility model multimedia FPGA education developing engine.

Embodiment

See also Fig. 1, multimedia FPGA that the utility model provides education developing engine is provided with system programmable logic array fpga chip 10, the wireless communication interface 20 that connects respectively with fpga chip 10 different pins, expansion interface 21, FPGA dedicated serial config memory 22, two DDR (Double Data Rate synchronous DRAM) 23, nonvolatile flash memory NOR FLASH 24, display module 25, SD card 26, two imageing sensors 27, PS2 keyboard 28, IF for robot 29, RS232 30, Ethernet interface 31, video coding chip 32, video decoding chip 33, audio encoding and decoding chip 34, and USB interface chip 35.

Wireless communication interface 20 can be sent to backstage control center in real time by wireless network, improves interactive capability.

Also being connected with USB on the pin of fpga chip 10 connection FPGA dedicated serial config memorys 22 changes serial paralled interface control chip 221, and it can be connected with a download cable (USB BLASTER) 223 by M3218.

Display module 25 adopts LCD or LED.

Imageing sensor 27 preferred signals are the 1080P60 cmos sensor of Sony, can realize the analysis of multidimensional static target.

An infrared communication end 261 and clock signal input simultaneously also are connected in parallel on the pin of fpga chip 10 connection SD card 26.

RS23230 is and the robot controller general-purpose interface to be convenient to the user and to expand to robot vision processing special module by this interface.

Ethernet interface 31 is selected RJ45 for use, realizes the access of LAN (Local Area Network) by the 1000M Ethernet.

So video coding chip 32 usefulness are converted to simulating signal with the shows signal of numeral, output to projector, display etc., it connects VGA (Video Graphics Array) output terminal 321.

Video decoding chip 33 is used to connect a television decoder (TV DECORDER) 331, and preferred 5H comb television decoder is used to carry out video simulation.

Audio encoding and decoding chip 34 has three pins, connects audio input end 341, audio output 342 and microphone input end 343 respectively.

USB interface chip 35 is used to connect USB device (USB DEVICE) 351 and USB main equipment (USB HOST) 352.

In the utility model preferred embodiment, fpga chip 10 adopts Xilinx V5, it is the FPGA that is specifically designed to digital signal processing, comprises 288 high-speed hardware DSP48E multipliers and high speed, jumbo ram in slice unit, contains 600 ten thousand logical block simultaneously.Owing to adopted FPGA to handle multimedia video and audio stream, can realize to the video/audio lossless process.

In actual applications, the integrated a plurality of interfaces of education developing engine of the present utility model are convenient to the student and are carried out circuit design, and can present the progress and the result of circuit design, have avoided complicated experiment component, and make experimental teaching more directly perceived and lively.

The above only is a better embodiment of the present utility model; protection domain of the present utility model does not exceed with above-mentioned embodiment; as long as the equivalence that those of ordinary skills do according to the utility model institute disclosure is modified or changed, all should include in the protection domain of putting down in writing in claims.

Claims

1. a multimedia FPGA educates developing engine, it is characterized in that: be provided with system programmable logic array fpga chip, the wireless communication interface that different pins with fpga chip connect respectively, Double Data Rate synchronous DRAM, nonvolatile flash memory, display module, imageing sensor, robot controller general-purpose interface, video coding chip, video decoding chip and audio encoding and decoding chip.

2. multimedia FPGA education developing engine as claimed in claim 1, it is characterized in that: fpga chip also connects FPGA dedicated serial config memory, and also being connected with USB simultaneously changes the serial paralled interface control chip, and it can be connected with a download cable.

3. multimedia FPGA education developing engine as claimed in claim 1, it is characterized in that: the fpga chip pin connects a USB interface chip.

4. multimedia FPGA education developing engine as claimed in claim 1, it is characterized in that: described imageing sensor is a cmos sensor.

5. multimedia FPGA education developing engine as claimed in claim 1, it is characterized in that: described video coding chip connects the VGA output terminal.

6. multimedia FPGA education developing engine as claimed in claim 1, it is characterized in that: video decoding chip is used to connect a television decoder.

7. multimedia FPGA education developing engine as claimed in claim 1, it is characterized in that: the pin of fpga chip connects the SD card.