CN202041950U - Anti-collision controller for RS485 bus - Google Patents

Abstract

The utility model provides an anti-collision controller for an RS485 bus. The anti-collision controller comprises a deserializer, a destination address access sequence register, a read back information sequence register, a double-line switch and a discriminatory comparator, wherein the deserializer is used for receiving a destination address sent by a processor and deserializing the destination address to obtain a detection structure; the destination address access sequence register is used for storing the detection structure; the read back information sequence register is used for storing data read back from the bus by the anti-collision controller; the double-line switch is connected between the processor and an RS485 transceiver and used for controlling data transmission therebetween; and the discriminatory comparator is used for comparing contents in both the destination address access sequence register and the read back information sequence register and controlling the on/off of the double-line switch according to the comparison result. The anti-collision controller detects the communication situation of the bus in a real time manner, automatically waits when data transmission is interfered, and starts data transmission once the bus is in the idle state, so that the data throughput is effectively improved and the bus is prevented from collision.

Description

A kind of RS485 bus anti-collision controller

Technical field

The utility model relates to data communication technology, relates in particular to a kind of RS485 bus anti-collision controller.

Background technology

RS485 bus communication technology is the technology that comparative maturity is used, and it mainly uses the RS485 transceiver to send by balance and the mode of differential received is transmitted at the enterprising line data of RS485 bus.

With mode of operation, general RS485 bus working method mainly is a master slave mode, as shown in Figure 1, whole communication bus system is made up of from node (slave 14) a host node (main frame 12) and several, constantly take turns continuous query by host node and whether communication requirement is arranged from node, if have then the RS485 bus control right is given a certain, send from node and to return bus control right at once after finishing from node.

The working method of a kind of in addition in addition " wheel main wheel from ", promptly allow bus control right mode with similar token ring between each node transmit, the node of controlled power becomes host node, other node becomes from node, a node is when sending data, give adjacent node with bus control right, and this node transmits control downwards after handling the communication requirement of this node again.

The RS485 bus is physical medium with the twisted-pair feeder, be operated under the semiduplex communications status, it is synchronization, can only there be a node to become host node and be in transmit status on the bus, other all nodes must be in accepting state, if synchronization has plural node to be in transmit status, will cause the data of all transmit legs to send failure, promptly so-called bus collision.

Two kinds of bus working methods above-mentioned are much having bigger limitation to real-time, Industry Control occasion that reliability requirement is high, main cause be the master-slave mode bus do not have the right of the communication initiated from node, communication each other need be passed through the host node transfer, the right to use of bus is distributed by master unit fully, and each subelement can not capture bus without authorization.If the unit of system is more, the time in one week of master unit circle collection is just very long, can not in time send to master unit during the subelement information change, causes system slow to the reaction treatment speed of catastrophic event.And each node on " wheel main wheel from " mode bus is owing to wait for time the unknown of bus control right, and real-time also can't guarantee.Simultaneously, if the node that obtains token of the host node of master-slave mode or " wheel main wheel from " formula breaks down, the work of whole bus will be paralysed, and risk is too concentrated.

Present problem at the RS485 bus collision, there has been certain methods to handle, wherein arranged occupying of inquiry judging bus on the software, but the resource of system has very big waste, simultaneously, if on the bus and when connecing a lot of RS485 nodes, consider that the time on the computed in software is accurate inadequately, often also can cause communication failure; Also having certain methods in addition is to come testbus by increasing some peripheral circuits, but has changed the electric property of bus, can't satisfy the RS485 bus standard fully, has influenced the running quality of bus.

Summary of the invention

The purpose of this utility model is to provide a kind of RS485 bus anti-collision controller, makes each node all have the right that can initiate to communicate by letter, reduces the chance of sounding conflict simultaneously again as far as possible, improves the data throughout of system.

Technical solutions of the utility model are:

The utility model provides a kind of RS485 bus anti-collision controller, and it comprises:

Deserializer is used for the destination address that receiving processor sends and goes here and there and change the acquisition detecting structure;

Destination address access sequence register is used to store described detecting structure;

Retaking of a year or grade information preface register is used to store the data that RS485 bus anti-collision controller reads back from bus;

The two-wire switch is connected between processor and the RS485 transceiver, control data transmission therebetween;

Differentiate comparer, be used for the content of comparison object address access sequence register and retaking of a year or grade information preface register, and control the break-make of above-mentioned two-wire switch according to comparative result.

Described RS485 bus anti-collision controller, wherein, described detecting structure comprises detection bus field, call conversation/obtain the bus field, bus is waited for field and communication field.

Described RS485 bus anti-collision controller, wherein, described bus waits for that the duration of field equals terminal address and bus waits for that fragment is long-pending.

Described RS485 bus anti-collision controller, wherein, described bus waits for that fragment is 4Bit.

The utility model provides a kind of RS485 bus anti-collision controller, detect in real time by its signal intelligence bus, when the transmission data are interfered, wait for automatically,, can effectively improve data throughout and avoid bus conflict to occur in case the bus free time just begins data transmission.

Description of drawings

Fig. 1 is existing master slave mode RS485 bus structure synoptic diagram;

Fig. 2 is the schematic diagram of the utility model RS485 bus anti-collision controller better embodiment;

Fig. 3 is the synoptic diagram of detecting structure in the utility model better embodiment.

Embodiment

In order to make the purpose of this utility model, technical scheme and advantage clearer,, the utility model is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.

With reference to figure 2, principle of the present utility model is to add a RS485 bus anti-collision controller 30 on the basis of existing processor 22 and RS485 transceiver 24, above-mentioned RS485 bus anti-collision controller 30 can be made of CPLD, come the data of management processor 22 to send and receive by RS485 bus anti-collision controller 30, thereby avoid bus collision.

Described RS485 bus anti-collision controller 30 comprises: deserializer 31, destination address access sequence register 33, retaking of a year or grade information preface register 35, differentiation comparer 37 and two-wire switch 39, described deserializer 31 is used for the address of wanting access destination that receiving processor 22 sends, and goes here and there and changes the detecting structure of a visit of back generation; Described destination address access sequence register 33 is used to store described detecting structure; Described retaking of a year or grade information preface register 35 is used to store the data that RS485 bus anti-collision controller 30 reads back from bus; Described differentiation comparer 37 is used for the content of comparison object address access sequence register 33 and retaking of a year or grade information preface register 35, and according to comparative result control two-wire switch 39; Described two-wire switch is used for the data transmission between processor controls 22 and the RS485 transceiver 24.

Wherein: the RO pin is the reception data output pin of RS485 transceiver 24; The RE pin be RS485 transceiver 24 the reception data enable pin, in the present embodiment, RS485 bus anti-collision controller 30 directly is made as the RE foot control of RS485 transceiver 24 low, make it be in the state that receives data constantly, even if this is when sending data, also receive simultaneously, thereby realized reading back check of data; The DE pin is the transmission data enable pin of RS485 transceiver 24; The DI pin is the input pin of RS485 transceiver 24 data that will send.

The workflow of above-mentioned RS485 bus anti-collision controller 30 is as follows: at first, the destination address that will visit processor 22, go here and there and change the detecting structure that the back produces a visit by deserializer 31, be put in the destination address access sequence register 33; Whether then, read the bus data (can be 8) of certain-length by RS485 bus anti-collision controller 30, differentiating this segment data is 1 entirely, if not, then judging has data in transmission on the bus, continue detecting, up to finding that the data that read all are at 1 o'clock, promptly mean the bus free time; Then,, the data of call targets address are sent on the bus, simultaneously, the data on the bus are read back, be placed in the retaking of a year or grade information sequence register 35 by RS485 bus anti-collision controller 30 call targets addresses; At last, by differentiating the content of comparer 37 comparison object address access sequence registers 33 with retaking of a year or grade information sequence register 35, if situation about fighting for does not appear in the identical bus that just means, bus can be used, differentiate comparer 37 controls this moment and open two-wire switch 37, processor 22 just can communicate on the RS485 bus by RS485 transceiver 24; If destination address access sequence register 33 is inequality with the content of retaking of a year or grade information sequence register 35, illustrate that the data that send out have been subjected to interference on bus, that is to say, there is other terminal also attempting on bus, sending out data, in this case, then carrying out bus by 30 controls of RS485 bus anti-collision controller waits for, the time of waiting for is relevant with the address of this terminal, relevant is calculated as follows: minimum bus of agreement waits for that (the minimum bus is here waited for fragment to fragment earlier, can not be very little, can't resolve the competition of obtaining bus between the different terminals very little, the oversize overlong time waited for of then can causing, bus efficiency is not high, the length of preferred 4 Bit positions), concrete each terminal wait time=the minimum bus of terminal address * waits for fragment, because the terminal address of the time of waiting for itself has relation, and the address of each terminal is inequality, all, in the contention of bus, different terminal requirements was separated from the time, through after waiting for, whether free now by RS485 bus anti-collision controller 30 detection bus again.

With reference to figure 3, the detecting structure of above-mentioned RS485 bus anti-collision controller 30 comprises: detection bus field, call conversation/obtain the bus field, bus is waited for field and communication field, wherein, the representative of detecting field is read bus data, if the bus free time, in the regular hour, on the bus variation that does not have data, can think that bus can use; Call conversation is obtained the representative of bus field during this period of time, and the access sequence that comprises destination address is sent on the bus data on the bus of reading back simultaneously by the form that normal RS485 communicates by letter; Bus wait field represents bus occupied, needs to wait for; Data transmission is normally carried out in the communication field representative.Under normal circumstances, if the RS485 bus is idle, as long as bus files an application just can get access to, this moment, bus waited for that field is empty; When the RS485 bus is busy, then need when waiting for that field arrives, bus wait for.

Should be understood that; the above only is a better embodiment of the present utility model; not in order to limit protection domain of the present utility model; for those of ordinary skills; any modification of being done according to the above description, be equal to and replace and improvement etc., all should be included within the protection domain of the present utility model.

Claims (1)

1. a RS485 bus anti-collision controller is characterized in that, comprising:

Deserializer is used for the destination address that receiving processor sends and goes here and there and change the acquisition detecting structure;

Destination address access sequence register is used to store described detecting structure;

Retaking of a year or grade information preface register is used to store the data that RS485 bus anti-collision controller reads back from bus;

The two-wire switch is connected between processor and the RS485 transceiver, control data transmission therebetween;

Differentiate comparer, be used for the content of comparison object address access sequence register and retaking of a year or grade information preface register, and control the break-make of above-mentioned two-wire switch according to comparative result.

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