CN202041884U - SSD (Steady-state Distribution) control SOC (System on a Chip) chip - Google Patents
SSD (Steady-state Distribution) control SOC (System on a Chip) chip Download PDFInfo
- Publication number
- CN202041884U CN202041884U CN2011200988234U CN201120098823U CN202041884U CN 202041884 U CN202041884 U CN 202041884U CN 2011200988234 U CN2011200988234 U CN 2011200988234U CN 201120098823 U CN201120098823 U CN 201120098823U CN 202041884 U CN202041884 U CN 202041884U
- Authority
- CN
- China
- Prior art keywords
- bus
- controller
- chip
- amba
- control soc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000011159 matrix material Substances 0.000 claims abstract description 14
- 230000002093 peripheral effect Effects 0.000 claims description 23
- LHMQDVIHBXWNII-UHFFFAOYSA-N 3-amino-4-methoxy-n-phenylbenzamide Chemical compound C1=C(N)C(OC)=CC=C1C(=O)NC1=CC=CC=C1 LHMQDVIHBXWNII-UHFFFAOYSA-N 0.000 claims description 19
- 230000005540 biological transmission Effects 0.000 abstract description 2
- 238000004377 microelectronic Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 4
- 238000012795 verification Methods 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Landscapes
- Microcomputers (AREA)
Abstract
The utility model provides an SSD control SOC (System on a Chip) chip, and belongs to the field of microelectronic technological products. The structure of the chip comprises a control logic, external equipment, an AMBAAPB external bus, an AHB-APB bridge, an AMBAAHB system bus, a register controller, an on-chip SRAM/ROM, an SATA auxiliary equipment interface, an intelligent DMA, a bus matrix, an Sdram controller, an Nand flash memory controller and a PRD memory. Compared with the prior art, the chip has the characteristics that the design is reasonable, the use is convenient, the safety of data transmission is improved, and the like.
Description
Technical field
The utility model relates to a kind of microelectric technique product, specifically a kind of SSD control SOC chip.
Background technology
Along with the development of semiconductor process techniques and design tool, more and more Fu Za function is integrated on the single silicon-chip, and SOC (SOC (system on a chip)) produces under the general orientation that integrated system (IS) changes at integrated circuit (IC) just.The appearance of SOC makes integrated circuit develop into integrated system, and the function of whole complete electronic set can be integrated in the chip piece.In the near future, the boundary between integrated circuit and the complete electronic set will thoroughly be broken.SOC is integrated in microprocessor, Simulation with I P nuclear, digital IP kernel and storer on the one chip exactly.SSD is because its storage medium is NandFlash, so it has just had similar advantage to NandFlash: light, storage density is big, low in energy consumption, antidetonation and temperature adaptation wide ranges.But the microelectric technique that the two combination is not arranged at present.
Summary of the invention
Technical assignment of the present utility model is at the deficiencies in the prior art, and a kind of SSD reasonable in design, simple in structure control SOC chip is provided.
The technical scheme that its technical matters that solves the utility model adopts is: comprise SRAM/ROM on steering logic, peripherals, AMBAAPB peripheral bus, AHB-APB bridge, AMBAAHB system bus, register controller, the sheet, SATA slave unit interface, intelligent DMA, bus matrix, Sdram controller, Nand flash controller and PRD storer; SRAM/ROM, AMBA APB peripheral bus and register controller are connected with AMBA AHB system bus respectively on steering logic, intelligent DMA, bus matrix, SATA slave unit interface, the sheet; Peripherals is connected with AMBA APB peripheral bus, and intelligent DMA is connected with bus matrix, and bus matrix is connected with SATA slave unit interface, Sdram controller, Nand flash controller and PRD storer respectively again.
The AMBAAPB peripheral bus is connected with the AMBAAHB system bus by the AHB-APB bridge.
Steering logic is by ARM7, and jtag port and AMBA bus controller are formed.
Peripherals is by house dog, interruptable controller, and power managed, timer, serial ports and GPIO six parts are formed.
Intelligence DMA is made up of 3 road DMA Master.
The Nand flash controller always has 8, and each data channel is supported 8 sheet choosings at most, maximum 64 NandFlash of carry that support.
NandFlash controller (NFC) support hardware 8/12/24bit ECC verification, shared 1 the ECC verification unit of per 2 data passages.NFC includes 4x4KB FIFO, supports SLC/MLC.
The SATA end has an independently PRD storer, the command queue (CMD Queue) that system can put into PRDM with the SATA instruction of resolving, and SATA can be according to the formation situation, and whether decision continues to send instruction, and need not send interruption, thereby avoids interrupting time delay.The NCQ of SATA (Native Command Queue, native command formation) can distinguish according to command content, redistributes instruction sequences, thereby improves read-write efficiency.
Intelligence DMA can will write data, backups among the Sdram by the Sdram controller, after write data reports an error, the Backup Data heavy duty can be guaranteed that data write correctly.
A kind of SSD of the present utility model controls the SOC chip compared with prior art, and the beneficial effect that is produced is:
The write operation intelligent backup is supported in SOC chip support hardware ECC verification, and data transmission security improves a lot.SSD is because its storage medium is NandFlash, so it has just had similar advantage to NandFlash: light, storage density is big, low in energy consumption, antidetonation and temperature adaptation wide ranges.And SSD control SOC chip will have a significant impact the performance tool of SSD.
Description of drawings
Accompanying drawing 1 is a structural representation of the present utility model.
Among the figure, 1, steering logic, 2, peripherals, 3, AMBAAPB peripheral bus, 4, the AHB-APB bridge, 5, AMBA AHB system bus, 6, register controller, 7, SRAM/ROM on the sheet, 8, SATA slave unit interface, 9, intelligent DMA, 10, bus matrix, 11, the Sdram controller, 12, Nand flash controller, 13, PRD storer, 14, DMA Master, 15, jtag port, 16, ARM7,17, AMBA bus, 18, house dog, 19, interruptable controller, 20, power managed, 21, timer, 22, serial ports, 23, GPIO.
Embodiment
Below in conjunction with accompanying drawing the utility model is done following detailed description the in detail.
As shown in drawings, a kind of SSD control SOC chip of the present utility model, its structure comprises SRAM/ROM7, SATA slave unit interface 8, intelligent DMA9, bus matrix 10, Sdram controller 11, Nand flash controller 12 and PRD storer 13 on steering logic 1, peripherals 2, AMBA APB peripheral bus 3, AHB-APB bridge 4, AMBA AHB system bus 5, register controller 6, the sheet; SRAM/ROM7, AMBA APB peripheral bus 3 and register controller 6 are connected with AMBA AHB system bus 5 respectively on steering logic 1, intelligent DMA9, bus matrix 10, SATA slave unit interface 8, the sheet; Peripherals 2 is connected with AMBA APB peripheral bus 3, and intelligent DMA9 is connected with bus matrix 10, and bus matrix 10 is connected with SATA slave unit interface 8, Sdram controller 11, Nand flash controller 12 and PRD storer 13 respectively again.
AMBA APB peripheral bus 3 is connected with AMBA AHB system bus 5 by AHB-APB bridge 4.
Intelligence DMA9 is made up of 3 road DMA Master14.
Nand flash controller 12 always has 8.
Except that the described technical characterictic of instructions, be those skilled in the art's known technology.
Claims (6)
1. a SSD control SOC chip is characterized in that comprising SRAM/ROM, SATA slave unit interface, intelligent DMA, bus matrix, Sdram controller, Nand flash controller and PRD storer on steering logic, peripherals, AMBA APB peripheral bus, AHB-APB bridge, AMBA AHB system bus, register controller, the sheet; SRAM/ROM, AMBA APB peripheral bus and register controller are connected with AMBA AHB system bus respectively on steering logic, intelligent DMA, bus matrix, SATA slave unit interface, the sheet; Peripherals is connected with AMBA APB peripheral bus, and intelligent DMA is connected with bus matrix, and bus matrix is connected with SATA slave unit interface, Sdram controller, Nand flash controller and PRD storer respectively again.
2. a kind of SSD control SOC chip according to claim 1 is characterized in that the AMBAAPB peripheral bus is connected with the AMBAAHB system bus by the AHB-APB bridge.
3. a kind of SSD control SOC chip according to claim 1 is characterized in that steering logic by ARM7, and jtag port and AMBA bus controller are formed.
4. a kind of SSD control SOC chip according to claim 1 is characterized in that peripherals by house dog, interruptable controller, and power managed, timer, serial ports and GPIO six parts are formed.
5. a kind of SSD control SOC chip according to claim 1 is characterized in that intelligent DMA is made up of 3 road DMA Master.
6. a kind of SSD control SOC chip according to claim 1 is characterized in that the Nand flash controller always has 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011200988234U CN202041884U (en) | 2011-04-07 | 2011-04-07 | SSD (Steady-state Distribution) control SOC (System on a Chip) chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011200988234U CN202041884U (en) | 2011-04-07 | 2011-04-07 | SSD (Steady-state Distribution) control SOC (System on a Chip) chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202041884U true CN202041884U (en) | 2011-11-16 |
Family
ID=44969321
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011200988234U Expired - Fee Related CN202041884U (en) | 2011-04-07 | 2011-04-07 | SSD (Steady-state Distribution) control SOC (System on a Chip) chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202041884U (en) |
-
2011
- 2011-04-07 CN CN2011200988234U patent/CN202041884U/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103412990B (en) | A kind of multi-level collaborative low-power design method | |
| CN203311856U (en) | Parallel burner circuit and burner | |
| CN104182010A (en) | Rack based on data-switch data transmission | |
| CN202205050U (en) | Core board for protecting and controlling electric system | |
| CN203838697U (en) | Solid-state disc device based on DDR interface | |
| CN209103281U (en) | Integrated multi-bus interface module based on pci interface | |
| CN107861565A (en) | Computer control system based on Loongson processor | |
| CN102096559B (en) | Method for improving data transmission efficiency of SATA interface solid state disk | |
| Kogge et al. | Yearly update: exascale projections for 2013. | |
| CN204166522U (en) | A kind of high-speed high capacity FLASH veneer memory circuit plate | |
| CN202041884U (en) | SSD (Steady-state Distribution) control SOC (System on a Chip) chip | |
| CN202583967U (en) | LBE (Location Based Entertainment) bus monoboard computer based on processor MPC5200B | |
| CN202583964U (en) | Multibus-compatible embedded military computer module | |
| CN207367196U (en) | A kind of Portable computer main board and portable computer based on Feiteng processor | |
| CN207516997U (en) | A kind of outband management module that NVMe SSD are carried out using CPLD | |
| CN203759601U (en) | Industrial computer mainboard | |
| Huang et al. | SmartBackup: An efficient and reliable backup strategy for solid state drives with backup capacitors | |
| CN205656615U (en) | Treater based on MPC824x provides generic interface | |
| CN204945694U (en) | A kind of core board based on Godson GSC3280 SOC (system on a chip) | |
| CN201134097Y (en) | SOC chip integrated with IP cores of RAID and SAS control | |
| CN205942532U (en) | Embedded computer module | |
| CN205003669U (en) | B3G test platform's data transmission system | |
| CN205193779U (en) | RAID card based on multi -path server | |
| CN203480375U (en) | Core board | |
| CN202217205U (en) | Main board of network safety device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111116 Termination date: 20140407 |