CN202033558U - LCD panel - Google Patents
LCD panel Download PDFInfo
- Publication number
- CN202033558U CN202033558U CN2011201363095U CN201120136309U CN202033558U CN 202033558 U CN202033558 U CN 202033558U CN 2011201363095 U CN2011201363095 U CN 2011201363095U CN 201120136309 U CN201120136309 U CN 201120136309U CN 202033558 U CN202033558 U CN 202033558U
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- Prior art keywords
- boss
- display panels
- cylindrical spacer
- ito electrode
- base palte
- Prior art date
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- Expired - Lifetime
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Abstract
The utility model provides an LCD panel, which comprises an array substrate, a color film substrate and a columnar isolation pad arranged between the array substrate and the color film substrate, wherein first bosses are arranged on the array substrate; a groove for limiting the columnar isolation pad from displacement is formed on the first bosses; and the first end of the columnar isolation pad is arranged on the color film substrate and the second end of the columnar isolation pad is inserted into the groove. By adopting the LCD panel provided by the utility model, the columnar isolation pad can be effectively prevented from displacement, so that the thickness and the uniformity of a liquid crystal layer between the array substrate and the color film substrate are under control, and the problem of the non-uniform display of the LCD panel resulted from the change of the thickness and the uniformity of the liquid crystal layer is avoided.
Description
Technical field
The utility model relates to the display technique field, especially designs a kind of display panels.
Background technology
Existing display panels comprises two substrates: color film (CF) substrate and array (Array) substrate are provided with the liquid crystal layer that liquid crystal material is formed between the two substrates.The thickness of liquid crystal layer and homogeneity can influence the performance of display panels, for thickness and the homogeneity of controlling liquid crystal layer, as shown in Figure 1, cylindrical spacer (PS) are set between color membrane substrates and array base palte usually in the prior art.One end of cylindrical spacer is connected on the color membrane substrates, and the other end is pressed on the array base palte, to keep the spacing between color membrane substrates and the array base palte.
Above-mentioned display panels has following shortcoming: when display panels is subjected to the external force extruding or bounces, cylindrical spacer can be subjected to displacement between color membrane substrates and array base palte, thereby make the thickness of liquid crystal layer and homogeneity change, cause display panels brightness to show uneven (touch mura).
The utility model content
In view of this, the utility model provides a kind of display panels, can stop the displacement of cylindrical spacer.
For addressing the above problem, the utility model provides a kind of display panels, comprise: comprise array base palte, color membrane substrates and be arranged at described array base palte and described color membrane substrates between cylindrical spacer, it is characterized in that, described array base palte is provided with first boss, have a groove that is used to limit described cylindrical spacer displacement on described first boss, first end of described cylindrical spacer is arranged on the described color membrane substrates, and second end is inserted in the described groove.
Preferably, described array base palte is made up of glass substrate, ground floor ITO electrode, gate electrode, first insulation course, semiconductor layer, signal electrode, second insulation course and second layer ITO electrode.
Preferably, described first boss is: the projection that forms in ground floor ITO electrode manufacturing process is covered formed boss by other each layers after the described ground floor ITO electrode.
Preferably, described first boss is: the boss that forms in second layer ITO electrode manufacturing process.
Preferably, also be provided with one second boss in the described groove, second end of described cylindrical spacer is pressed on described second boss.
Preferably, described second boss is arranged at the center of described groove.
Preferably, the cross sectional dimensions of described second boss is less than the cross sectional dimensions of second end of described cylindrical spacer.
Preferably, the height of described second boss matches with the height of described cylindrical spacer.
Preferably, described second boss is: the projection that forms in ground floor ITO electrode manufacturing process is covered formed boss by other each layers after the described ground floor ITO electrode.
Preferably, described second boss is: the boss that forms in second layer ITO electrode manufacturing process.
Preferably, the height of described second boss is lower than the height of described first boss.
Preferably, second end of described cylindrical spacer is a terraced structure, has first step and second step, and wherein, described first step and described second boss offset, and described second step is corresponding with first boss but do not contact.
The utlity model has following beneficial effect:
Can effectively stop the displacement of cylindrical spacer, thus the thickness of the liquid crystal layer between array of controls substrate and the color membrane substrates and homogeneity avoid changing because of the thickness and the homogeneity of liquid crystal layer, cause display panels brightness to show uneven problem.
Description of drawings
Fig. 1 is the diagrammatic cross-section of display panels of the prior art;
Fig. 2 is a diagrammatic cross-section of display panels of the present utility model;
Fig. 3 is another diagrammatic cross-section of display panels of the present utility model;
Fig. 4 is an embodiment of array base palte of the present utility model;
Fig. 5 is another embodiment of array base palte of the present utility model.
Embodiment
Below in conjunction with drawings and Examples, embodiment of the present utility model is described in further detail.
Please refer to Fig. 2, Fig. 2 is a diagrammatic cross-section of display panels of the present utility model, described display panels comprises: array base palte 201, color membrane substrates 202 and be arranged at cylindrical spacer 203 between described array base palte 201 and the described color membrane substrates 202, described cylindrical spacer 203 can be a straight cylinder, can be the awl cylinder.Described cylindrical spacer 203 has first end and second end, generally first end is called the bottom, second end is called the top, and when described cylindrical spacer 203 was the awl cylinder, the cross sectional dimensions of the bottom of described cylindrical spacer 203 was greater than the cross sectional dimensions on its top.And described chock insulator matter can also be that the top is the shape that step-like cylinder waits (comprising straight cylinder and awl cylinder) other suitable anti-sliding stops.
In order to reach the purpose that stops described cylindrical spacer 203 displacements, in the utility model, first boss 2011 can be set on described array base palte 201, have a groove 20111 that is used to limit described cylindrical spacer 203 displacements on described first boss 2011, the position of described first boss 2011 is corresponding with the position of described cylindrical spacer 203.First end of described cylindrical spacer 203 is arranged on the described color membrane substrates 202, generally, first end of described cylindrical spacer 203 is to fixedly connected with described color membrane substrates 202, second end of described cylindrical spacer 203 is inserted in the groove 20111 of described first boss 2011, the shape of described groove 20111 matches with the shape of second end of described cylindrical spacer 203, to limit the displacement of described cylindrical spacer 203 preferably, thereby control the thickness and the homogeneity of the liquid crystal layer between described array base palte 201 and the described color membrane substrates 202, avoid changing, cause display panels brightness to show uneven problem because of the thickness and the homogeneity of liquid crystal layer.
Described array base palte 201 is made up of glass substrate, ground floor ITO (Indium-Tin Oxide, tin indium oxide) electrode, gate electrode (Gate), first insulation course, semiconductor layer, signal electrode, second insulation course and second layer ITO electrode usually.In the utility model, described first boss 2011 can be the projection that forms in ground floor ITO electrode manufacturing process, by the formed boss of other each layers coverings after the described ground floor ITO electrode.In addition, described first boss 2011 also can be the boss that forms in second layer ITO electrode manufacturing process.
The shape of the xsect of described cylindrical spacer 203 may be circle, quadrilateral or other polygons, in order to secure the above cylindrical spacer 203 better, the shape of the xsect of described groove 20111 is identical with the shape of the xsect of described cylindrical spacer 203, for instance, when the xsect of described cylindrical spacer 203 be shaped as circle the time, the shape of the xsect of described groove 2011 also is circular.The shape of described first boss 2011 is not limit, it can be the right cylinder boss, also can be square boss, rectangular parallelepiped boss etc., when described first boss 2011 is the right cylinder boss, when the shape of the xsect of described groove 2011 was circle, being shaped as of the xsect of described first boss was one circular.
In order to strengthen control ability to the displacement of described cylindrical spacer 203, as shown in Figure 3, one second boss 2012 can also be set in the groove 20111 of described first boss 2011, second end of described cylindrical spacer 203 is pressed on described second boss 2012, preferably, described second boss 2012 is arranged at the center of described groove 20111, the height of described second boss 2031 need match with the height of described cylindrical spacer 203, be that described cylindrical spacer just in time offsets with second boss, be in and keep the thick optimum condition of box.
The cross sectional dimensions of described second boss 2012 usually need be less than the cross sectional dimensions of second end of described cylindrical spacer 203, thereby after second end of described cylindrical spacer 203 is pressed on described second boss 2012, can be so that described cylindrical spacer 203 forms the miniature deformation of depression to the inside, to strengthen control ability, prevent that described cylindrical spacer 203 is subjected to displacement to the displacement of described cylindrical spacer 203.
In order to strengthen the control ability to the displacement of described cylindrical spacer 203, the height of described second boss 2031 is lower than the height of described first boss.
Identical with described first boss 2011, described second boss 2012 can be the projection that forms in ground floor ITO electrode manufacturing process, by the formed boss of other each layers coverings after the described ground floor ITO electrode, also can be the boss that in second layer ITO electrode manufacturing process, forms.
Be illustrated in figure 4 as an embodiment of array base palte of the present utility model, the manufacturing process of described array base palte is as follows: when ground floor ITO electrode mask (Mask), reeded annular round platform in making, make gate electrode, insulation course, semiconductor layer, signal electrode, insulation course etc. then successively, in addition, when second layer ITO electrode mask, in annular round platform, form a little round platform, after each layer making finishes, final described first boss 2011, described second boss 2012 of the final formation of described little round platform of forming of above-mentioned annular round platform.When array base palte and color membrane substrates during to box, the top of the cylindrical spacer on the color membrane substrates can be pressed on described second boss 2012, one to the inside miniature deformation can take place in cylindrical spacer, thereby certain restriction is played in the displacement of cylindrical spacer, by the cooperation of first boss 2011 outside the cylindrical spacer, further limit the displacement of cylindrical spacer in addition.
Fig. 5 is another embodiment of the array base palte of the utility model embodiment, wherein, described array base palte comprises successively: glass substrate 501, ground floor ITO electrode 502, gate electrode 503, insulation course 504 and second claim the ITO electrode 505 (other each layers are not shown), when ground floor ITO electrode 502 masks (Mask), make a little round platform, when second layer ITO electrode 505 masks, make reeded annular round platform in, after each layer making finishes, final described first boss 2011, described second boss 2012 of the final formation of above-mentioned little round platform of forming of above-mentioned annular round platform.
Need to prove, in some cases, have two types cylindrical spacer in the described display panels, principal post shape chock insulator matter and auxilliary cylindrical spacer, the height of auxilliary cylindrical spacer is less than the height of principal post shape chock insulator matter, its bottom is connected with described color membrane substrates, and the cylindrical spacer in the foregoing description typically refers to principal post shape chock insulator matter.Certainly, the chock insulator matter that uses that matches with above-mentioned first boss and second boss also can be a kind of chock insulator matter that has main chock insulator matter and auxilliary chock insulator matter function concurrently, can be step-like structure such as this chock insulator matter top (refer to contact an end) with array base palte, have first step and second step, first step (referring to that chock insulator matter is near a step of array) props up second boss, second step is corresponding to first boss, but (only just contacting with first boss when liquid crystal panel is under pressure, thick to keep box better) usually do not contact with first boss under the state.What the first step of chock insulator matter play a part at this moment is main chock insulator matter, and what second step then play a part is auxilliary chock insulator matter.
The above only is a preferred implementation of the present utility model; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.
Claims (12)
1. display panels, comprise array base palte, color membrane substrates and be arranged at described array base palte and described color membrane substrates between cylindrical spacer, it is characterized in that, described array base palte is provided with first boss, has a groove that is used to limit described cylindrical spacer displacement on described first boss, first end of described cylindrical spacer is arranged on the described color membrane substrates, and second end is inserted in the described groove.
2. display panels as claimed in claim 1 is characterized in that, described array base palte is made up of glass substrate, ground floor ITO electrode, gate electrode, first insulation course, semiconductor layer, signal electrode, second insulation course and second layer ITO electrode.
3. display panels as claimed in claim 2 is characterized in that, described first boss is: the projection that forms in ground floor ITO electrode manufacturing process is covered formed boss by other each layers after the described ground floor ITO electrode.
4. display panels as claimed in claim 2 is characterized in that, described first boss is: the boss that forms in second layer ITO electrode manufacturing process.
5. as claim 3 or 4 described display panels, it is characterized in that also be provided with one second boss in the described groove, second end of described cylindrical spacer is pressed on described second boss.
6. display panels as claimed in claim 5 is characterized in that described second boss is arranged at the center of described groove.
7. display panels as claimed in claim 5 is characterized in that, the cross sectional dimensions of described second boss is less than the cross sectional dimensions of second end of described cylindrical spacer.
8. display panels as claimed in claim 5 is characterized in that, the height of described second boss matches with the height of described cylindrical spacer.
9. display panels as claimed in claim 5 is characterized in that, described second boss is: the projection that forms in ground floor ITO electrode manufacturing process is covered formed boss by other each layers after the described ground floor ITO electrode.
10. display panels as claimed in claim 5 is characterized in that, described second boss is: the boss that forms in second layer ITO electrode manufacturing process.
11. display panels as claimed in claim 5 is characterized in that, the height of described second boss is lower than the height of described first boss.
12. display panels as claimed in claim 5, it is characterized in that, second end of described cylindrical spacer is a terraced structure, have first step and second step, wherein, described first step and described second boss offset, and described second step is corresponding with described first boss but do not contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201363095U CN202033558U (en) | 2011-05-03 | 2011-05-03 | LCD panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201363095U CN202033558U (en) | 2011-05-03 | 2011-05-03 | LCD panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202033558U true CN202033558U (en) | 2011-11-09 |
Family
ID=44895851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011201363095U Expired - Lifetime CN202033558U (en) | 2011-05-03 | 2011-05-03 | LCD panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202033558U (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102998852A (en) * | 2012-12-10 | 2013-03-27 | 京东方科技集团股份有限公司 | Cushion isolating material, liquid crystal panel, liquid crystal display device and preparation method of cushion isolating material |
| CN102998851A (en) * | 2012-12-05 | 2013-03-27 | 京东方科技集团股份有限公司 | Liquid crystal display panel and display device |
| CN103034012A (en) * | 2012-12-14 | 2013-04-10 | 京东方科技集团股份有限公司 | Three-dimensional(3D) display module, liquid crystal lens and preparation method for liquid crystal lens |
| CN104035239A (en) * | 2014-05-08 | 2014-09-10 | 京东方科技集团股份有限公司 | Substrate and display device |
| CN104483784A (en) * | 2015-01-06 | 2015-04-01 | 京东方科技集团股份有限公司 | Display panel, manufacturing method of display panel and display device |
| CN104793406A (en) * | 2015-04-29 | 2015-07-22 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display |
| WO2016065851A1 (en) * | 2014-10-27 | 2016-05-06 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display device |
| CN105807507A (en) * | 2016-05-26 | 2016-07-27 | 京东方科技集团股份有限公司 | Display panel and manufacturing method thereof and display device |
| CN105929607A (en) * | 2016-07-04 | 2016-09-07 | 京东方科技集团股份有限公司 | Liquid crystal display panel and manufacturing method thereof as well as display device |
| CN106483718A (en) * | 2015-08-26 | 2017-03-08 | 株式会社日本显示器 | Display device |
| CN106802517A (en) * | 2017-04-12 | 2017-06-06 | 京东方科技集团股份有限公司 | A kind of liquid crystal display panel and display device |
| CN107255879A (en) * | 2017-08-01 | 2017-10-17 | 京东方科技集团股份有限公司 | A kind of array base palte, display panel and display device |
| CN109976046A (en) * | 2019-04-08 | 2019-07-05 | 深圳市华星光电技术有限公司 | Liquid crystal display panel |
| CN113960839A (en) * | 2021-10-20 | 2022-01-21 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof and display device |
-
2011
- 2011-05-03 CN CN2011201363095U patent/CN202033558U/en not_active Expired - Lifetime
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102998851B (en) * | 2012-12-05 | 2016-01-06 | 京东方科技集团股份有限公司 | A kind of display panels and display device |
| CN102998851A (en) * | 2012-12-05 | 2013-03-27 | 京东方科技集团股份有限公司 | Liquid crystal display panel and display device |
| CN102998852A (en) * | 2012-12-10 | 2013-03-27 | 京东方科技集团股份有限公司 | Cushion isolating material, liquid crystal panel, liquid crystal display device and preparation method of cushion isolating material |
| CN103034012A (en) * | 2012-12-14 | 2013-04-10 | 京东方科技集团股份有限公司 | Three-dimensional(3D) display module, liquid crystal lens and preparation method for liquid crystal lens |
| CN103034012B (en) * | 2012-12-14 | 2015-06-03 | 京东方科技集团股份有限公司 | Three-dimensional(3D) display module, liquid crystal lens and preparation method for liquid crystal lens |
| CN104035239A (en) * | 2014-05-08 | 2014-09-10 | 京东方科技集团股份有限公司 | Substrate and display device |
| US9488873B2 (en) | 2014-05-08 | 2016-11-08 | Boe Technology Group Co., Ltd. | Substrate and display device |
| US9897863B2 (en) | 2014-10-27 | 2018-02-20 | Boe Technology Group Co., Ltd. | Array substrate, display panel and display apparatus having recesses on data lines or gate lines |
| WO2016065851A1 (en) * | 2014-10-27 | 2016-05-06 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display device |
| CN104483784A (en) * | 2015-01-06 | 2015-04-01 | 京东方科技集团股份有限公司 | Display panel, manufacturing method of display panel and display device |
| CN104793406A (en) * | 2015-04-29 | 2015-07-22 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display |
| CN106483718B (en) * | 2015-08-26 | 2019-09-10 | 株式会社日本显示器 | Display device |
| CN106483718A (en) * | 2015-08-26 | 2017-03-08 | 株式会社日本显示器 | Display device |
| CN105807507B (en) * | 2016-05-26 | 2019-07-26 | 京东方科技集团股份有限公司 | Display panel and preparation method thereof and display device |
| CN105807507A (en) * | 2016-05-26 | 2016-07-27 | 京东方科技集团股份有限公司 | Display panel and manufacturing method thereof and display device |
| US10768489B2 (en) | 2016-05-26 | 2020-09-08 | Boe Technology Group Co., Ltd. | Display panel with spacers and walls for the spacers, manufacturing method thereof and display device |
| CN105929607A (en) * | 2016-07-04 | 2016-09-07 | 京东方科技集团股份有限公司 | Liquid crystal display panel and manufacturing method thereof as well as display device |
| CN106802517A (en) * | 2017-04-12 | 2017-06-06 | 京东方科技集团股份有限公司 | A kind of liquid crystal display panel and display device |
| US10656472B2 (en) | 2017-04-12 | 2020-05-19 | Boe Technology Group Co., Ltd. | Liquid crystal display panel and display device |
| CN107255879A (en) * | 2017-08-01 | 2017-10-17 | 京东方科技集团股份有限公司 | A kind of array base palte, display panel and display device |
| CN109976046A (en) * | 2019-04-08 | 2019-07-05 | 深圳市华星光电技术有限公司 | Liquid crystal display panel |
| CN113960839A (en) * | 2021-10-20 | 2022-01-21 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof and display device |
| CN113960839B (en) * | 2021-10-20 | 2023-10-20 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof and display device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20111109 |