CN202004747U - BiCMOS (bipolar complementary metal oxide semiconductor) sampling retaining circuit - Google Patents
BiCMOS (bipolar complementary metal oxide semiconductor) sampling retaining circuit Download PDFInfo
- Publication number
- CN202004747U CN202004747U CN2010206791649U CN201020679164U CN202004747U CN 202004747 U CN202004747 U CN 202004747U CN 2010206791649 U CN2010206791649 U CN 2010206791649U CN 201020679164 U CN201020679164 U CN 201020679164U CN 202004747 U CN202004747 U CN 202004747U
- Authority
- CN
- China
- Prior art keywords
- triode
- current switch
- emitter
- base stage
- buffer stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Electronic Switches (AREA)
Abstract
The utility model relates to a BiCMOS (bipolar complementary metal oxide semiconductor) sampling retaining circuit, comprising an input buffer stage for receiving a first input signal and a second input signal; a first output buffer stage and a second output buffer stage which are respectively connected with the input buffer stage and are used for outputting a first output signal and a second output signal respectively; a first sampling capacitor, a first current switch, a second current switch and a third current switch which are connected between the input buffer stage and the second output buffer stage in parallel, as well as a second sampling capacitor, a fourth current switch, a fifth current switch and a sixth current switch which are connected between the input buffer stage and the first output buffer stage, and all the current switches are NMOS (N-channel metal oxide semiconductor) tubes. The BiCMOS has the advantages of bipolar circuit rapid, low input offset voltage and high current driving capacity, and has the characteristics of low power consumption and high integrated level of a CMOS (complementary metal-oxide-semiconductor) circuit, so as to meet the working requirements of a high-speed high-precision ADC (analog to digital converter) chip, thereby being widely applied to the design of a high-speed A/D converter module and an IP (intellectual property) core.
Description
Technical field
The utility model relates to integrated circuit, relates in particular to a kind of BiCMOS (Bipolar CMOS, ambipolar CMOS) sampling hold circuit.
Background technology
As everyone knows, sampling hold circuit is the important component part in the A/D converter, and its effect is that the analog signal sampling maintenance of outside input is handled, and we can say that the speed of sampling hold circuit has directly determined the switching rate of whole A/D converter.
In the two-step A/D converter, often adopt and penetrate a grade follower switch sampling maintenance amplifying circuit.Typically penetrate structure that the sampling of grade follower switch keeps amplifying circuit as shown in Figure 1, output buffer stage, first, second sampling capacitance C that this sampling maintenance amplifying circuit mainly comprises the input buffering level be made up of first to fourth triode Q1 to Q4, is made up of the 8th, the 9th triode Q8, Q9 and the 14, the 15 triode Q14, Q15
H1, C
H2And first to the 6th current switch T1 to T6; Wherein, first, second triode Q1, Q2 penetrate grade follower as the cascade that links to each other with input and can reduce from the transient current of importing, first to the 6th current switch T1 to T6 is the triode of NPN structure, and first, second current switch T1, T2 and the 4th, the 5th current switch T4, T5 link to each other, be all sampling clock, the 3rd current switch T3 links to each other with the 6th current switch T6, is all the maintenance clock.The sequential of two clocks as shown in Figure 3, in sample phase, the first current switch T1 and the 4th current switch T4 conducting, the current source that is connected on the 5th, the 11 triode Q5, the Q11 turn-offs, the first input signal VIN1 and the second input signal VIN2 by input buffering level and the 5th, the 11 triode Q5, Q11 with charge storage at first, second sampling capacitance C
H1, C
H2On; In the maintenance stage, first, second current switch T1, T2 and the 4th, the 5th current switch T4, T5 turn-off, and the 3rd current switch T3 and the 6th current switch T6 conducting are stored in first, second sampling capacitance C
H1, C
H2Electric charge export by output buffer.
But in above-mentioned sampling hold circuit, the switching characteristic of being made of bipolar switch first to the 6th current switch T1 to T6 is poor, makes the speed of whole sampling hold circuit descend, thereby directly influences and limiting the speed of A/D converter; In addition, in the 5th, the 6th triode Q5, Q6 conducting moment, the first output signal Vo1 and the second output signal Vo2 have a bigger shake.Therefore, thisly penetrate the sampling of grade follower switch and keep amplifying circuit more and more can not adapt to the job requirement of high-speed a/d converter.
The utility model content
In order to solve the problem that above-mentioned prior art exists, the utility model aims to provide a kind of BiCMOS sampling hold circuit, realizing switching characteristic preferably, thereby effectively improves the speed of service of sampling hold circuit.
A kind of BiCMOS sampling hold circuit described in the utility model, it comprises that one is used to receive first, the input buffering level of second input signal, that be connected with this input buffering level respectively and be respectively applied for output first, first of second output signal, the second output buffer stage, be connected in first sampling capacitance and first to the 3rd current switch between the described input buffering level and the second output buffer stage in parallel and be connected in described input buffering level in parallel and first second sampling capacitance and the 4th to the 6th current switch of exporting between the buffer stage, described input buffering level comprises first triode of series connection and second triode and the 4th triode of the 3rd triode and series connection, wherein, the emitter of described first triode and second triode is connected back ground connection, the base stage and the collector electrode of described the 3rd triode and the 4th triode are connected to an external power source, described first to the 6th current switch is the NMOS pipe, the source electrode of described first to the 3rd current switch ground connection that links to each other, and first, the grid of second current switch links to each other, the source electrode of described the 4th to the 6th current switch ground connection that links to each other, and the 4th, the grid of the 5th current switch links to each other.
In above-mentioned BiCMOS sampling hold circuit, described circuit also comprises first, second electric capacity, one end of described first electric capacity is connected with the collector electrode of described first triode, the other end is connected between described second sampling capacitance and the first output buffer stage, one end of described second electric capacity is connected with the collector electrode of described second triode, and the other end is connected between described first sampling capacitance and the second output buffer stage.
In above-mentioned BiCMOS sampling hold circuit, the described first output buffer stage comprises the 8th triode and the 9th triode, the collector electrode of described the 8th, the 9th triode is connected to described external power source, the base stage of described the 8th triode is connected with the emitter of one the 5th triode, and be connected to the collector electrode of described second triode by the base stage of the 5th triode, the emitter of the 8th triode is connected with the base stage of described the 9th triode, the grounded emitter of the 9th triode, and the collector electrode of described the 5th triode is connected with described external power source;
The described second output buffer stage comprises the 14 triode and the 15 triode, collector electrode described the 14, the 15 triode is connected to described external power source, the base stage of described the 14 triode is connected with the emitter of 1 the 11 triode, and be connected to the collector electrode of described first triode by the base stage of the 11 triode, the emitter of the 14 triode is connected with the base stage of described the 15 triode, the grounded emitter of the 15 triode, and the collector electrode of described the 11 triode is connected with described external power source;
One end of described first sampling capacitance is connected with the base stage of described the 14 triode, and the other end is connected with described external power source; One end of described second sampling capacitance is connected with the base stage of described the 8th triode, and the other end is connected with described external power source;
The drain electrode of described first current switch is connected with the emitter of described the 14 triode, the drain electrode of described second current switch is connected with the emitter of described the 11 triode, the drain electrode of described the 3rd current switch is connected with the base stage of described the 11 triode, the drain electrode of described the 4th current switch is connected with the emitter of described the 8th triode, the drain electrode of described the 5th current switch is connected with the emitter of described the 5th triode, and the drain electrode of described the 6th current switch is connected with the base stage of described the 5th triode.
In above-mentioned BiCMOS sampling hold circuit, the other end of described first electric capacity is connected with the base stage of described the 8th triode, and the other end of described second electric capacity is connected with the base stage of described the 14 triode.
In above-mentioned BiCMOS sampling hold circuit, the emitter of described the 3rd triode is connected with the collector electrode of described first triode by a resistance, the emitter of described the 4th triode is connected with the collector electrode of described second triode by a resistance, described first, the emitter of second triode links to each other after respectively connecting a resistance, and by a current source ground connection, the source electrode of described first to the 3rd current switch links to each other the back by a current source ground connection, the source electrode of described the 4th to the 6th current switch links to each other the back by a current source ground connection, the described the 9th, the emitter of the 15 triode is respectively by a current source ground connection.
In above-mentioned BiCMOS sampling hold circuit, the base stage of described first triode receives described first input signal, the base stage of described second triode receives described second input signal, the emitter of described the 9th triode is exported described first output signal, and the emitter of described the 15 triode is exported described second output signal.
Owing to adopted above-mentioned technical solution, the utility model has replaced traditional ambipolar current switch of being made up of triode by the current switch that adopts the NMOS form of tubes, only need the source electrode and the drain electrode of NMOS pipe are exchanged, can when transmission current, realize transmitted in both directions, therefore realize switching characteristic preferably, thereby improved the speed of sampling hold circuit; In addition, for in sample phase in the transfer process that keeps the stage, prevent because the 5th, the crossing fast motion of the 11 triode and output signal is caused big shake, therefore, the utility model has been set up first, second electric capacity, with reduce the 5th, the opening speed of the 11 triode, and the maintenance stage in the transfer process of sample phase, reduced the transient current from input, simultaneously, first, second electric capacity can also be used to compensated input signal feedthrough effect.
Description of drawings
Fig. 1 penetrates the schematic diagram that grade follower switch sampling keeps amplifying circuit in the prior art;
Fig. 2 is the schematic diagram of a kind of BiCMOS sampling hold circuit of the utility model;
Fig. 3 is the switching sequence figure of a kind of BiCMOS sampling hold circuit of the utility model.
Embodiment
Below in conjunction with accompanying drawing, specific embodiment of the utility model is elaborated.
As shown in Figure 2, the utility model, promptly a kind of BiCMOS sampling hold circuit, it comprises an input buffering level 1, the first output buffer stage 2, the second output buffer stage 3, the first sampling capacitance C
H1, the second sampling capacitance C
H2, first capacitor C 1, second capacitor C 2 and first to the 6th current switch M1 to M6, wherein, first to the 6th current switch M1 to M6 is the NMOS pipe.
The first output buffer stage 2 comprises the 8th triode Q8 and the 9th triode Q9, wherein, eight, the collector electrode of the 9th triode Q8, Q9 is connected to external power source VCC, the base stage of the 8th triode Q8 is connected with the emitter of one the 5th triode Q5, and be connected to the collector electrode of the second triode Q2 by the base stage of the 5th triode Q5, the emitter of the 8th triode Q8 is connected with the base stage of the 9th triode Q9, the emitter of the 9th triode Q9 is exported the first output signal Vo1, and by a current source Is ground connection, the collector electrode of the 5th triode Q5 is connected with external power source VCC.
The second output buffer stage 3 comprises the 14 triode Q14 and the 15 triode Q15, wherein, the 14, the 15 triode Q14, the collector electrode of Q15 is connected to external power source VCC, the base stage of the 14 triode Q14 is connected with the emitter of 1 the 11 triode Q11, and be connected to the collector electrode of the first triode Q1 by the base stage of the 11 triode Q11, the emitter of the 14 triode Q14 is connected with the base stage of the 15 triode Q15, the emitter of the 15 triode Q15 is exported the second output signal Vo2, and by a current source Is ground connection, the collector electrode of the 11 triode Q11 is connected with external power source VCC.
The first sampling capacitance C
H1An end be connected with the base stage of the 14 triode Q14, the other end is connected with external power source VCC; The second sampling capacitance C
H2An end be connected with the base stage of the 8th triode Q8, the other end is connected with external power source VCC.
One end of first capacitor C 1 is connected with the collector electrode of the first triode Q1, and the other end is connected with the base stage of the 8th triode Q8; One end of second capacitor C 2 is connected with the collector electrode of the second triode Q2, and the other end is connected with the base stage of the 14 triode Q14.
The source electrode of first to the 3rd current switch M1 to M3 links to each other the back by a current source Is ground connection, the grid of first, second current switch M1, M2 links to each other, the drain electrode of the first current switch M1 is connected with the emitter of the 14 triode Q14, the drain electrode of the second current switch M2 is connected with the emitter of the 11 triode Q11, and the drain electrode of the 3rd current switch M3 is connected with the base stage of the 11 triode Q11; The source electrode of the 4th to the 6th current switch M4 to M6 links to each other the back by a current source Is ground connection, four, the grid of the 5th current switch M4, M5 links to each other, the drain electrode of the 4th current switch M4 is connected with the emitter of the 8th triode Q8, the drain electrode of the 5th current switch M5 is connected with the emitter of the 5th triode Q5, and the drain electrode of the 6th current switch M6 is connected with the base stage of the 5th triode Q5.
In the utility model, first, second triode Q1, Q2 penetrate grade follower as the cascade that links to each other with input signal and can reduce from the transient current of importing; First, second current switch M1, the M2 and the 4th that links to each other, the grid voltage V of the 5th current switch M4, M5
T, be all sampling clock, the grid voltage V of the 3rd current switch M3 and the 6th current switch M6
HBe all the maintenance clock, the utility model is operated in sampling and the sequential chart in maintenance stage can be as shown in Figure 3.
In sum, the utility model had both had that ambipolar circuit is quick, input offset voltage is low and the advantage of high current drive capability, the characteristic that possesses cmos circuit low-power consumption and high integration again, thereby can satisfy the work requirements of High Speed High Precision ADC chip, can be widely used in the design of high-speed a/d converter module and IP kernel.
Below embodiment has been described in detail the utility model in conjunction with the accompanying drawings, and those skilled in the art can make the many variations example to the utility model according to the above description.Thereby some details among the embodiment should not constitute qualification of the present utility model, and the scope that the utility model will define with appended claims is as protection range of the present utility model.
Claims (6)
1. BiCMOS sampling hold circuit, it comprises that one is used to receive first, the input buffering level of second input signal, that be connected with this input buffering level respectively and be respectively applied for output first, first of second output signal, the second output buffer stage, be connected in first sampling capacitance and first to the 3rd current switch between the described input buffering level and the second output buffer stage in parallel and be connected in described input buffering level in parallel and first second sampling capacitance and the 4th to the 6th current switch of exporting between the buffer stage, described input buffering level comprises first triode of series connection and second triode and the 4th triode of the 3rd triode and series connection, wherein, the emitter of described first triode and second triode is connected back ground connection, the base stage and the collector electrode of described the 3rd triode and the 4th triode are connected to an external power source, it is characterized in that, described first to the 6th current switch is the NMOS pipe, the source electrode of described first to the 3rd current switch ground connection that links to each other, and first, the grid of second current switch links to each other, the source electrode of described the 4th to the 6th current switch ground connection that links to each other, and the 4th, the grid of the 5th current switch links to each other.
2. BiCMOS sampling hold circuit according to claim 1, it is characterized in that, described circuit also comprises first, second electric capacity, one end of described first electric capacity is connected with the collector electrode of described first triode, the other end is connected between described second sampling capacitance and the first output buffer stage, one end of described second electric capacity is connected with the collector electrode of described second triode, and the other end is connected between described first sampling capacitance and the second output buffer stage.
3. BiCMOS sampling hold circuit according to claim 1 and 2 is characterized in that,
The described first output buffer stage comprises the 8th triode and the 9th triode, the collector electrode of described the 8th, the 9th triode is connected to described external power source, the base stage of described the 8th triode is connected with the emitter of one the 5th triode, and be connected to the collector electrode of described second triode by the base stage of the 5th triode, the emitter of the 8th triode is connected with the base stage of described the 9th triode, the grounded emitter of the 9th triode, and the collector electrode of described the 5th triode is connected with described external power source;
The described second output buffer stage comprises the 14 triode and the 15 triode, collector electrode described the 14, the 15 triode is connected to described external power source, the base stage of described the 14 triode is connected with the emitter of 1 the 11 triode, and be connected to the collector electrode of described first triode by the base stage of the 11 triode, the emitter of the 14 triode is connected with the base stage of described the 15 triode, the grounded emitter of the 15 triode, and the collector electrode of described the 11 triode is connected with described external power source;
One end of described first sampling capacitance is connected with the base stage of described the 14 triode, and the other end is connected with described external power source; One end of described second sampling capacitance is connected with the base stage of described the 8th triode, and the other end is connected with described external power source;
The drain electrode of described first current switch is connected with the emitter of described the 14 triode, the drain electrode of described second current switch is connected with the emitter of described the 11 triode, the drain electrode of described the 3rd current switch is connected with the base stage of described the 11 triode, the drain electrode of described the 4th current switch is connected with the emitter of described the 8th triode, the drain electrode of described the 5th current switch is connected with the emitter of described the 5th triode, and the drain electrode of described the 6th current switch is connected with the base stage of described the 5th triode.
4. BiCMOS sampling hold circuit according to claim 3 is characterized in that, the other end of described first electric capacity is connected with the base stage of described the 8th triode, and the other end of described second electric capacity is connected with the base stage of described the 14 triode.
5. BiCMOS sampling hold circuit according to claim 4, it is characterized in that, the emitter of described the 3rd triode is connected with the collector electrode of described first triode by a resistance, the emitter of described the 4th triode is connected with the collector electrode of described second triode by a resistance, described first, the emitter of second triode links to each other after respectively connecting a resistance, and by a current source ground connection, the source electrode of described first to the 3rd current switch links to each other the back by a current source ground connection, the source electrode of described the 4th to the 6th current switch links to each other the back by a current source ground connection, the described the 9th, the emitter of the 15 triode is respectively by a current source ground connection.
6. BiCMOS sampling hold circuit according to claim 5, it is characterized in that, the base stage of described first triode receives described first input signal, the base stage of described second triode receives described second input signal, the emitter of described the 9th triode is exported described first output signal, and the emitter of described the 15 triode is exported described second output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206791649U CN202004747U (en) | 2010-12-23 | 2010-12-23 | BiCMOS (bipolar complementary metal oxide semiconductor) sampling retaining circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206791649U CN202004747U (en) | 2010-12-23 | 2010-12-23 | BiCMOS (bipolar complementary metal oxide semiconductor) sampling retaining circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202004747U true CN202004747U (en) | 2011-10-05 |
Family
ID=44707471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010206791649U Expired - Lifetime CN202004747U (en) | 2010-12-23 | 2010-12-23 | BiCMOS (bipolar complementary metal oxide semiconductor) sampling retaining circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202004747U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023124276A1 (en) * | 2021-12-30 | 2023-07-06 | 普源精电科技股份有限公司 | Snubber circuit and delay circuit |
-
2010
- 2010-12-23 CN CN2010206791649U patent/CN202004747U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023124276A1 (en) * | 2021-12-30 | 2023-07-06 | 普源精电科技股份有限公司 | Snubber circuit and delay circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103248837B (en) | A kind of imageing sensor based on memristor | |
| CN105071806A (en) | High-linearity input signal buffer applied to high-speed analog-digital converter | |
| CN102270981A (en) | Sampling switch circuit | |
| CN101986570B (en) | Analog-to-digital converter (ADC) and sample-and-hold circuit thereof | |
| CN106357269A (en) | Input buffer for high-speed time-interleaved analog-digital converter | |
| CN103246209B (en) | Power management system | |
| CN101714862B (en) | Driver for isolating edge signal | |
| CN203708221U (en) | Broadband sample hold circuit used for front end of successive-approximation analog-to-digital converter | |
| CN101399545B (en) | Low power buffer circuit | |
| CN202004747U (en) | BiCMOS (bipolar complementary metal oxide semiconductor) sampling retaining circuit | |
| CN201341126Y (en) | Current switch type BiCMOS latch comparator circuit | |
| CN101840908A (en) | Wide-input voltage range zero-leakage current input pull-up circuit | |
| CN204967796U (en) | Be applied to high -speed adc's high linearity incoming signal buffer | |
| CN103001633B (en) | NMOS buffer for the Current Control Digital-analog converter of high speed low-res | |
| CN101917184B (en) | Four-redundancy discrete signal integrated circuit | |
| CN102571069B (en) | Single-power-supply positive and negative logic conversion circuit | |
| CN210431392U (en) | Analog-to-digital converter circuit | |
| CN1777036A (en) | Hybrid two-layer folding circuit for high speed low-power consumption folding structure A/D converter | |
| CN2508464Y (en) | Sampling interface circuit structure using switch capacitance technique | |
| CN103036568B (en) | A kind of gradual approaching A/D converter | |
| CN102291116A (en) | Turnover type sampling hold circuit | |
| CN202393939U (en) | Cascade 1 x 8 optical switch | |
| CN204442347U (en) | A kind of MOS switch with high linearity | |
| CN107070447B (en) | Multi-input high-speed CMOS buffer circuit | |
| CN206060708U (en) | A kind of IGBT drive signals transmission circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20111005 |
|
| CX01 | Expiry of patent term |