CN201993422U - Device for real-time monitoring of health status of digital integrated circuit welding spots - Google Patents

Abstract

A device for real-time monitoring of the health status of digital integrated circuit welding spots comprises a status signal acquisition circuit, a status signal detecting circuit and a judgment output circuit. The status signal acquisition circuit is used for acquiring voltage signals capable of reflecting the health status of a welding spot network and transmitting the voltage signals to the status signal detecting circuit; the status signal detecting circuit is used for detecting status signals and transmitting detecting results to the judgment output circuit; and finally the judgment output circuit is used for comprehensively judging the detecting results and outputting judgment results. The device is capable of monitoring the health status of the welding spot network for connecting an internal chip of a digital integrated circuit device with a printed circuit board in real time during normal use of the digital integrated circuit device without affecting the normal use of the digital integrated circuit device, and the health status of the welding spot network can be effectively assessed by means of division of health, sub-health and failure. The device is simple in method, easy in realization and low in power consumption, and has wide application prospect in the technical field of welding spot network monitoring.

Description

A kind of to the real-time device for monitoring of digital integrated circuit welding spot health status

Technical field

The utility model relates to a kind of circuit that monitoring in real time connects the pad network health state of digital integrated circuit chip and circuit board that is used in normal operation, relate in particular to a kind ofly, belong to solder joint network monitor technical field the real-time device for monitoring of digital integrated circuit welding spot health status.

Background technology

All the time, the connectivity of pad all is an important integrity problem.Along with the widespread use of the BGA that has thousands of pins (Ball Grid Array, ball grid array) encapsulation, the encapsulation problem of complicated circuit has obtained good solution; Yet the increase of number of pins has also caused the reduction of reliability simultaneously.Therefore, for a lot of application circuits, the monitoring of the health status of solder joint is necessary.

As shown in Figure 1, this chip 1 is made up of wafer 2, wafer base 3 and BGA encapsulation 4.Flip-chip 5 upside-down mountings of being made up of wafer 2 and wafer base 3 encapsulate 4 inside at BGA, and are connected on the pad of encapsulation by inner soldered ball 38.BGA encapsulation 4 links together with printed wiring board 8 by BLM (ball limiting metallurgy, flange limit metallurgy) 6 and external solder ball 7 again.The various mechanical connections of connecting wafer and printed wiring board, inner soldered ball, BLM and external solder ball are referred to as " solder joint network ".

As shown in Figure 2, solder joint network resistor RSJ (resistance of solder joint network) 9 is series between high level Vdd 10 and the chip I/O 11 with R3.When chip internal is write logical one 2 I/O output is written as 0, RSJ9 will get certain voltage 13 according to the ratio of self resistance and R3, be called sense voltage.By monitoring node 14 place's sense voltage 13, know promptly whether RSJ9 self resistance changes, and then can assess its integrality.The resistance bridge network of being made up of R1, R2 produces reference voltage 16 by the principle of series connection dividing potential drop equally at node 15 places.Whether comparer 17 will compare with reference voltage 16 sense voltage 13, break down to judge RSJ 9.

For the incidental intermittent defect of solder joint,, therefore need between the whole operating period, butt welding point carry out malfunction monitoring because its duration is very short.To this, technology shown in Figure 2 also has certain limitation in the application of reality.At first, when test, the test I/O that solder joint connected output must be set to low level and can test.Like this, this I/O pin just can not drop into normal function application.If I/O is used to monitor intermittent defect, then this I/O pin just can not drop into normal function application.And no I/O is carried out malfunction monitoring is nonsensical.Use if I/O is used for normal function, then this technology can only could be monitored fault when the I/O output low level.Promptly can not reach the purpose of between the whole operating period, carrying out malfunction monitoring.Secondly, close because impulse disturbances waveform and intermittent defect detect voltage waveform, so when impulse disturbances occurred, this technology can be considered as impulse disturbances fault-signal and cause false-alarm.At last, this technology can only be given and is out of order and two results of non-fault, and health status that can not butt welding point network 9 is carried out classified estimation.

Summary of the invention

1, purpose: the purpose of this utility model is to provide a kind of to the real-time device for monitoring of digital integrated circuit welding spot health status, it can not influence under the normal prerequisite of using of device, and the health status that digital integrated circuit (IC)-components is connected the solder joint network of its internal wafer and printed wiring board between the operating period is monitored in real time.

2, technical scheme:

The utility model is a kind of to the real-time device for monitoring of digital integrated circuit welding spot health status, and it comprises state signal collecting circuit, status signal testing circuit and judges three parts of output circuit.Relation is therebetween: the state signal collecting circuit is gathered the voltage signal of the health status that can reflect the solder joint network, and is transferred to the status signal testing circuit; The status signal testing circuit detects status signal, and testing result is transferred to the judgement output circuit; Finally by judging that output circuit comprehensively judges testing result and export judged result.

Described state signal collecting circuit is: be formed by connecting by two branch roads.Article one, branch road series diode D1, R5 are connected to high level Vdd; Another series connection D6, R6 are connected to low level ground.By the setting of these two branch roads, then no matter device I/O output be high level or low level, the solder joint network state can both be detected.(comprising that resistance is tending towards 0 situation when the solder joint network free hinders) under the less situation of solder joint network resistor, when I/O output high level, D1 is by the D6 conducting, and solder joint network resistor, D6 and R6 are series between the low level that high level that I/O exports and R6 ground connection provides.At this moment, on the node between D6 and the R6, will produce state-detection voltage.When the I/O output low level, D1 conducting D6 ends, and solder joint network resistor, D1 and R5 are series between the high level that the low level of I/O output and Vdd that R5 is connected provide.At this moment, on the node between D1 and the R5, will produce state-detection voltage.When the solder joint network resistor arrives to a certain degree greatly, D1, D6 conducting simultaneously.At this moment, all will produce state-detection voltage on the node between D6 and R6 and D1 and the R5.

Described status signal testing circuit is: provide circuit and two double-limit comparators to form by reference threshold voltage.Relation is therebetween: reference threshold voltage provides circuit to provide bound reference threshold voltage to two double-limit comparators.The resistance bridge that this reference threshold voltage provides resistance bridge that circuit is connected into by R13, R14, R15 and R8, R7, R4 to be connected into is parallel between the high-low level and forms.Simultaneously, the state-detection voltage that produces on the node between D6 and R6 and D1 and the R5 is transferred to two double-limit comparators respectively.Double-limit comparator is called window comparator again, belong to a kind of typical voltage comparator, it is made up of fundamental operation amplifier, diode and amplitude limiter circuit, relation is therebetween: after two branch road parallel connections by fundamental operation amplifier and diode series connection, connect with amplitude limiter circuit, wherein amplitude limiter circuit is formed with being series at after voltage stabilizing diode is in parallel between ground and another resistance by resistance again.The fundamental operation amplifier is to be provided by integrated operational amplifier in the utility model.During solder joint network health state deteriorating, its resistance value can become big and cause the variation of state-detection voltage.Double-limit comparator compares state-detection voltage and reference voltage, to assess its health status.The reference voltage of each double-limit comparator all has two threshold values.When state-detection voltage fell between these two threshold values, the comparer output low level also thought that health status worsens.

Wherein, described each resistance, its resistance size only need satisfy corresponding formulas and get final product.

Described judgement output circuit is: by a composite door circuit of forming jointly with door U1 or door U2, U4 and XOR gate U3.Annexation between it is: the output of two double-limit comparators is connected with door U1 and XOR gate U3 with dual input; With door U1 same have enable to import Enable's or the door U2 be connected; XOR gate U3 and or the output of door U2 insert or door U4.It is to comprehensively judging from the detection signal of the double-limit comparator on two branch roads output and exporting judged result.

When device I/O was in high-impedance state, the status signal testing circuit on device and the printed wiring board disconnected.If device I/O, then can artificially control I/O output high level or low level not in user mode.When device I/O is in the high-low level state, when promptly using state, the utility model is divided into health, inferior health and fault three phases with the health status of solder joint network.Health is promptly excellent.Inferior health shows then that its health status has worsened but does not also have influence on the normal use of device.Malfunction shows that its health status has deteriorated into the normal degree of using of influence.When the solder joint network resistor was the 0 Ω left and right sides, two double-limit comparators were exported high level simultaneously, or door U2, U4 output height is flat.At this moment, judge that the solder joint network is in health status.When the solder joint network resistor hour, two double-limit comparators can an output low level, and another output high level, even door U2 output low level, or door U4 output high level.At this moment, judge that the solder joint network is in sub-health state.When the solder joint network resistor was big, two double-limit comparators are output low levels simultaneously, or also output low level simultaneously of door U2, U4.At this moment, judge that the solder joint network state is in malfunction.

3, advantage and effect: the utility model can not influence under the normal prerequisite of using of device, and the health status that digital integrated circuit (IC)-components is connected the solder joint network of its internal wafer and printed wiring board between the whole normal operating period is monitored in real time.The false-alarm that impulse disturbances causes can also be effectively got rid of in the setting of upper limit threshold voltage in the double-limit comparator, greatly reduces false alarm rate.In addition, but the health status of the division butt welding point network of healthy, inferior health and these three states of fault assess effectively.The utility model method is comparatively simple, realizes that power consumption is not high, can not bring bigger added burden to system easily.

Description of drawings

Fig. 1 is the johning knot composition of chip bga and printed wiring board;

Fig. 2 is forefathers' inventive circuit synoptic diagram;

Fig. 3 is a circuit structure diagram of the present utility model;

The equivalent circuit diagram of state signal collecting circuit when Fig. 4 a is the I/O output low level;

The equivalent circuit diagram of state signal collecting circuit when Fig. 4 b is I/O output high level;

Fig. 5 is that the double-limit comparator threshold voltage provides circuit diagram;

The simulation waveform figure that the butt welding point health status was simulated when Fig. 6 a was I/O output high level;

The simulation waveform figure that the butt welding point health status was simulated when Fig. 6 b was the I/O output low level.

Symbol description is as follows among the figure:

1 chip; 2 wafers; 3 wafer bases; The 4BGA encapsulation; 5 flip-chips; 6 flange limit metallurgies; 7 external solder ball; 8 printed wiring boards; 9 solder joint networks; 10 high level; 11 digital integrated circuit input/output port; Logic is write in 12 digital integrated circuit inside; Voltage on the node between 13R3 and the RSJ; Node between 14R3 and the RSJ; Node between 15R1 and the R2; Voltage on the node between 16R1 and the R2; 17 comparers; 18 state signal collecting circuit; Node between 19RSJ and D1, the D6; Node between 20D6 and the R6; The state-detection voltage that produces on the node between 21D6 and the R6; Node between 22D1 and the R5; The state-detection voltage that produces on the node between 23D1 and the R5; 24 status signal testing circuits; 25 pairs of state detection signals 23 compare the double-limit comparator of judgement; 26 pairs of state detection signals 21 compare the double-limit comparator of judgement; Node between 27R13 and the R14; Node between 28R14 and the R15; The reference voltage that produces on the node between 29R7 and the R8; The reference voltage that produces on the node between 30R7 and the R4; The reference voltage that produces on the node of 31R13 and R14; The reference voltage that produces on the node between 32R14 and the R15; Node between 33R7 and the R8; Node between 34R7 and the R4; 35 sub-health state signals; 36 fault status signals; 37 judge output circuit; 38 inner soldered balls.

RSJ solder joint network resistor R1 48000 Ω R2 2000 Ω R3 4800 Ω R4 1000 Ω R5 1000 Ω R6 1000 Ω R7 24k Ω R8 8000 Ω R9-R12 are the double-limit comparator internal resistance, all get 1000 Ω R13,1000 Ω R14,24000 Ω R15,8000 Ω:

D1-D6 is a diode, model 1N4500; D7, D8 are voltage stabilizing diode, and model is 1N4625; U1 is and door, and model 74F08, U3 are XOR gate, and model 74F86, U2, U4 are or door model 74AS1032A; V is an integrated operational amplifier, and model is LM324.

Embodiment

As shown in Figure 3, the utility model is a kind of circuit that digital integrated circuit welding spot health status is monitored in real time, and it comprises state signal collecting circuit 18, status signal testing circuit 24 and judges 37 3 parts of output circuit.State signal collecting circuit 18 on the printed wiring board is connected with digital integrated circuit input/output port 11 by solder joint network 9.18 pairs of voltage signals that can reflect the health status of solder joint network of state signal collecting circuit, be that the state-detection voltage 23 that produces on the node between state-detection voltage 21, D1 and the R5 that produces on the node between D6 and the R6 is gathered, and be transferred to status signal testing circuit 24.24 pairs of above-mentioned state- detection voltages 21,23 of status signal testing circuit detect, and testing result is transferred to judgement output circuit 37.Finally by judging that 37 pairs of testing results of output circuit comprehensively judge and export judged result.

Described state signal collecting circuit 18 is: be made up of two branch roads that are intersected in node 19 places.Article one, series diode D1, R5 are connected to high level Vdd; Another series connection D6, R6 are connected to low level ground.By the setting of these two branch roads, then no matter device I/O output be that high level or low level solder joint network health state can both be detected.Under the less situation of solder joint network resistor RSJ, (comprise that resistance is tending towards 0 situation when the solder joint network free hinders), when I/O output high level, D1 is by the D6 conducting, and solder joint network resistor RSJ, D6 and R6 are series between the low level that high level that I/O exports and R6 ground connection provides.At this moment, on the node between D6 and the R6 20, will produce state-detection voltage 21, and the voltage on the node 22 between D1 and the R5 is high level Vdd.When the I/O output low level, D1 conducting D6 ends, and solder joint network resistor RSJ, D1 and R5 are series between the high level that the low level of I/O output and Vdd that R5 is connected provide.At this moment, on the node between D1 and the R5 22, will produce state-detection voltage 23, and the voltage on the node 20 between D6 and the R6 is low level 0V.When solder joint network resistor RSJ arrives to a certain degree greatly, D1D6 conducting simultaneously.At this moment, will produce state- detection voltage 21,23 respectively on the node 20,22.

Described status signal testing circuit 24 is: provide circuit and two double-limit comparators to form by reference threshold voltage.Reference threshold voltage provides circuit to provide bound reference threshold voltage to two double-limit comparators.The resistance bridge that the resistance bridge that it is connected into by R13, R14, R15 and R8, R7, R4 are connected into is parallel between the high-low level and forms.The reference voltage 31 that node 27 places between R13, the R14 produce is the upper limit threshold voltage of double-limit comparator 25, and the reference voltage 32 that node 28 places between R14, the R15 produce is the lower threshold voltage of double-limit comparator 25; The reference voltage 29 that node 33 places between R8, the R7 produce is the upper limit threshold voltage of double-limit comparator 26, and the reference voltage 30 that node 34 places between R7, the R4 produce is the lower threshold voltage of double-limit comparator 26.Simultaneously, the node 22 between the node 20 between D6 and the R6, D1 and the R5 is connected with two double-limit comparators 25,26 in the state detection circuit 24 respectively.During solder joint network health state deteriorating, its resistance value can become big and cause the variation of state-detection voltage.Two double-limit comparators 25,26 compare state-detection voltage and reference voltage, to assess its health status.The reference voltage of each double-limit comparator all has two threshold values.When state-detection voltage fell between these two threshold values, comparer 17 output low levels also thought that health status worsens.

Described judgement output circuit 37 is: by a composite door circuit of forming jointly with door U1 or door U2, U4 and XOR gate U3.It is to comprehensively judging from the detection signal of the double-limit comparator on two branch roads 25,26 output and exporting judged result.Connected mode is as follows: the output of two double-limit comparators 25,26 is connected with door U1 and XOR gate U3 with dual input; With door U1 same have enable to import Enable's or the door U2 be connected; XOR gate U3 and or the output of door U2 insert or door U4.When device I/O is in high-impedance state, make that the status monitoring circuit on device and the printed wiring board disconnects.At this moment, the state that status signal testing circuit 24 can't butt welding point network 9 detects.A former general or a door U2 enable to import Enable and put 1, with the output of closed condition signal.Thus, the health status of solder joint network 9 can be divided into health, inferior health and three states of fault.The division correspondence of state the certain limit of solder joint network 9 resistance values.Because the problem of detection sensitivity, there is a minimum value R in resistance value that can detected solder joint network 9 _MinThen the resistance value RSJ of solder joint network 9 at 0 Ω to R _MinBetween the time, two double-limit comparators 25,26 are exported high level simultaneously, or the door U2, U4 output high level.At this moment, judge that solder joint network 9 is in health status.When RSJ increases to R _MidAnd when making D1, D6 conducting simultaneously, two double-limit comparators 25,26 are output low levels simultaneously, or also output low level simultaneously of door U2, U4.At this moment, judge that solder joint network 9 states are in malfunction and export fault status signal 36.When RSJ is in R _MinAnd R _MidBetween the time, two double-limit comparators 25,26 can an output low level, and another output high level, even door U2 output low level, or door U4 output high level.At this moment, judge that solder joint network 9 is in sub-health state and exports sub-health state signal 35.

The specific implementation method of device is as follows:

State signal collecting circuit 18 is formed by connecting by two branch roads.Article one, branch road series diode D1, R5 are connected to high level Vdd; Another series connection D6, R6 are connected to low level ground.Conducting by D1, D6 with end, what make no matter device I/O output is high level or low level, solder joint network 9 states can both be detected.When device I/O output low level, to be D6, R6 be series between the high-low level with same again D1, R5 after solder joint network 9 resistance R SJ are in parallel its equivalent electrical circuit, shown in Fig. 4 a; When device I/O output high level, to be D1, R5 be series between the high-low level with same again D6, R6 after solder joint network 9 resistance R SJ are in parallel its equivalent electrical circuit, shown in Fig. 4 b.Along with the increase of RSJ, make D1, D6 just the RSJ value of conducting simultaneously be R _MidBy Fig. 4 a and Fig. 4 b as can be known, if device I/O output low level, the then 19 place's voltage U of the node between RSJ and D1, the D6 ₁₉When just equaling diode turn-on voltage Von, D1, D6 be conducting simultaneously just.At this moment, the resistance RSJ of solder joint network 9 is R _MidAnd can be expressed from the next

$R_{\mathrm{mid}}=\frac{V_{\mathrm{on}}{R}_5}{\mathrm{Vdd}-{2V}_{\mathrm{on}}}$

If device I/O output high level, then U ₁₉When just equaling Vdd-Von, D1, D6 be conducting simultaneously just.At this moment, the resistance RSJ of solder joint network 9 is R _Mid' and can be expressed from the next

${R_{\mathrm{mid}}}^{\′}=\frac{V_{\mathrm{on}}{R}_6}{\mathrm{Vdd}-{2V}_{\mathrm{on}}}$

By above two formulas as can be seen, in order to make R _MidSame R _Mid' equate that R5 must equal R6.About the resistance of R5, R6, from the angle that reduces power consumption, should be the bigger the better.But consider from the angle of monitoring sensitivity,, be difficult to detect to such an extent as to then the voltage of being got on the solder joint network 9 resistance R SJ is just very little if R5, R6 resistance are very big.In general, R5, R6 resistance are chosen as R _MinAbout 10 times.

What in fact, really reflect solder joint network 9 health status is the voltage at its resistance R SJ two ends.And state-detection voltage is owing to there being relation one to one, so can be used for status detection with solder joint network 9 resistance R SJ both end voltage.The calculating of the state-detection voltage 23 that produces on the node between state-detection voltage 21, D1 and the R5 that produces on the node between the relation between them and state-detection voltage D6 and the R6, can be by following formulate:

When device I/O output low level and solder joint network 9 resistance R SJ hour, D1 conducting D6 ends, have this moment

The state-detection voltage 23 that produces on the node between D1 and the R5: $\mathrm{<figure-callout\; id="23"\; label="U"\; filenames="HDA0000039337840000022.png,HDA0000039337840000023.png"\; state="\{\{state\}\}">U</figure-callout>}23={\mathrm{<figure-callout\; id="19"\; label="U"\; filenames="HDA0000039337840000022.png,HDA0000039337840000023.png"\; state="\{\{state\}\}">U</figure-callout>}}_{19}+\mathrm{Von}=(\mathrm{Vdd}-\mathrm{Von})\&times;$ $\frac{\mathrm{RSJ}}{\mathrm{RSJ}+\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5}+\mathrm{Von}.$

Node 20 place's voltage: U between D6 and the R6 ₂₀=0V.

Solder joint network 9 resistance R SJ both end voltage: U _RSJ=U ₂₃-Von.

When device I/O output low level and solder joint network 9 resistance R SJ were big, D1, D6 conducting simultaneously had the state-detection voltage 23 that produces on the node between D1 and the R5 this moment:

${\mathrm{<figure-callout\; id="23"\; label="U"\; filenames="HDA0000039337840000022.png,HDA0000039337840000023.png"\; state="\{\{state\}\}">U</figure-callout>}}_{23}={\mathrm{<figure-callout\; id="19"\; label="U"\; filenames="HDA0000039337840000022.png,HDA0000039337840000023.png"\; state="\{\{state\}\}">U</figure-callout>}}_{19}+\mathrm{Von}=\frac{\mathrm{RSJ}\&times;R6(\mathrm{Vdd}-\mathrm{Von})+\mathrm{RSJ}\&times;\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5\&times;\mathrm{Von}}{\mathrm{RSJ}\&times;\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5+\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5\&times;\mathrm{<figure-callout\; id="6"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}6+\mathrm{RSJ}\&times;\mathrm{<figure-callout\; id="6"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}6}+\mathrm{Von}.$

The state-detection voltage 21 that produces on the node between D6 and the R6:

${\mathrm{<figure-callout\; id="21"\; label="U"\; filenames="HDA0000039337840000022.png,HDA0000039337840000023.png"\; state="\{\{state\}\}">U</figure-callout>}}_{21}=U_{19}-\mathrm{Von}=\frac{\mathrm{RSJ}\&times;R6(\mathrm{Vdd}-\mathrm{Von})+\mathrm{RSJ}\&times;\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5\&times;\mathrm{Von}}{\mathrm{RSJ}\&times;\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5+\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5\&times;\mathrm{<figure-callout\; id="6"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}6+\mathrm{RSJ}\&times;R6}-\mathrm{Von}.$

Solder joint network 9 resistance R SJ both end voltage: U _RSJ=U ₂₃-Von=U ₂₁+ Von.

When device I/O output high level and solder joint network 9 resistance R SJ hour, D6 conducting D1 ends, have this moment

The state-detection voltage 21 that produces on the node between D6 and the R6: ${\mathrm{<figure-callout\; id="21"\; label="U"\; filenames="HDA0000039337840000022.png,HDA0000039337840000023.png"\; state="\{\{state\}\}">U</figure-callout>}}_{21}=U_{19}-\mathrm{Von}=(\mathrm{Vdd}-\mathrm{Von})\&times;$ $\frac{\mathrm{<figure-callout\; id="6"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}6}{\mathrm{RSJ}+\mathrm{<figure-callout\; id="6"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}6}.$

Node 22 place's voltage: U between D1 and the R5 ₂₂=Vdd.

Solder joint network 9 resistance R SJ both end voltage: U _RSJ=Vdd-(U ₂₁+ Von).

When device I/O output high level and solder joint network 9 resistance R SJ were big, D1, D6 conducting simultaneously had the state-detection voltage 23 that produces on the node between D1 and the R5 this moment:

${\mathrm{<figure-callout\; id="23"\; label="U"\; filenames="HDA0000039337840000022.png,HDA0000039337840000023.png"\; state="\{\{state\}\}">U</figure-callout>}}_{23}={\mathrm{<figure-callout\; id="19"\; label="U"\; filenames="HDA0000039337840000022.png,HDA0000039337840000023.png"\; state="\{\{state\}\}">U</figure-callout>}}_{19}+\mathrm{Von}=\frac{\mathrm{RSJ}\&times;R6(\mathrm{Vdd}-\mathrm{Von})+\mathrm{RSJ}\&times;\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5\&times;\mathrm{Von}+\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5\&times;\mathrm{<figure-callout\; id="6"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}6\&times;\mathrm{Vdd}}{\mathrm{RSJ}\&times;\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5+\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5\&times;\mathrm{<figure-callout\; id="6"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}6+\mathrm{RSJ}\&times;\mathrm{<figure-callout\; id="6"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}6}+\mathrm{Von}.$

The state-detection voltage 21 that produces on the node between D6 and the R6:

${\mathrm{<figure-callout\; id="21"\; label="U"\; filenames="HDA0000039337840000022.png,HDA0000039337840000023.png"\; state="\{\{state\}\}">U</figure-callout>}}_{21}=U_{19}-\mathrm{Von}=\frac{\mathrm{RSJ}\&times;R6(\mathrm{Vdd}-\mathrm{Von})+\mathrm{RSJ}\&times;\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5\&times;\mathrm{Von}+\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5\&times;\mathrm{<figure-callout\; id="6"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}6\&times;\mathrm{Vdd}}{\mathrm{RSJ}\&times;\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5+\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}5\&times;\mathrm{<figure-callout\; id="6"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}6+\mathrm{RSJ}\&times;R6}-\mathrm{Von}.$

Solder joint network 9 resistance R SJ both end voltage:

U _RSJ＝Vdd-U ₂₃+Von＝Vdd-U ₂₁-Von。

In order to remove the impulse disturbances influence, reduce false alarm rate, adopt double-limit comparator to come monitoring state to detect voltage.Fundamental operation amplifier in the utility model in the double-limit comparator is to be provided by integrated operational amplifier, and model is chosen as LM324.Resistance R 9-R12 is a current-limiting resistance in the double-limit comparator, is chosen as 1000 Ω; D2-D5 is a diode, and model is chosen as 1N4500; D7, D8 are voltage stabilizing diode, are used to prevent the too high damage gate circuit of curtage, optional model 1N4625, and its voltage stabilizing value is 5.1V.As shown in Figure 5, the resistance bridge that is connected into of the resistance bridge that is connected into by R13, R14, R15 respectively of the dual threshold reference voltage of two double-limit comparators and R8, R7, R4 provides.The threshold voltage of double-limit comparator should be by the critical value decision of state-detection voltage when solder joint network 9 health status worsen.Simultaneously, the threshold reference voltage of each double-limit comparator can be by following formulate:

The upper limit threshold voltage of double-limit comparator 25, promptly reference voltage 31: ${\mathrm{<figure-callout\; id="31"\; label="U"\; filenames="HDA0000039337840000031.png"\; state="\{\{state\}\}">U</figure-callout>}}_{31}=\mathrm{Vdd}\&times;\frac{\mathrm{<figure-callout\; id="14"\; label="R"\; filenames="HDA0000039337840000012.png"\; state="\{\{state\}\}">R</figure-callout>}14+R15}{\mathrm{<figure-callout\; id="13"\; label="R"\; filenames="HDA0000039337840000012.png"\; state="\{\{state\}\}">R</figure-callout>}13+\mathrm{<figure-callout\; id="14"\; label="R"\; filenames="HDA0000039337840000012.png"\; state="\{\{state\}\}">R</figure-callout>}14+\mathrm{<figure-callout\; id="15"\; label="R"\; filenames="HDA0000039337840000012.png"\; state="\{\{state\}\}">R</figure-callout>}15}.$

The lower threshold voltage of double-limit comparator 25, promptly reference voltage 32: ${\mathrm{<figure-callout\; id="32"\; label="U"\; filenames="HDA0000039337840000031.png,HDA0000039337840000041.png"\; state="\{\{state\}\}">U</figure-callout>}}_{32}=\mathrm{Vdd}\&times;\frac{R15}{\mathrm{<figure-callout\; id="13"\; label="R"\; filenames="HDA0000039337840000012.png"\; state="\{\{state\}\}">R</figure-callout>}13+\mathrm{<figure-callout\; id="14"\; label="R"\; filenames="HDA0000039337840000012.png"\; state="\{\{state\}\}">R</figure-callout>}14+\mathrm{<figure-callout\; id="15"\; label="R"\; filenames="HDA0000039337840000012.png"\; state="\{\{state\}\}">R</figure-callout>}15}.$

The upper limit threshold voltage of double-limit comparator 26, promptly reference voltage 29: ${\mathrm{<figure-callout\; id="29"\; label="U"\; filenames="HDA0000039337840000031.png,HDA0000039337840000041.png"\; state="\{\{state\}\}">U</figure-callout>}}_{29}=\mathrm{Vdd}\&times;\frac{\mathrm{<figure-callout\; id="7"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}7+R4}{\mathrm{<figure-callout\; id="8"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}8+\mathrm{<figure-callout\; id="7"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}7+R4}.$

The lower threshold voltage of double-limit comparator 26, promptly reference voltage 30: ${\mathrm{<figure-callout\; id="30"\; label="U"\; filenames="HDA0000039337840000031.png,HDA0000039337840000041.png"\; state="\{\{state\}\}">U</figure-callout>}}_{30}=\mathrm{Vdd}\&times;\frac{R4}{\mathrm{<figure-callout\; id="8"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}8+\mathrm{<figure-callout\; id="7"\; label="R"\; filenames="HDA0000039337840000011.png"\; state="\{\{state\}\}">R</figure-callout>}7+R4}.$

Judge in the output circuit 37 the optional model 74F08 of U1, the optional model 74F86 of U3, the optional model 74AS1032A of U2, U4.

Give an example R _MinGet 100 Ω, R5, R6 are 1000 Ω, and Vdd is 3.3V, and Von is 0.65V, then R _MidBe 325 Ω.Be RSJ in 0 to 100 Ω scope, solder joint network 9 is a health status; In 325 Ω scopes, solder joint network 9 is a sub-health state to RSJ at 100 Ω; RSJ is during greater than 325 Ω, and solder joint network 9 is a malfunction.If solder joint network 9 unsoundness state deterioratings, then when device I/O exports high level, the voltage U at node 19 places between RSJ and D1, the D6 ₁₉Reduce along with the increase of RSJ.When the RSJ minimum is 100 Ω, U ₁₉=3.06V; When RSJ is infinitely great, U ₁₉=1.65V.The full conducting of D6 in this process, and U ₂₁For 2.41V between the 1V.And work as U ₁₉When 2.65V was between 1.65V, D1 was also with conducting, and U ₂₃For 3.3V between the 2.3V.When device I/O output low level, the voltage U at node 19 places between RSJ and D1, the D6 ₁₉Increase along with the increase of solder joint network 9 resistance R SJ.When the RSJ minimum is 100 Ω, U ₁₉=240mV; When RSJ is infinitely great, U ₁₉=1.65V.The full conducting of D1 in this process, and U ₂₃For 890mV between the 2.3V.And work as U ₁₉When 650mV was between 1.65V, D6 was also with conducting, and U ₂₁For 0V between the 1V.By above analysis as can be known, during solder joint network health state deteriorating, U ₂₁At 0V between the 2.41V, and U ₂₃At 890mV between the 3.3V.The bound threshold voltage that is double-limit comparator 25 should be 3.3V and 890mV respectively; The bound threshold voltage of double-limit comparator 26 should be 2.41V and 0V respectively.Yet when D1 ended, the node 22 place's voltages between D1 and the R5 were 3.3V.For avoiding erroneous judgement, so upper limit threshold voltage needs less than 3.3V.In like manner, when D6 ended, the node 20 place's voltages between D6 and the R6 were 0V.For avoiding erroneous judgement, so lower threshold voltage needs greater than 0V.Consider the factor of noise simultaneously, then the bound threshold voltage of double-limit comparator 25 should be 3.2V and 800mV respectively; The bound threshold voltage of double-limit comparator 26 should be 2.5V and 100mV respectively.After the bound threshold voltage of double-limit comparator was determined, the proportionate relationship between resistance R 13, R14, R15, R4, R7, the R8 just can be learnt.Consider power consumption considerations, desirable R13 is 1000 Ω, and R14 is 24k Ω, and R15 is 8000 Ω, and R4 is 1000 Ω, and R7 is 24k Ω, and R8 is 8000 Ω.

According to above analysis, when device I/O output high level, along with solder joint network 9 changes to disconnection (resistance infinity), U from non-fault (resistance is 0 Ω) ₁₉Be reduced to 1.65V gradually by 3.3V.Therefore, it is 3.3V that node 19 places between RSJ and D1, D6 are provided with the pulse voltage high level, and low level is 1.65V, but then the health status of butt welding point network 9 is simulated.The simulation waveform figure of circuit is shown in Fig. 6 a.At this moment, D6 manages first conducting.The resistance RSJ of solder joint network 9 is considered to non-fault when 0 Ω is in 100 Ω scopes.Show as the state-detection voltage U among Fig. 6 a ₂₁, U ₂₃Respectively greater than upper limit threshold reference voltage U ₂₉, U ₃₁, sub-health state signal 35 and fault status signal 36 are exported high level, promptly are judged as to be in health status.When RSJ reaches 100 Ω, U ₂₁Less than U ₂₉And U ₂₃Still greater than U ₃₁, sub-health state signal 35 output low levels and fault status signal 36 is still exported high level promptly are judged as solder joint network 9 and are in sub-health state.When increasing to 325 Ω along with RSJ, D1 is conducting simultaneously also, makes U ₂₃Also less than U ₃₁, then also output low level of fault status signal 36 judges that promptly the solder joint network is in malfunction.In like manner, when device I/O output low level, along with the solder joint network changes to disconnection (resistance infinity), U from non-fault (resistance is 0 Ω) ₁₉Be increased to 1.65V gradually by 0V.Therefore, at node 19 places the pulse voltage high level being set is 1.65V, and low level is 0V, can get the simulation waveform figure of circuit, shown in Fig. 6 b.

Claims (1)

1. one kind to the real-time device for monitoring of digital integrated circuit welding spot health status, it is characterized in that: it comprises state signal collecting circuit, status signal testing circuit and judges three parts of output circuit; The status signal testing circuit is gathered and be transferred to this state signal collecting circuit to the voltage signal of the health status that can reflect the solder joint network; This status signal testing circuit detects status signal and testing result is transferred to the judgement output circuit; Finally testing result is comprehensively judged and exported judged result by this judgement output circuit;

Described state signal collecting circuit is: be formed by connecting by two branch roads; Article one, branch road series diode D1, R5 are connected to high level Vdd; Another series connection D6, R6 are connected to low level ground;

Described status signal testing circuit is: provide circuit and two double-limit comparators to form by reference threshold voltage; Reference threshold voltage provides circuit to provide bound reference threshold voltage to two double-limit comparators; The resistance bridge that this reference threshold voltage provides resistance bridge that circuit is connected into by R13, R14, R15 and R8, R7, R4 to be connected into is parallel between the high-low level and forms; Simultaneously, the state-detection voltage that produces on the node between D6 and R6 and D1 and the R5 is transferred to two double-limit comparators respectively; Double-limit comparator is a window comparator, is a kind of typical voltage comparator, and it is made up of fundamental operation amplifier, diode D2-D5 and amplitude limiter circuit; Article two, after the branch road parallel connection by fundamental operation amplifier and diode D2-D5 series connection, connect with amplitude limiter circuit again, wherein amplitude limiter circuit by resistance R 9-R12 be series at after voltage stabilizing diode D7, D8 are in parallel and another resistance between form; This fundamental operation amplifier is to be provided by integrated operational amplifier; The reference voltage of each double-limit comparator all has two threshold values;

Described judgement output circuit is: by a composite door circuit of forming jointly with door U1 or door U2, U4 and XOR gate U3; The output of two double-limit comparators is connected with door U1 and XOR gate U3 with dual input; With door U1 same have enable to import Enable's or the door U2 be connected; XOR gate U3 and or the output of door U2 insert or door U4.

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