CN201957032U

CN201957032U - Self-adaption multiplexer and de-multiplexer of broadband based on FPGA and priority level

Info

Publication number: CN201957032U
Application number: CN2011200270835U
Authority: CN
Inventors: 刘光伦
Original assignee: Sichuan Jiuzhou Electric Group Co Ltd
Current assignee: Sichuan Jiuzhou Electric Group Co Ltd
Priority date: 2011-01-27
Filing date: 2011-01-27
Publication date: 2011-08-31
Anticipated expiration: 2021-01-27

Abstract

The utility model belongs to the technical field of digital multiplexing, and discloses a self-adaption multiplexer and de-multiplexer of a broadband based on FPGA and priority level. The multiplexer comprises a first asynchronous serial interface ASI, a first voice data interface, a first two groups of RS232 interfaces, a first site programmable gate array FPGA and modulation module, wherein the first asynchronous serial interface ASI, the first voice data interface and the first two groups of RS232 interfaces are respectively connected with the first site programmable gate array FPGA which is connected with the modulation module. The utility model also discloses the corresponding de-multiplexer. The multiplexer and the de-multiplexer can fully utilize a link broadband, and can satisfy the transmission of each shunting signal.

Description

Wideband adaptive multiplexer based on FPGA and priority is conciliate multiplexer

Technical field

The utility model relates to the Digital Multiple Connection Technique field, relate in particular to a kind of based on FPGA(Field-Programmable Gate Array: i.e. field programmable gate array, it is the product that further develops on the basis of programming devices such as PAL, GAL, CPLD) the wideband adaptive multiplexer conciliate multiplexer.

Background technology

The application of Digital Multiple Connection Technique is at first from the local telephone network relay transmission, and for adapting to the flexible connection of asynchronous branch road, adopting the stuffing pulse technology was the high speed bitstream with the multiple connection of quasi synchronous low speed tributary signal at that time.Transmission medium is a cable during beginning because the band resource anxiety, therefore mainly be conceived to control and fill in shake and save the overhead bit expense, according to the technology history of country /region formed beautiful, day, the PDH (Pseudo-synchronous Digital Hierarchy) of the three kinds of different rates structures in Europe.

In vehicular communication system, at every moment all there is exchanges data aircraft and ground control centre.Aircraft will with oneself status signal and the image capturing system picture signal of gathering real-time be sent to ground.The ground control centre also will be analyzed aircraft and transmit the data-signal of returning, and makes correct reaction, and control signal corresponding is sent on the aircraft.Be sent in the data-signal on ground at aircraft, can be divided in real time and the dissimilar signal of non real-time some non-real-time datas of the i.e. status signal of aircraft and picture signal and collection.In the data of reality transmitted, each circuit-switched data may cut in and out, and is not to have as view data always.Send the instruction of images acquired when ground control centre after, carry-on image collecting device just begins image data.So some the time, certain road signal does not have data back.And the data volume of other each road signal also fluctuates up and down, if distribute fixing bandwidth along separate routes to each, must cause the waste of bandwidth.The general employing of Digital Multiple Connection Technique of the prior art distributed the mode of fixing bandwidth along separate routes to each, and some the time, certain road signal does not have data back.And the data volume of other each road signal also fluctuates up and down, causes the waste of bandwidth.

The utility model content

Therefore the technical problem of the waste of the bandwidth that causes at the average assigned bandwidth that exists in the prior art is necessary to provide a kind of wideband adaptive multiplexer based on FPGA and priority to conciliate multiplexer.

The utility model discloses a kind of wideband adaptive multiplexer and conciliate multiplexer based on FPGA and priority.A kind of wideband adaptive multiplexer based on FPGA and priority comprises the first Asynchronous Serial Interface ASI, the first speech data interface, first two groups of RS232 interfaces, primary scene programmable gate array FPGA and modulation module; The above-mentioned first Asynchronous Serial Interface ASI, the first speech data interface, first two groups of RS232 interfaces are connected with the primary scene programmable gate array FPGA respectively, and above-mentioned primary scene programmable gate array FPGA is connected with modulation module.The invention also discloses with above-mentioned multiplexer and separate multiplexer accordingly, comprise the second Asynchronous Serial Interface ASI, second speech data interface, second two groups of RS232 interfaces, secondary scene programmable gate array FPGA and demodulation module; The above-mentioned second Asynchronous Serial Interface ASI, second speech data interface, second two groups of RS232 interface are connected with secondary scene programmable gate array FPGA respectively, and above-mentioned secondary scene programmable gate array FPGA is connected with demodulation module.

The beneficial effects of the utility model are: provide a kind of wideband adaptive multiplexer based on FPGA and priority to conciliate multiplexer, above-mentioned multiplexer is conciliate the mode that multiplexer utilizes multiple connection frame by frame and asynchronous multiplexing, adopt buffering to finish the code check adjustment, make full use of the transmission characteristic that link bandwidth can satisfy each shunting sign again.

Description of drawings

Fig. 1 is a multiplexer structure chart of the present utility model.

Fig. 2 is the multiplexer structure chart of separating of the present utility model.

Fig. 3 is the fundamental diagram of multiplexer.

Fig. 4 is the frame format schematic diagram.

Embodiment

Below in conjunction with accompanying drawing the utility model is further elaborated.The utility model discloses a kind of wideband adaptive multiplexer and conciliate multiplexer based on FPGA and priority.

Multiplexer structure chart of the present utility model as shown in Figure 1, it comprises the first Asynchronous Serial Interface ASI, the first speech data interface, first two groups of RS232 interfaces, primary scene programmable gate array FPGA and modulation module; The above-mentioned first Asynchronous Serial Interface ASI, the first speech data interface, first two groups of RS232 interfaces are connected with the primary scene programmable gate array FPGA respectively, and above-mentioned primary scene programmable gate array FPGA is connected with modulation module.One road video data is delivered to a FPGA by the first Asynchronous Serial Interface ASI, one road speech data is delivered to a FPGA after compressing by AMBE2000, first two groups of RS232 interface data directly enter a FPGA, four circuit-switched data are through after the multiple connection, deliver to modulation module and modulate and send radio-frequency module to send.Wherein above-mentioned RS232 interface is one of communication interface on the personal computer, by Electronic Industries Association (Electronic Industries Association, the asynchronous transmission standard interface of EIA) being formulated.The RS-232 interface occurs with 9 pins (DB-9) or the kenel of 25 pins (DB-25), is called COM1 and COM2.

The multiplexer structure chart of separating of the present utility model as shown in Figure 2, it comprises the second Asynchronous Serial Interface ASI, second speech data interface, second two groups of RS232 interfaces, secondary scene programmable gate array FPGA and demodulation module; The above-mentioned second Asynchronous Serial Interface ASI, second speech data interface, second two groups of RS232 interface are connected with secondary scene programmable gate array FPGA respectively, and above-mentioned secondary scene programmable gate array FPGA is connected with demodulation module.Correspondingly, the course of work of separating the course of work of separating device again and multiplexer is opposite, radio frequency part is delivered to the demodulation module demodulation after receiving signal, data after the demodulation are delivered to and are separated the multiple connection module and separate multiple connection, separate that each circuit-switched data after the multiple connection delivers to that each self-corresponding output interface shows or further data processing.

The fundamental diagram of multiplexer as shown in Figure 3, the utility model adopt the mode of multiple connection frame by frame and asynchronous multiplexing.Because it is asynchronous participating in each shunting sign of multiple connection, before multiple connection, each data along separate routes must be converted to the data of closing road clock frequency domain.Promptly before carrying out each circuit-switched data multiple connection, must carry out the code check adjustment.In the utility model technology, adopt buffer technology to finish the code check adjustment, after data enter FPGA, import an asynchronous FIFO, if the input data have data clock signal then directly use the data input clock of data clock as FIFO, if do not have data clock then adopt clock recovery circuitry to extract the input clock signal of input signal clock frequency, with the data output clock signal of local clock signal (the output clock after the multiple connection) as FIFO as FIFO.After the code check adjustment on each road was finished, Multi-connection unit received each shunting sign through the data after the justification, according to time-multiplexed mode, respectively each circuit-switched data is added frame head, again by same port output.The utility model adopts the mode of multiple connection frame by frame, and the maximum data number of every frame is fixed (comprising frame head), and the length of frame is variable.All adding frame head before every frame can be with each reduction of data along separate routes so that separate the multiple connection end.

In the real-time of this multiplexer design consideration data and the significance level of data each circuit-switched data is carried out the priority design, the priority that real-time is high is the highest, and the data that importance is high are taken second place.And do not limit each concrete bandwidth along separate routes, each can ownly transmit requirement according to data along separate routes, and the bandwidth of real-time adjustment oneself according to the maximum delay requirement of transfer of data, is set the maximum amount of data of every frame data.Each is adopted priority mode along separate routes, the data that priority is high have the request of transmission with regard to first multiple connection, the data that priority is low have request, must could send after the multiple connection after the high multiple connection of priority is over, and require high for some real-time, and the signal that speed is little, as voice, GPS information etc. then adopt and all insert this circuit-switched data transmit in each frame, the data division of this insertion can be flexible and changeable, can insert the arrangement of data according to the actual needs.If each circuit-switched data does not all have the request of data of transmission, adopt fixed codeword to carry out the infilled frame data, guarantee the transmission requirement of real time data like this, have greater flexibility again, also high to bandwidth utilization.

Concrete frame format schematic diagram as shown in Figure 4, the synchronous head here are in order to guarantee the group synchronization of transfer of data, just frame synchronization.This is the precondition of correct receiver packet number certificate, so in frame head, synchronization field is to send at first to close on the delivery channel of road.Be the little real time data of inserting of data volume after the synchronization field, as voice etc., big or small maximum can be inserted 10 BYTE, can adjust as required, and each frame of these data all will send the real-time that guarantees data.Be only frame identification field then.The effect of this field is to show that the data of this bag are to come from which bar along separate routes, recover the data of this shunt according to this field when separating multiple connection.

Above-described specific embodiment; the purpose of this utility model, technical scheme and beneficial effect are further described; institute is understood that; the above only is a specific embodiment of the utility model; be not limited to the utility model; all within spirit of the present utility model and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within the protection range of the present utility model.

Claims

1. the wideband adaptive multiplexer based on FPGA and priority is characterized in that comprising the first Asynchronous Serial Interface ASI, the first speech data interface, first two groups of RS232 interfaces, primary scene programmable gate array FPGA and modulation module; The described first Asynchronous Serial Interface ASI, the first speech data interface, first two groups of RS232 interfaces are connected with the primary scene programmable gate array FPGA respectively, and described primary scene programmable gate array FPGA is connected with modulation module.

2. multiplexer as claimed in claim 1 is separated multiplexer accordingly, it is characterized in that comprising the second Asynchronous Serial Interface ASI, second speech data interface, second two groups of RS232 interfaces, secondary scene programmable gate array FPGA and demodulation module; The described second Asynchronous Serial Interface ASI, second speech data interface, second two groups of RS232 interface are connected with secondary scene programmable gate array FPGA respectively, and described secondary scene programmable gate array FPGA is connected with demodulation module.