CN201956057U - Multi-sampling-rate decoding system for digital audio signal - Google Patents
Multi-sampling-rate decoding system for digital audio signal Download PDFInfo
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- CN201956057U CN201956057U CN2010206683729U CN201020668372U CN201956057U CN 201956057 U CN201956057 U CN 201956057U CN 2010206683729 U CN2010206683729 U CN 2010206683729U CN 201020668372 U CN201020668372 U CN 201020668372U CN 201956057 U CN201956057 U CN 201956057U
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Abstract
The utility model provides a multi-sampling-rate decoding system for a digital audio signal, which at least comprises a clock generating module, a programmable clock generating module and a single-sampling-rate digital audio signal decoding module. The clock generating module is used for generating basic clock signals needed for the working of the system; the programmable clock generating module is used for processing the basic clock signal transmitted by the clock generating module, programming to generate system clock signals at different frequencies according to requirements and supplying the system clock signals to the single-sampling-rate digital audio signal decoding module; and the single-sampling-rate digital audio signal decoding module cooperates with the system clock signals at different frequencies to achieve the decoding of a multi-sampling-rate digital audio signal. Without the additional design of a plurality of different clock frequency dividing circuits, the multi-sampling-rate decoding system for the digital audio signal can achieve the purpose of decoding the multi-sampling-rate digital audio signal by only using a conventional single-sampling-rate audio decoding module.
Description
Technical field
The utility model relates to a kind of decode system of digital audio and video signals, particularly relates to a kind of multi-sampling rate decode system of digital audio and video signals.
Background technology
The most of digital audio processing technology that adopts of present multimedia processor, just converting simulated audio signal to digital audio and video signals stores in multimedia processor, when playing sound the digital audio and video signals of storing is reduced into simulated audio signal and plays again, so the decoding of digital audio and video signals is most important for the digital audio processing technology.
As previously mentioned, in the digital audio processing technical field, for reaching good audio frequency effect, the digital audio and video signals of multiple sampling rate often needs to decode, the digital audio and video signals sampling rate that is usually directed to is 44.1KHz, 32KHz and 48KHz, in some audio system even also may need to handle the digital audio and video signals of 16KHz, 24KHz and 22.05KHz sampling rate.
At present, handle following two kinds usually of the conventional methods of the digital audio and video signals of different sampling rates.Fig. 1 is the system architecture diagram of the multi-sampling rate decode system of wherein a kind of existing digital audio and video signals, as shown in Figure 1, the multi-sampling rate decode system of existing digital audio and video signals comprises system clock generation module 101 and multi-sampling rate digital audio and video signals processing module 102, system clock generation module 101 is made of crystal oscillator and phaselocked loop (PLL) circuit, be used to produce fixed system clock signal F, in multi-sampling rate digital audio and video signals processing module 102, at first according to the demand of sampling rate, fixing system clock F is carried out corresponding frequency division by a plurality of frequency dividing circuits (frequency dividing circuit 1...N) and clock signal selecting circuit handle the clock signal F/X that obtains being fit to
iSupplying with Digital audio process module decodes.Fig. 2 is the system architecture diagram of the multi-sampling rate decode system of another kind of existing digital audio and video signals, the multi-sampling rate decode system of this digital audio and video signals produces fixed system clock signal F by crystal oscillator and phaselocked loop (PLL) circuit, for the digital audio and video signals of different sampling rates, design is decoded with the corresponding a plurality of Digital audio process module of sampling rate (digital audio and video signals decoder module 1...N) respectively.
Though above-mentioned two kinds of methods can reach the purpose of the digital audio and video signals of the multiple sampling rate of decoding, but but have following two shortcomings: 1, above-mentioned two kinds of methods are for the signal of different sampling rates, all need to design a plurality of clock division circuitss, it is complicated to cause hardware to be realized, cost rises; 2, above-mentioned two kinds of methods can't directly be expanded into the digital audio and video signals decoder module that can handle a plurality of different sampling rates for the digital audio decoding module of existing single sampling rate.
In sum, the multi-sampling rate decode system of the digital audio and video signals of prior art exists hardware to realize that complicated, cost rises and can't expand the digital audio decoding module problem of existing single sampling rate as can be known, therefore, be necessary to propose improved technological means in fact, solve this problem.
The utility model content
For overcoming the above-mentioned shortcoming of prior art, fundamental purpose of the present utility model is to provide a kind of multi-sampling rate decode system of digital audio and video signals, and it has been realized need not a plurality of different clock division circuitss of additional designs and has only utilized existing single sampling rate audio decoder module can be to the purpose of the decoding of the digital audio and video signals of multi-sampling rate.
For reaching above-mentioned and other purpose, the utility model provides a kind of multi-sampling rate decode system of digital audio and video signals, comprises at least: the clock generating module is used to produce basic clock signal; Programmable clock generation module receives this basic clock signal and it is handled the clock signal of system of the suitable digital audio and video signals sampling rate to be decoded of programming generation frequency; And single sampling rate digital audio decoding module, receive this clock signal of system, realize the decoding of this digital audio and video signals to be decoded.
Further, this programmable clock generation module produces this clock signal of system in the following way: the relation of calculating original system clock frequency in signal sampling rate that this list sampling rate digital audio decoding module handles and the original application in original application; According to the relation of this signal sampling rate and this primal system clock frequency, extrapolate the required system clock frequency of this digital audio and video signals to be decoded that to decode; Calculate the relation of this system clock frequency and this basic clock signal; Select the setting of this programmable clock generation module according to the relation of this system clock frequency and this basic clock signal, simulate and immediate this clock signal of system of this system clock frequency.
Further, signal sampling rate and this primal system clock frequency handled in original application of this list sampling rate digital audio and video signals decoder module has fixing proportionate relationship.
Further, this programmable clock generation module is realized by programmable phase-locked loop circuitry.
This programmable clock generation module comprises at least to be removed R frequency divider, phase detector, low-pass filter, voltage controlled oscillator and removes the Fractional-N frequency device, this basic clock signal is fed through and exports this phase detector, this low-pass filter and this clock signal of system of this voltage controlled oscillator processing back output successively to after this removes the processing of R frequency divider, and the output of this voltage controlled oscillator simultaneously also removes the Fractional-N frequency device by this and feeds back to this phase detector.
Compared with prior art, the multi-sampling rate decode system of a kind of digital audio and video signals of the utility model, change system clock frequency by programmable clock generation module, realized utilizing existing single sampling rate audio decoder module can be to the application requirements of multi-sampling rate digital audio and video signals decoding, in the utility model, digital audio and video signals at different sampling rates, need not a plurality of different clock division circuitss of additional designs, can realize decoding to the multi-sampling rate digital audio and video signals, it is simple in structure, and made full use of existing single sampling rate audio decoder module, realize the signal Processing of any sampling rate, exempt the process and the design risk that design new multi-sampling rate audio decoder module, reduced cost.
Description of drawings
Fig. 1 is a kind of system architecture diagram of multi-sampling rate decode system of existing digital audio and video signals;
Fig. 2 is a kind of system architecture diagram of multi-sampling rate decode system of existing digital audio and video signals;
Fig. 3 is the system architecture diagram of the multi-sampling rate decode system of a kind of digital audio and video signals of the utility model;
Fig. 4 is the simple knot composition of programmable clock generation module among Fig. 3;
Fig. 5 is the flow chart of steps of the multi-sampling rate coding/decoding method of a kind of digital audio and video signals of the utility model.
Embodiment
Below by specific instantiation and accompanying drawings embodiment of the present utility model, those skilled in the art can understand other advantage of the present utility model and effect easily by the content that this instructions disclosed.The utility model also can be implemented or be used by other different instantiation, and the every details in this instructions also can be based on different viewpoints and application, carries out various modifications and change under the spirit of the present utility model not deviating from.
Fig. 3 is the system architecture diagram of the multi-sampling rate decode system of a kind of digital audio and video signals of the utility model.As shown in Figure 3, the multi-sampling rate decode system of a kind of digital audio and video signals of the utility model comprises clock generating module 301, programmable clock generation module 302 and single sampling rate audio decoder module 303.
Wherein to be used to produce the required frequency of system works be the basic clock signal of F to clock generating module 301, and give programmable clock generation module 302 the basic clock signal F of system and handle, and specifically, clock generating module 301 can be realized by crystal oscillating circuit; Programmable clock generation module 302 be used for the basic clock signal F that clock generating module 301 sends is handled, and the clock signal of system Fi of programming generation different frequency offers single sampling rate digital audio decoding module according to demand; And single sampling rate digital audio decoding module 303, the clock signal of system that cooperates different frequency, realize the decoding of the digital audio and video signals of multi-sampling rate, in the original application, frequency at the clock signal of system of supplying with this list sampling rate digital audio decoding module 303 is under the F0 condition, the sampling rate of can decoding is the digital audio and video signals to be decoded of Fs0, and in the utility model, single sampling rate digital audio decoding module 303 is used with the clock signal of system Fi that programmable clock generation module 302 produces, and can realize the decoding of the digital audio and video signals of multi-sampling rate.
Specifically, this programmable clock generation module 302 can be realized by programmable phase-locked loop circuitry.Fig. 4 is the simple knot composition of the programmable clock generation module 302 of the utility model preferred embodiment.As shown in Figure 4, the utility model programmable clock generation module 302 comprises removes R frequency divider 401, phase detector 402, low-pass filter 403, voltage controlled oscillator 404 and remove Fractional-N frequency device 405, wherein remove the basic clock signal F that R frequency divider 401 receive clock generation modules 301 are sent into, after handling, R frequency divider 401 exports phase detector 402 through removing successively to, low-pass filter 403 and voltage controlled oscillator 404 are handled back output system time clock Fi, the output of this voltage controlled oscillator simultaneously also removes Fractional-N frequency device 405 by one and feeds back to phase detector 402, by changing the clock signal of system Fi that removes R frequency divider 401 and can produce different frequency except that the setting of R in the Fractional-N frequency device 405 and N.Programmable clock generation module 302 can produce the clock signal of system Fi that is fit to digital audio and video signals sampling rate to be decoded in the following way: at first calculate signal sampling rate that single sampling rate digital audio and video signals decoder module handles with the relation between the primal system clock frequency in original application; According to above-mentioned relation, extrapolate this list sampling rate digital audio and video signals decoder module then if the required system clock frequency of digital audio and video signals (digital audio and video signals to be decoded) that will decode; Then the computing system clock frequency is with the relation of the basic clock signal of clock generating module generation; Select the setting of programmable clock generation module 302 at last according to the proportionate relationship of system clock frequency and basic clock signal, be specially and remove R frequency divider 401 and the setting that removes N and R in the Fractional-N frequency device 405, to simulate and the immediate clock signal Fi0 of required system clock frequency, and Fi0 offered single sampling rate digital audio and video signals decoder module as clock signal of system, to realize the decoded digital sound signal.
Fig. 5 is the flow chart of steps of the multi-sampling rate coding/decoding method of a kind of digital audio and video signals of the utility model.Below will cooperate Fig. 5 and further specify the multi-sampling rate coding/decoding method of the utility model digital audio and video signals by a specific embodiment.
Suppose in the original application, the primal system clock frequency is F0, the signal sampling rate of single sampling rate digital audio and video signals decoder module 303 is Fs0, the sampling rate that now needs to decode is the digital audio and video signals to be decoded of Fsi, the multi-sampling rate coding/decoding method of a kind of digital audio and video signals of the present utility model, step is as follows:
Because sampling rate Fsi of the present utility model and system clock frequency Fi have ubiquity, so digital audio and video signals Fsn for any sampling rate, as the digital audio and video signals of the multiple sampling rates such as 44.1KHz, 32KHz, 48KHz, 16KHz, 24KHz and 22.05KHz that relate at the digital audio processing field, all only need the substitution relational expression
And programmable clock generation module is set in view of the above, change the clock signal of system Fn0 that programmable clock generation module produces, can realize utilizing the decode digital audio and video signals of any sampling rate Fsn of the digital audio and video signals decoder module of single sampling rate, the programmable clock generation module that relates in while the utility model, can be according to the system clock frequency error range that digital audio processing system allowed, select the programmable clock generation module of suitable accuracy, so that obtain better system performance.
The foregoing description is illustrative principle of the present utility model and effect thereof only, but not is used to limit the utility model.Any those skilled in the art all can be under spirit of the present utility model and category, and the foregoing description is modified and changed.Therefore, rights protection scope of the present utility model should be listed as claims.
Claims (3)
1. the multi-sampling rate decode system of a digital audio and video signals comprises at least:
The clock generating module is used to produce basic clock signal;
Programmable clock generation module receives this basic clock signal and it is handled the clock signal of system of the suitable digital audio and video signals sampling rate to be decoded of programming generation frequency; And
Single sampling rate digital audio decoding module receives this clock signal of system, realizes the decoding of this digital audio and video signals to be decoded.
2. the multi-sampling rate decode system of digital audio and video signals as claimed in claim 1, it is characterized in that: this programmable clock generation module is realized by programmable phase-locked loop circuitry.
3. the multi-sampling rate decode system of digital audio and video signals as claimed in claim 2, it is characterized in that: this programmable clock generation module comprises at least to be removed R frequency divider, phase detector, low-pass filter, voltage controlled oscillator and removes the Fractional-N frequency device, this basic clock signal is fed through and exports this phase detector, this low-pass filter and this clock signal of system of this voltage controlled oscillator processing back output successively to after this removes the processing of R frequency divider, and the output of this voltage controlled oscillator simultaneously also removes the Fractional-N frequency device by this and feeds back to this phase detector.
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| CN2010206683729U CN201956057U (en) | 2010-12-17 | 2010-12-17 | Multi-sampling-rate decoding system for digital audio signal |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543085A (en) * | 2010-12-17 | 2012-07-04 | 无锡华润矽科微电子有限公司 | Multi-sampling rate decoding system of digital audio signal and method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543085A (en) * | 2010-12-17 | 2012-07-04 | 无锡华润矽科微电子有限公司 | Multi-sampling rate decoding system of digital audio signal and method thereof |
| CN102543085B (en) * | 2010-12-17 | 2013-07-17 | 无锡华润矽科微电子有限公司 | Multi-sampling rate decoding system of digital audio signal and method thereof |
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