CN201928262U - Low-jitter burst type clock recovery circuit - Google Patents
Low-jitter burst type clock recovery circuit Download PDFInfo
- Publication number
- CN201928262U CN201928262U CN2011200635196U CN201120063519U CN201928262U CN 201928262 U CN201928262 U CN 201928262U CN 2011200635196 U CN2011200635196 U CN 2011200635196U CN 201120063519 U CN201120063519 U CN 201120063519U CN 201928262 U CN201928262 U CN 201928262U
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- recovery circuit
- clock recovery
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Abstract
The utility model provides a low-jitter burst type clock recovery circuit, which comprises voltage-controlled oscillators and annular oscillators. The low-jitter burst type clock recovery circuit is characterized in that the voltage-controlled oscillators are connected with the annular oscillators through voltage buffers. The clock recovery circuit provided by the utility model has simple structure, and ensures the same output frequency of the three annular oscillators through controlling the voltage at the current output points, so as to solve the problem that recovery clock changes with the change of the input data type, and realizes lower jitter characteristic compared with the traditional burst type clock recovery circuit.
Description
Technical field
The utility model relates to a kind of burst clock restore circuit, belongs to technical field of integrated circuits.
Background technology
The burst clock restore circuit since simple in structure, advantage such as reliability is high, clock recovery speed is fast be widely used.But its recovered clock shake is excessive, also may produce shake with the difference of input data type simultaneously.Traditional burst clock restore circuit can be realized control to the local clock frequency by control voltage v_ctrl as shown in Figure 2.NOR gate in next two ring oscillators is done gate, makes gate-control signal by the outer input data waveform.Enable one of two ring oscillators respectively at voltage vin rising/trailing edge.Two ring oscillator outputs are combined into recovered clock rec_clk.But this implementation method can be because intersymbol interference causes very big clock jitter.This is because the current output terminal of three chain of inverters does not interconnect.Though control voltage is identical,, current output terminal causes three ring oscillator frequency differences thereby producing voltage fluctuation owing to high-impedance state with the input code type.
The utility model content
Technical problem to be solved in the utility model provides a kind of new burst clock restore circuit, can solve the recovered clock circuit owing to the different jitter problems that cause of input data type.
For solving the problems of the technologies described above, the utility model provides a kind of low jitter burst clock restore circuit, comprises voltage controlled oscillator, ring oscillator, it is characterized in that, described voltage controlled oscillator is connected with described ring oscillator by voltage buffer.
Described voltage buffer is connected with 2 described ring oscillators respectively.
Described 2 ring oscillators are made gate by NOR gate, make gate-control signal by external input voltage.
The output of described 2 ring oscillators is output as recovered clock through a NOR gate.
The beneficial effect that the utility model reached: clock recovery circuitry of the present utility model is simple in structure, guarantee that by Control current output point voltage three ring oscillator output frequencies are identical, thereby solved the problem that recovered clock changes with the variation of importing data type, thereby realized having than the lower jittering characteristic of traditional burst clock restore circuit.
Description of drawings
Fig. 1 is low jitter burst clock restore circuit figure of the present utility model;
Fig. 2 is traditional burst clock restore circuit figure.
Embodiment
Below in conjunction with accompanying drawing the utility model is further described.Following examples only are used for the technical solution of the utility model more clearly is described, and can not limit protection range of the present utility model with this.
As shown in Figure 1, control voltage v_ctrl is the control voltage of the voltage controlled oscillator VCO of local phase-locked loop pll, and NOR gate nor1, nor2 among two ring oscillator ro1, the ro2 do gate, and vin makes gate-control signal by external input voltage.Two ring oscillator ro1, ro2 outputs are combined into recovered clock rec_clk.Low jitter burst clock restore circuit of the present utility model has added a voltage buffer buf and has limited connected two ring oscillator ro1, ro2 frequency of oscillation in former burst clock restore circuit, make the complete and local phase-locked loop pll frequency of oscillation of frequency of oscillation consistent, and do not disturb the running clock of local phase-locked loop pll.Like this, recovered clock causes the excessive problem of shake with regard to not being subjected to disturb between input data bitstream.
The above only is a preferred implementation of the present utility model; should be understood that; for those skilled in the art; under the prerequisite that does not break away from the utility model know-why; can also make some improvement and distortion, these improvement and distortion also should be considered as protection range of the present utility model.
Claims (4)
1. a low jitter burst clock restore circuit comprises voltage controlled oscillator, ring oscillator, it is characterized in that, described voltage controlled oscillator is connected with described ring oscillator by voltage buffer.
2. low jitter burst clock restore circuit according to claim 1 is characterized in that, described voltage buffer is connected with 2 described ring oscillators respectively.
3. low jitter burst clock restore circuit according to claim 2 is characterized in that, described 2 ring oscillators are made gate by NOR gate, make gate-control signal by external input voltage.
4. low jitter burst clock restore circuit according to claim 2 is characterized in that the output of described 2 ring oscillators is output as recovered clock through a NOR gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011200635196U CN201928262U (en) | 2011-03-11 | 2011-03-11 | Low-jitter burst type clock recovery circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011200635196U CN201928262U (en) | 2011-03-11 | 2011-03-11 | Low-jitter burst type clock recovery circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201928262U true CN201928262U (en) | 2011-08-10 |
Family
ID=44432096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011200635196U Expired - Lifetime CN201928262U (en) | 2011-03-11 | 2011-03-11 | Low-jitter burst type clock recovery circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201928262U (en) |
-
2011
- 2011-03-11 CN CN2011200635196U patent/CN201928262U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20110810 |
|
| CX01 | Expiry of patent term |