CN201910306U - Reverse chip resistor array and material-loading belt embedded with reverse chip resistor array - Google Patents
Reverse chip resistor array and material-loading belt embedded with reverse chip resistor array Download PDFInfo
- Publication number
- CN201910306U CN201910306U CN2010206117779U CN201020611777U CN201910306U CN 201910306 U CN201910306 U CN 201910306U CN 2010206117779 U CN2010206117779 U CN 2010206117779U CN 201020611777 U CN201020611777 U CN 201020611777U CN 201910306 U CN201910306 U CN 201910306U
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- exclusion
- pedestal
- protective layer
- layer
- electrode portion
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Abstract
The utility model discloses a reverse chip resistor array and a material-loading belt embedded with the reverse chip resistor array. For the reverse chip resistor array, a plurality of groups of resistor arrays are arranged on a base, wherein each resistor array contains a line layer arranged on the bottom surface of the base, the two electrodes of the resistor array are electrically connected and are arranged at the two ends of the line layer, a first protective layer is arranged on the line layer, and a second protective layer is arranged on the top surface of the base, therefore, the toughness and the strength of the whole structure can be improved, and the line layer can shorten the circuit path, reduce the impedance and effectively improve the product yield rate. For the material-loading belt embedded with the reverse chip resistor array, a plurality of reverse chip resistor arrays are arranged on a carrier and are sealed by a cover film; therefore, the material-loading belt can be convenient to contain, carry and use the reverse chip resistor arrays, so as to improve the service efficiency of products.
Description
Technical field
The utility model relates to a kind of exclusion structure, particularly a kind of inverse type wafer exclusion and insert the material containing band of inverse type wafer exclusion.
Background technology
General common wafer exclusion please refer to Fig. 8 and Fig. 9, and it includes a matrix 40, organizes exclusion 41, a protective layer 42 and a character code layer 43 more, and wherein, matrix 40 is rectangular susceptors of insulating ceramics material; Many group exclusions 41 compartment of terrain arrangement respectively are arranged on the matrix 40, and each exclusion 41 is an electric conductor, and includes a line layer 410 and two lateral electrodes 411, wherein, line layer 410 is arranged at matrix 40 end faces, and the two ends of 411 difference of lateral electrode connection line layer 410 are formed on the sidewall of matrix 40; Protective layer 42 adopts soft insulation material and covers and is arranged on the line layer 410; Character code layer 43 is that seal places on the protective layer 42, in order to indicate the model specification of exclusion wafer.
Yet, when general wafer exclusion is arranged on the circuit board, the circuit signal that is transmitted must be via a upwards conduction of lateral electrode 411, to feed line layer 410, and then be circulated to opposite side electrode 411 downwards, and cause that bang path is long, line resistance is big, and easily because of resistance generates heat greatly, crooked, distortion, even cause short circuit, and influence the normal operation of wafer exclusion 41.
In addition, since protective layer 42 only with single-layer type be arranged on the surface of line layer 410, therefore; it is not enough that toughness and intensity seem; avoid the collision deformation of external force or cross thermal flexure and be difficult to an overfill protection wafer exclusion, cause the fault and the damage of wafer exclusion easily, part still haves much room for improvement.
Summary of the invention
Because the circuit of existing wafer exclusion is long, impedance is big and the undercapacity of protective layer; and cause Chip-R short circuit, fault or damage easily; operate normally and influence the wafer exclusion; be head it off; the purpose of this utility model provides a kind of inverse type wafer exclusion that reduces line impedance, enhanced protection layer structure; to reach Low ESR, yield height, purpose that resistance capacity to deformation is strong, for reaching aforesaid purpose, technological means of the present utility model such as following.
The utility model provides a kind of inverse type wafer exclusion, and wherein include a pedestal, organize exclusion more, one first protective layer, one second protective layer and a character code layer, wherein:
Pedestal is an insulating base frame;
Many group exclusions can be arranged at respectively on the pedestal conductively, and each exclusion is to include a line layer and two end electrodes, and wherein, line layer is arranged on the base bottom surface; Termination electrode is electrically connected and is arranged at the two ends of line layer respectively;
First protective layer is that insulator and covering are arranged on the line layer;
Second protective layer is that insulator and covering are arranged on the base top surface; And
The character code layer is arranged on second protective layer;
Wherein, each termination electrode is formed with a top electrode portion and a hearth electrode portion respectively in bottom surface, pedestal top, and is formed with the lateral electrode portion that is electrically connected top electrode portion and hearth electrode portion on the sidewall of pedestal;
Wherein, each termination electrode is formed with a hearth electrode portion in base bottom surface, and the lateral electrode portion that is formed with an electrical connection hearth electrode portion on the sidewall of pedestal, and lateral electrode portion is not through to base top surface;
Wherein, the height of lateral electrode portion accounts for more than 1/2nd of pedestal sidewall height.
The utility model also provides a kind of material containing band of inserting inverse type wafer exclusion, and it includes a carrier, a plurality of inverse type wafer exclusion and a coverlay, wherein:
Carrier is in the form of sheets, and is equipped with a plurality of guide holes in a side, and is equipped with a plurality of containing holes in opposite side;
These a plurality of inverse type wafer exclusions are that correspondence is placed in the containing hole of this carrier, and each inverse type wafer exclusion includes a pedestal, organizes exclusion more, one first protective layer, one second protective layer and a character code layer, and wherein, pedestal is an insulating base frame; Many group exclusions can be arranged at respectively on the pedestal conductively, and each exclusion is to include a line layer and two end electrodes, and wherein, line layer is arranged on the base bottom surface; Termination electrode is electrically connected and is arranged at the two ends of line layer respectively; First protective layer is that insulator and covering are arranged on the line layer, and is posted by on the carrier when inserting; Second protective layer is that insulator and covering are arranged on the base top surface; The character code layer is arranged on second protective layer; And
Coverlay is covered on these a plurality of containing holes of carrier;
Wherein, described a plurality of containing hole is respectively a blind hole;
Wherein, described a plurality of containing holes are respectively a perforation, and these a plurality of containing holes both sides paste a coverlay respectively on carrier.
Rely on above-mentioned technological means; inverse type wafer exclusion of the present utility model and insert the material containing band of inverse type wafer exclusion; because line layer is to be arranged at base bottom surface; therefore; circuit signal can directly be passed to other end electrode by line layer apace by a termination electrode; reach and significantly shorten bang path; reduce the purpose of impedance; further; the utility model is respectively equipped with first protective layer and second protective layer in both sides up and down in pedestal; can increase whole toughness and intensity; can resist bending effectively; distortion takes place with the situation of breaking, and keeps the good channel status of line layer; promote the product yield.
Description of drawings
Fig. 1 is the stereoscopic figure of the utility model first embodiment;
Fig. 2 is that the utility model first embodiment is arranged at the part sectioned view on the circuit board;
Fig. 3 is the stereoscopic figure of the utility model second embodiment;
Fig. 4 is that the utility model second embodiment is arranged at the part sectioned view on the circuit board;
Fig. 5 is the outward appearance plane graph of material containing band of the present utility model;
Fig. 6 is the part sectioned view of material containing band of the present utility model;
Fig. 7 is the part sectioned view of another kenel material containing band of the utility model;
Fig. 8 is the stereoscopic figure of existing wafer exclusion;
Fig. 9 is the part sectioned view of existing wafer exclusion.
Embodiment
Following conjunction with figs. and preferred embodiment of the present utility model, further setting forth the utility model is to reach the technological means that predetermined utility model purpose is taked.
The utility model is about a kind of inverse type wafer exclusion and inserts the material containing band of inverse type wafer exclusion; please refer to Fig. 1 to Fig. 5; it includes a pedestal 10, organizes exclusion 11, one first protective layer 12, one second protective layer 13, a character code layer 14 and a material containing band 20 more, wherein:
First embodiment of the present utility model please refer to Fig. 1 and Fig. 2, and pedestal 10 is the pedestals that are the material that insulate, and preferably, pedestal 10 is the ceramic bodies that are rectangular shape;
First protective layer 12 adopts soft insulation material and is arranged on the line layer 110, forms insulation, protective effect in order to cover line layer 110;
Second protective layer 13 adopts soft insulation material and is arranged on pedestal 10 end faces, in order to inverse type wafer A to be provided the structural strength of integral body, and be located in pedestal 10 both sides in conjunction with first protective layer 12, in order to promote toughness, intensity and the bending resistance curvature of wafer exclusion two-wayly;
Second embodiment of the present utility model please refer to Fig. 3 and Fig. 4, and pedestal 10B, the first protective layer 12B, the second protective layer 13B are identical with first embodiment with character code layer 14B, yet the structure of each exclusion 11B is slightly different with first embodiment, illustrates as the back:
Each exclusion 11B of second embodiment of the present utility model is an electric conductor, and includes a line layer 110B and two end electrodes 111B, and wherein, line layer 110B is arranged at pedestal 10B bottom surface; Termination electrode 111B is electrically connected and is provided with the two ends of line layer 110B respectively; and form a hearth electrode portion in pedestal 10B bottom surface; and on pedestal 10B sidewall, be formed with a lateral electrode portion that is electrically connected on hearth electrode portion; the height of this lateral electrode portion is to account for more than 1/2nd of pedestal 10B sidewall height; but be not through to pedestal 10B end face; can make pedestal 10B end face keep formation state; the first protective layer 12B is set on line layer 110 again; and be provided with the second protective layer 13B in pedestal 10B end face, then be provided with character code layer 14B on the second protective layer 13B.
Because the lateral electrode portion of termination electrode 111B only is arranged on about 1/2nd of pedestal 10B sidewall height among second embodiment of the present utility model, and it is non-through to pedestal 10B end face, therefore, can reach and save the electrode material consumption, reduce the effect of cost of manufacture, moreover, can avoid lateral electrode portion to produce short circuit phenomenon because of tarnishing, can effectively increase the stability of wafer row group, it is smooth that the lateral electrode portion design that do not run through pedestal 10B end face simultaneously can make the end face of wafer exclusion keep, installing of wafer row group has convenient the absorption again, adhere to easily, be difficult for taking off material ... the effect that waits.
Please refer to Fig. 5 and Fig. 6; material containing band 20 is to be used for the packaging structure of a plurality of inverse type wafer of splendid attire exclusion A; it includes a carrier 21 and at least one coverlay 22; ccontaining these a plurality of inverse type wafer exclusion A in compartment of terrain on the carrier 21; and when inserting; the side that each inverse type wafer exclusion A is provided with first protective layer 12 is to be posted by on the carrier 21; place in order to keep the unified forward that is of each inverse type wafer exclusion A; coverlay 22 with light-permeable is attached at inverse type wafer exclusion A encapsulation on the carrier 21, wherein again:
A wherein embodiment of this material containing band 20, please refer to Fig. 6, its carrier 21 is cardboard or the sheets that are strip, and in a side continuously and the compartment of terrain be equipped with a plurality of guide holes 210, position guiding benchmark in order to as mechanically actuated operation the time, opposite side then continuously and the compartment of terrain be concaved with a plurality of containing holes 211 that shape adapts to inverse type wafer exclusion A profile, each containing hole 211 is blind holes, and in each containing hole 211 a corresponding ccontaining inverse type wafer exclusion A, paste a coverlay 22 on the carrier 21, in order to fixing encapsulation inverse type wafer exclusion A;
Another embodiment of this material containing band 20, please refer to Fig. 7, its general configuration is identical with the embodiment of Fig. 6, a plurality of containing hole 211A on the carrier 21 are perforation, and the both sides of containing hole 211A are covered with a coverlay 22 respectively on carrier 21, and inverse type wafer exclusion A is attached on the carrier 21 by the both sides encapsulation.
Inverse type wafer exclusion A of the present utility model, during use, be loaded with the material containing band 20 of inverse type wafer exclusion A prior to carry on the operation board, position by guide hole 210, and after utilizing machine to divest coverlay 22, attract the end face of inverse type wafer exclusion A that it is adhered to suction nozzle, put again and be installed on the circuit board 30, this moment, mounting means was earlier with pedestal (10,10B) be provided with first protective layer (12, side 12B) is against being arranged on the circuit board 30, utilize engagement means electric connecting terminal electrode (111 again, 111B) with circuit board 30 on circuit, can finish installation;
Because inverse type wafer exclusion A of the present utility model; its line layer (110,110B) is arranged between pedestal (10,10B) bottom surface and first protective layer (12,12B); therefore; the circuit signal of circuit board 30 can feed a termination electrode (111,111B) directly by line layer (110,110B); be passed to other end electrode (111,111B) apace; to shorten circuit paths significantly, reach and reduce impedance, minimizing problem of short-circuit.
Further; because the both sides of inverse type wafer exclusion A are respectively equipped with first protective layer (12; 12B) with second protective layer (13; 13B); not only can cover line layer (110; 110B) with pedestal (10; 10B); reach insulation and the purpose of protecting; the characteristic that relies on soft insulation material simultaneously; can strengthen the toughness and the intensity of inverse type wafer exclusion integral body; can resist effectively because of collision; vibrations; overheated ... as to wait the plain bending that is caused; distortion and the situation of breaking; can reduce line layer (110 significantly; situation about 110B) opening circuit keeps good channel status; promote the product yield.
The above only is preferred embodiment of the present utility model, be not that the utility model is done any pro forma restriction, though the utility model discloses as above with preferred embodiment, yet be not in order to limit the utility model, any those skilled in the art, in the scope that does not break away from technical solutions of the utility model, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solutions of the utility model, according to technical spirit of the present utility model to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solutions of the utility model.
Claims (7)
1. an inverse type wafer exclusion is characterized in that, include a pedestal, organize exclusion more, one first protective layer, one second protective layer and a character code layer, wherein:
Pedestal is an insulating base frame;
Many group exclusions can be arranged at respectively on the pedestal conductively, and each exclusion includes a line layer and two end electrodes, and line layer is arranged on the base bottom surface; Termination electrode is electrically connected and is arranged at the two ends of line layer respectively;
First protective layer is that insulator and covering are arranged on the line layer;
Second protective layer is that insulator and covering are arranged on the base top surface; And
The character code layer is arranged on second protective layer.
2. inverse type wafer exclusion according to claim 1, it is characterized in that, each termination electrode is formed with a top electrode portion and a hearth electrode portion respectively in bottom surface, pedestal top, and is formed with the lateral electrode portion that is electrically connected top electrode portion and hearth electrode portion on the sidewall of pedestal.
3. inverse type wafer exclusion according to claim 1, it is characterized in that, each termination electrode is formed with a hearth electrode portion in base bottom surface, and the lateral electrode portion that is formed with an electrical connection hearth electrode portion on the sidewall of pedestal, and lateral electrode portion is not through to base top surface.
4. inverse type wafer exclusion according to claim 3 is characterized in that the height of lateral electrode portion accounts for more than 1/2nd of pedestal sidewall height.
5. a material containing band of inserting inverse type wafer exclusion is characterized in that, includes a carrier, a plurality of inverse type wafer exclusion and a coverlay, wherein:
Carrier and is equipped with a plurality of guide holes in a side in the form of sheets, and is equipped with a plurality of containing holes in opposite side;
These a plurality of inverse type wafer exclusion correspondences are placed in the containing hole of this carrier, each inverse type wafer exclusion be include a pedestal, organize exclusion more, one first protective layer, one second protective layer and a character code layer, wherein, pedestal is an insulating base frame; Many group exclusions can be arranged at respectively on the pedestal conductively, and each exclusion is to include a line layer and two end electrodes, and wherein, line layer is to be arranged on the base bottom surface; Termination electrode is electrically connected and is arranged at the two ends of line layer respectively; First protective layer is that insulator and covering are arranged on the line layer, and is posted by on the carrier when inserting; Second protective layer is that insulator and covering are arranged on the base top surface; The character code layer is arranged on second protective layer; And
Coverlay is to be covered on these a plurality of containing holes of carrier.
6. material containing band of inserting inverse type wafer exclusion according to claim 5 is characterized in that described a plurality of containing holes are respectively a blind hole.
7. material containing band of inserting inverse type wafer exclusion according to claim 5 is characterized in that described a plurality of containing holes are respectively a perforation, and these a plurality of containing holes both sides paste a coverlay respectively on carrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206117779U CN201910306U (en) | 2010-11-16 | 2010-11-16 | Reverse chip resistor array and material-loading belt embedded with reverse chip resistor array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206117779U CN201910306U (en) | 2010-11-16 | 2010-11-16 | Reverse chip resistor array and material-loading belt embedded with reverse chip resistor array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201910306U true CN201910306U (en) | 2011-07-27 |
Family
ID=44302506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010206117779U Expired - Lifetime CN201910306U (en) | 2010-11-16 | 2010-11-16 | Reverse chip resistor array and material-loading belt embedded with reverse chip resistor array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201910306U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI450283B (en) * | 2012-08-24 | 2014-08-21 | ||
| CN110400668A (en) * | 2018-04-24 | 2019-11-01 | 莫列斯有限公司 | Electronic component |
-
2010
- 2010-11-16 CN CN2010206117779U patent/CN201910306U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI450283B (en) * | 2012-08-24 | 2014-08-21 | ||
| CN110400668A (en) * | 2018-04-24 | 2019-11-01 | 莫列斯有限公司 | Electronic component |
| US11037895B2 (en) | 2018-04-24 | 2021-06-15 | Molex, Llc | Electronic component |
| CN110400668B (en) * | 2018-04-24 | 2022-02-08 | 莫列斯有限公司 | Electronic component |
| CN114582578A (en) * | 2018-04-24 | 2022-06-03 | 莫列斯有限公司 | Electronic component |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20110727 |