CN201840480U - Portable dynamic electroencephalogram monitor - Google Patents
Portable dynamic electroencephalogram monitor Download PDFInfo
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- CN201840480U CN201840480U CN2010205762615U CN201020576261U CN201840480U CN 201840480 U CN201840480 U CN 201840480U CN 2010205762615 U CN2010205762615 U CN 2010205762615U CN 201020576261 U CN201020576261 U CN 201020576261U CN 201840480 U CN201840480 U CN 201840480U
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Abstract
The utility model relates to a portable dynamic electroencephalogram monitor which belongs to the field of medical devices, and consists of an electroencephalogram signal acquisition unit, an electroencephalogram signal analysis and storage unit, and an upper computer, wherein an input/output terminal of the electroencephalogram signal acquisition unit is connected with a first input/output terminal of the electroencephalogram signal analysis and storage unit, and a first digital signal input/output terminal of the electroencephalogram signal analysis and storage unit is connected with the input/output terminal of the upper computer. The portable dynamic electroencephalogram monitor is high in stability and reliability, can realize dynamic long-term monitoring on accidental, temporary, paroxysmal or characteristic electrical activities of brain without affecting normal life, learning or working of patients. The portable dynamic electroencephalogram monitor can continuously record electroencephalogram data for a long time, thus having important clinical value for the diagnosis of epilepsy and cerebrovascular disease as well as research and analysis of sleep.
Description
Technical field
This utility model belongs to medical instruments field, particularly a kind of portable dynamic brain electricity monitor.
Background technology
The intention of obtaining the people by the physiological signal of gathering human brain always is human dream, since particularly having write down electroencephalogram for the first time from Hans Berger in 1929, people just infer that it perhaps can be used for communication and control, makes brain not need common media---the help of peripheral nervous and limbs and directly effect to external world.In addition, aspect disability rehabilitation field, medical diagnosis on disease, EEG research has had practical meaning more.
Since the eighties in 20th century, human diagnostic method to cerebral disorders has produced epoch-making progress.The process of diagnosing has been simplified in the appearance of digital developing apparatus such as CT, MRI greatly, has improved the accuracy of diagnosis, and can demonstrate the sharp image that the brain structure form changes, for clinical judgment.But it can only develop to the organic disease of brain, and the functional disease of brain is not developed, and this also is its defective.
At present the brain wave monitor mainly contains following several: a kind of is that the electromechanical electroencephalograph is also referred to as the heat pen and traces the formula electroencephalograph, is according to electro-mechanical principle, by mechanical mode, according to the variation of voltage with the EEG that records on paper.A kind of is the digitized electroencephalograph, is that collection brain tele-release is big, digital-to-analogue conversion, data save as the miniature EEG signals recorder of one, and a kind of state-of-the-art technology product that combines with computer software technology.In addition, also have the brain mapping instrument, be used to write down evoked brain potential the BEP instrument, have the video electroencephalograph of video monitor and writing function etc.
Preceding a kind of electroencephalograph stability and reliability is low, can only carry out the monitoring of static short time, but we knows that the abnormal movement of brain wave might not occur continuously, and some is an instantaneous variation.Thereby accidental, of short duration, paroxysm or have a distinctive brain electrical acti to some, the monitoring of the short time of monitoring might monitor less than.And data are preserved and inquiry is very difficult.Then a kind of electroencephalograph is generally changed the EEG signals that collects through A/D after, be transferred to host computer by Serial Port Line or wireless serial or USB interface, carrying out assistant analysis by host computer handles, shows and storage, though this on a kind of preserve and inquire about more convenient, but this also is can only go to specific hospital to check, and must real-time Transmission give host computer, can have influence on patient's study orthobiosis, can increase the time of inspection so greatly.Sum up existing eeg signal acquisition system, can find to exist following shortcoming: the big power consumption of eeg signal acquisition system bulk is big, is not easy to carry, and filtering performance is bad, and existing wave filter high frequency attenuation is too slow, and is bad to the eeg signal selectivity; Poor anti jamming capability, with the variation output unstable result of individual and environment, artefact is eliminated aspects such as ability, automatic analytic function and is also had big gap.
Summary of the invention
For remedying the deficiency of said apparatus, this utility model provides a kind of portable dynamic brain electricity monitor,
The technical solution of the utility model is achieved in that this electroencephalograph is made up of eeg signal acquisition unit, electroencephalogramsignal signal analyzing memory element, host computer, the unitary input/output terminal of eeg signal acquisition connects first input/output terminal of electroencephalogramsignal signal analyzing memory element, and the first digital signal input/output terminal of electroencephalogramsignal signal analyzing memory element connects the input/output terminal of host computer;
The eeg signal acquisition unit is made up of simulation process module, analog to digital conversion circuit, driven-right-leg circuit and brain electrode, wherein, brain electrode is by first brain electrode, second brain electricity level, the n brain electrode is formed, the outfan of brain electrode connects the input of simulation processing module by the line that leads, the outfan of simulation process module connects the input of analog to digital conversion circuit, the outfan of analog to digital conversion circuit is as the unitary outfan of eeg signal acquisition, and the elementary amplification circuit output end of modulus processing module connects the input of driven-right-leg circuit;
Described simulation process module by radio frequency suppress circuit, elementary amplifying circuit, power frequency crest of flame circuit, a back level amplification filtering circuit is formed, the outfan of brain electrode connects the input that radio frequency suppresses circuit, the outfan of radio frequency inhibition circuit connects the input of elementary amplifying circuit, the outfan of elementary amplifying circuit connects the input of power frequency crest of flame circuit, the outfan of power frequency crest of flame circuit connects the input of back level amplification filtering circuit, and the outfan of back level amplification filtering circuit is as the outfan of simulation process module;
The electroencephalogramsignal signal analyzing memory element comprises digital signal processor, PLD, keyboard, memorizer, liquid crystal display screen, real-time clock, USB, first signal input output end of digital signal processor is as first input/output terminal of electroencephalogramsignal signal analyzing memory element, the input/output terminal of the second input/output terminal connected storage of digital signal processor, the 3rd input/output terminal of digital signal processor connects the input/output terminal of liquid crystal display screen, the 4th input/output terminal of digital signal processor connects the input/output terminal of real-time clock, the 5th input/output terminal of digital signal processor connects the input/output terminal of USB, the 6th input/output terminal of digital signal processor is as the second digital signal input/output terminal of electroencephalogramsignal signal analyzing memory element, the outfan of digital signal processor connects the input of PLD, first outfan of PLD connects the input of keyboard, the input of the second outfan connected storage of PLD, the 3rd outfan of PLD connects the input of liquid crystal display screen, the 4th outfan of PLD connects the input of real-time clock, the 5th outfan of PLD connects the input of USB, the input of the outfan linking number word signal processor of keyboard;
This utility model advantage: a kind of portable dynamic brain electricity of this utility model monitor, stability, reliability is high, can realize accidental, of short duration, paroxysm or have the dynamic long term monitoring of distinctive brain electrical acti, and do not influence patient's study and work orthobiosis, because but therefore the eeg data of continuous record long period has important clinic value to the diagnosis of epilepsy and cerebrovascular disease and the research and analysis of sleep.
Description of drawings
Fig. 1 is this utility model portable dynamic brain electricity monitor structured flowchart;
Fig. 2 is this utility model portable dynamic brain electricity monitor simulation process module and driven-right-leg circuit schematic diagram;
Fig. 3 is this utility model portable dynamic brain electricity monitor analog to digital conversion circuit schematic diagram;
Fig. 4 is this utility model portable dynamic brain electricity monitor analog to digital conversion circuit sequencing contro sketch map;
Fig. 5 is this utility model portable dynamic brain electricity monitor analog to digital conversion circuit and digital signal processor sketch map;
Fig. 6 (a) is this utility model portable dynamic brain electricity monitor NANDFLASH memory circuitry schematic diagram;
Fig. 6 (b) is this utility model portable dynamic brain electricity monitor SD memory circuitry schematic diagram;
Fig. 7 is this utility model portable dynamic brain electricity monitor liquid crystal display screen circuit theory diagrams;
Fig. 8 is this utility model portable dynamic brain electricity monitor real time clock circuit schematic diagram;
Wherein, 1 signal gathering unit, 2 electroencephalogramsignal signal analyzing memory element, 3 host computers, 4 simulation process modules, 5 analog to digital conversion circuits, 6 driven-right-leg circuits, 7 brain electrodes, 2-1 digital signal processor, 2-2 PLD, the 2-3 keyboard, 2-4 memorizer, 2-5 liquid crystal display screen, the 2-6 real-time clock, 2-7USB, the 4-1 radio frequency suppresses circuit, the elementary amplifying circuit of 4-2,4-3 power frequency crest of flame circuit, level amplification filtering circuit behind the 4-4.
The specific embodiment
Below in conjunction with drawings and Examples this utility model device is described in further detail:
This utility model device as shown in Figure 1, form by eeg signal acquisition unit 1, electroencephalogramsignal signal analyzing memory element 2, host computer 3, the input/output terminal of signal gathering unit 1 connects first input/output terminal of electroencephalogramsignal signal analyzing memory element 2, and the second digital signal input/output terminal of electroencephalogramsignal signal analyzing memory element 2 connects the input/output terminal of host computer 3;
Described eeg signal acquisition unit 1 is made up of simulation process module 4, analog to digital conversion circuit 5, driven-right-leg circuit 6 and brain electrode 7, wherein, brain electrode 7 is by first brain electrode, second brain electricity level, the n brain electrode is formed, the outfan of brain electrode 7 connects the input of simulating processing module 4 by the line that leads, and the outfan of simulation process module 4 connects the input of analog to digital conversion circuit 5, and the elementary amplification circuit output end of modulus processing module 4 connects the input of driven-right-leg circuit 6;
As shown in Figure 2, described simulation process module 4 suppresses circuit 4-1 by radio frequency, elementary amplifying circuit 4-2, power frequency crest of flame circuit 4-3, back level amplification filtering circuit 4-4 forms, the outfan of brain electrode 7 connects the input that radio frequency suppresses circuit 4-1, the outfan of radio frequency inhibition circuit 4-1 connects the input of elementary amplifying circuit 4-2, the outfan of elementary amplifying circuit 4-2 connects the input of power frequency crest of flame circuit 4-3, the outfan of power frequency crest of flame circuit 4-3 connects the input of back level amplification filtering circuit 4-4, and the outfan of back level amplification filtering circuit 4-4 is as the outfan of simulation process module 4;
This utility model uses a difference low pass filter to supply rf attenuation filtering in the instrument amplifier prerequisite, guarantee to remove radio-frequency (RF) energy from input as much as possible, keep the ac current signal balance between each input and the ground, and in measuring bandwidth, keeping sufficiently high input impedance to avoid reducing load capacity to input signal source, its resistor of selecting for use plays the input circuit of instrument amplifier and the isolated effect of outside source;
Radio frequency suppresses circuit 4-1 and is made up of resistance and electric capacity, resistance is made up of first resistance R 11 and second resistance R 12, electric capacity is by first capacitor C 11, second capacitor C 12 and the 3rd capacitor C 13 are formed, one end of first resistance R 11 connects brain electrode, the other end of first resistance R 11 connects an end of first capacitor C 11, radio frequency suppresses first outfan of circuit 4-1, one end of second capacitor C 12, the other end of first capacitor C 11 connects the pin 5 of elementary amplifying circuit AD623, one end of second resistance R 12 connects the reference electrode of brain electrode, the other end of second resistance R 12 connects the other end of second capacitor C 12, one end of the 3rd capacitor C 13, radio frequency suppresses second outfan of circuit 4-1, and the other end of the 3rd electric capacity R13 connects the pin 5 of elementary amplifying circuit AD623;
Elementary amplifying circuit 4-2 is by resistance, electric capacity and operational amplifier are formed, resistance is by the 3rd resistance R 13, the 4th resistance R 14, the 5th resistance R 16 is formed, operational amplifier is made up of the first operational amplifier U12A and the second operational amplifier U11, first outfan of radio frequency inhibition circuit 4-1 connects the inverting input 2 of the second operational amplifier U11, second outfan of radio frequency inhibition circuit 4-1 connects the positive input 3 of the second operational amplifier U11, the outfan 6 of second operational amplifier connects an end of the 5th resistance R 16, first outfan of elementary amplifying circuit 4-2, the other end of the 5th resistance R 16 connects the inverting input 2 of the first operational amplifier U12A, one end of the 4th capacitor C 14, the other end of the 4th capacitor C 14 connects the outfan 1 of the first operational amplifier U12A, 5 ends of the second operational amplifier U11 also meet REF1,4 termination powers of the first operational amplifier U12A, the 11 end ground connection of the first operational amplifier U12A, 1 end of the second operational amplifier U11 connects an end of the 3rd resistance R 13,8 ends of the second operational amplifier U11 connect an end of the 4th resistance R 14, the other end of the 3rd resistance R 13, the other end connection of the 4th resistance R 14 also connects elementary amplifying circuit 4-2 second outfan, 7 termination powers of the second operational amplifier U11, the 4 end ground connection of the second operational amplifier U11; Wherein, the model of the first operational amplifier U12A is AD8609AR, and the model of the second operational amplifier U11 is AD623;
Though preposition elementary amplifying circuit has stronger inhibitory action to common mode disturbances, but there is the part power frequency to disturb and enters circuit in the difference mode signal mode, and frequency is within the frequency band of EEG signals, add factors such as top electrode and input circuit instability, the EEG signals of elementary amplifying circuit output still exists stronger power frequency to disturb, so filtering specially, in fact the common 50Hz power frequency of saying is disturbed, and frequency not merely is 50Hz, the interference of the integer harmonics frequency of 50Hz can not be ignored, its amplitude is littler than the interference of 50Hz, and can other harmonic wave of filtering when low-pass filtering, therefore only do the trap of 50Hz here, the active double T rejector circuit that utilizes that twin-T network and operational amplifier constitute suppresses the power frequency 50Hz of bio signal in surveying and disturbs;
Power frequency crest of flame circuit 4-3 is made up of resistance, electric capacity, operational amplifier, wherein, resistance is made up of the 6th resistance R X31, the 7th resistance R X32, the 8th resistance R X33, the 9th resistance R X34, the tenth resistance R X35, the 11 resistance R X36 and the 12 resistance R X37, electric capacity is made up of the 5th capacitor C X31, the 6th capacitor C X32, the 7th capacitor C X33 and the 8th capacitor C X34, and operational amplifier is made up of the 3rd operational amplifier UX2A, four-operational amplifier UX2B; First outfan of elementary amplifying circuit 4-2 connects the end of the 6th resistance R X31, the other end of the 6th resistance R X31 connects the end of the 7th resistance R X32, the end of the 7th capacitor C X33, the other end of the 7th resistance R X32, the end of the 8th resistance R X33 links to each other and connects the end of the 5th capacitor C X31, the end of the 6th capacitor C X32, the other end of the 5th capacitor C X31, the other end of the 6th capacitor C X32 links to each other and connects the end of the 9th resistance R X34, the end of the tenth resistance R X35, the outfan 7 of four-operational amplifier UX2B, the other end of the 9th resistance R X34, the other end of the tenth resistance R X35 links to each other, and connect the other end of the 7th capacitor C X33, the end of the 8th capacitor C X34, the other end of the 8th resistance R X34 connects the normal phase input end 3 of the 3rd operational amplifier UX2A, the other end of the 8th resistance R X33, the inverting input 2 of the 3rd operational amplifier UX2A connects the outfan 1 of the 3rd operational amplifier UX2A, the outfan of power frequency crest of flame circuit 4-3, the end of the 11 resistance R X36,4 termination powers of the 3rd operational amplifier UX2A, the 11 end ground connection of the 3rd operational amplifier UX2A, the other end of the 11 resistance R X36, the end of the 12 resistance R X37 links to each other and connects another termination simulation ground of normal phase input end 5, the 12 resistance R X37 of four-operational amplifier UX2B; Wherein, the model of the 3rd operational amplifier UX2A and four-operational amplifier UX2B is AD8609AR;
Back level amplification filtering circuit is made up of filtering and amplifying circuit two parts, adopt a single order active filter to connect with an amplifier, the back level that forms native system is amplified and filter circuit, the low-pass filter circuit formed of R18 and C15 wherein, the amplifying circuit that R17 and R18 form, back two-stage is enlarged into 39 times; When frequency input signal changes, have only the impedance of electric capacity to be affected: when frequency input signal was very low, electric capacity was equivalent to open circuit, and amplifier was equivalent to have amplification and was this moment
Amplifier; Input signal is at the upper frequency place, and electric capacity is equivalent to short circuit, and the output head grounding of amplifier plays the effect of filtering high-frequency signal at this moment;
Back level amplification filtering circuit 4-4 is by resistance, electric capacity and operational amplifier are formed, wherein, resistance is by the 13 resistance R 17, the 14 resistance R 18, the 15 resistance R 19, the 16 resistance 10 is formed, electric capacity is by the 9th capacitor C 15, the tenth capacitor C 16 is formed, operational amplifier is by the 5th operational amplifier U12B, the 6th operational amplifier U12C forms, the outfan of power frequency crest of flame circuit 4-3 connects an end of the 13 resistance R 17, the other end of the 13 resistance R 17 connects an end of the 14 resistance R 18, one end of the 9th capacitor C 15, the inverting input 6 of the 5th operational amplifier U12B, the normal phase input end of the 5th operational amplifier U12B connects simulation ground, the other end of the 14 resistance R 18, the other end of the 9th capacitor C 15 links to each other and connects the outfan 7 of the 5th operational amplifier U12B, one end of the 15 resistance R 19, the other end of the 15 resistance R 15 connects an end of the 16 resistance R 16, one end of the tenth capacitor C 16, the inverting input 9 of the 6th operational amplifier U12C, the normal phase input end 10 of the 6th operational amplifier U12C connects simulation ground, the other end of the 16 resistance R 10, the other end of the tenth capacitor C 16 connects the outfan 8 of the 6th operational amplifier U12C, the outfan OUT of back level amplification filtering circuit 4-4; Wherein, the model of the 5th operational amplifier U12B and the 6th operational amplifier U12C is AD8609AR;
In the amplification process of signal, in order to suppress common-mode voltage, need to use the higher instrument amplifier of common mode rejection ratio, but the common-mode signal that two inputs of instrument amplifier are subjected to influence may be different, the difference of the common-mode signal that these are different just is incorporated into before the instrument amplifier as difference mode signal, and instrument amplifier can not suppress difference mode signal, thereby introduces noise; Present embodiment solves this problem by the mode that reduces common-mode voltage, and in driven-right-leg circuit, the COM of instrument amplifier end is drawn common-mode signal, again common-mode signal is taken back human body with degenerative form, thereby reaches the purpose that reduces common-mode signal;
Driven-right-leg circuit 6 is by resistance, electric capacity and operational amplifier are formed, resistance is by the 11 resistance R 15, the 12 resistance R R1, the 13 resistance R R2 forms, electric capacity is by the 11 capacitor C R3, the 12 capacitor C R4 forms, operational amplifier is by the 7th operational amplifier U12D, the 8th operational amplifier URA forms, second outfan of elementary amplifying circuit 4-2 connects the normal phase input end 12 of the 7th operational amplifier U12D, the inverting input 13 of the 7th operational amplifier U12D connects the outfan 14 of the 7th operational amplifier U12D, one end of the 11 resistance R 15, the other end of the 11 resistance R 15 connects the end of the 12 resistance R R1, the end of the 11 capacitor C R3, the inverting input 2 of the 8th operational amplifier URA, the other end of the 12 resistance R R1, the other end of the 11 capacitor C R3 links to each other and connects the outfan 1 of the 8th operational amplifier URA, the end of the 13 resistance R R2, the end of the 12 capacitor C R4, the other end of the 13 resistance R R2 connects the other end of the 12 capacitor C R4; Wherein, the model of the 7th operational amplifier U12D is AD8609AR, and the model of the 8th operational amplifier URA is OP296GRU;
Analog to digital conversion circuit 5 as shown in Figure 3, form by operational amplifier, modulus conversion chip, reference source chip, resistance, electric capacity, wherein, resistance is made up of first resistance R 65, second resistance R 62, the 3rd resistance R 61, and electric capacity is made up of first capacitor C 610, second capacitor C 63, the 3rd capacitor C 62, the 4th electrochemical capacitor EC61; 2 feet of modulus conversion chip U2 connect an end of first capacitor C 610, another termination simulation ground of first capacitor C 610,3 feet of modulus conversion chip U2 connect 6 feet of reference source chip U1, one end of second capacitor C 63, another termination simulation ground of second capacitor C 63,2 feet of reference source chip U1 connect an end of the 3rd capacitor C 62, the end of the 4th electrochemical capacitor EC61 also connects+the 3.3V power supply, 4 feet of reference source chip U1 connect the other end of the 3rd capacitor C 62, the other end of the 4th electrochemical capacitor EC61 also connects simulation ground, the outfan 6 of the 19 foot concatenation operation amplifier U6_1 of modulus conversion chip U2, the inverting input 2 of operational amplifier U6_1, the normal phase input end of operational amplifier U6_1 connects the outfan OUT of back level amplification filtering circuit 4-4,8 feet of operational amplifier U6_1 connect an end of second resistance R 62, one end of the 3rd resistance R 61, another termination simulation ground of second resistance R 62, the other end of the 3rd resistance R 61+3.3V power supply, 10 feet of modulus conversion chip U2 connect simulation ground, 15 feet of modulus conversion chip U2 connect an end of first resistance R 65, and with 1 foot of modulus conversion chip U2,20 feet link to each other and connect+the 3.3V power supply, the other end of first resistance R 65 connects 14 feet of modulus conversion chip U2, the E2 foot of digital signal processor 2-1,11 feet of modulus conversion chip U2 connect 71 feet of PLD 2-2,13 feet of modulus conversion chip U2,12 feet are the D1 foot of linking number word signal processor 2-1 successively, the D3 foot; Wherein, the model of reference source chip is ADR441, and the model of modulus conversion chip is AD7689, and the model of operational amplifier is ADA4841-1;
Because EEG signals is 16 the tunnel, so need to use two AD7689 to satisfy the requirement of signalling channel way.Present embodiment is put height 16 road signals of sampling simultaneously by the CNV end of giving two ADC simultaneously, sequential chart during two ADC as shown in Figure 4, use program flow diagram that two ADC carry out 16 circuit-switched data AD conversion as shown in Figure 5, at first provide CNV according to normal sequential to first ADC, preceding 8 road signals are changed normally, this moment, the CNV of second ADC still was in high level, promptly still was in hold mode.Because CNV is in low level state when sending data, therefore after first ADC conversion and transmission finish 8 the tunnel, continue keeping CNV is low level, simultaneously the CNV of second ADC is put lowly, and beginning is conversion normally, when second ADC also changes and transmit when finishing 8 the tunnel, the CNV of two ADC is put height simultaneously, and the conversion of beginning next cycle is less than the time that ADC changes because DSP reads the time of data, therefore the AD conversion is carried out always, and can not cause the problems such as covering of data;
Analog to digital conversion circuit 5 is connected as shown in Figure 5 with digital signal processor 2-1, and wherein, the model of programmable logic device (CPLD) is EPM570T144C5, and the model of digital signal processor is ADSP-BF533; 7 feet of EPM570T144C5,141 feet, 142 feet, 143 feet, 121 feet, 122 feet, 123 feet, 124 feet, 125 feet, 127 feet, 129 feet, 130 feet, 109 feet, 110 feet, 111 feet, 112 feet, 113 feet, 114 feet, 117 feet, 118 feet, 119 feet, 120 feet connect the D2 foot successively, the E2 foot, the D1 foot, the D3 foot, the M9 foot, the N9 foot, the P9 foot, the M8 foot, the N8 foot, the P8 foot, the M7 foot, the N7 foot, the M13 foot, the M14 foot, the N14 foot, the N13 foot, the N12 foot, the M11 foot, the N11 foot, the P13 foot, the P12 foot, the P11 foot;
Described electroencephalogramsignal signal analyzing memory element 2 comprises digital signal processor 2-1, PLD 2-2, keyboard 2-3, memorizer 2-4, liquid crystal display screen 2-5, real-time clock 2-6, USB2-7, first signal input output end of digital signal processor 2-1 is as the input/output terminal of electroencephalogramsignal signal analyzing memory element 2, the input/output terminal of the second input/output terminal connected storage 2-4 of digital signal processor 2-1, the 3rd input/output terminal of digital signal processor 2-1 connects the input/output terminal of liquid crystal display screen 2-5, the 4th input/output terminal of digital signal processor 2-1 connects the input/output terminal of real-time clock 2-6, the 5th input/output terminal of digital signal processor 2-1 connects the input/output terminal of USB2-7, the 6th input/output terminal of digital signal processor 2-1 is as the digital signal input/output terminal of electroencephalogramsignal signal analyzing memory element 2, the outfan of digital signal processor 2-1 connects the input of PLD 2-2, first outfan of PLD 2-2 connects the input of keyboard 2-3, the input of the second outfan connected storage 2-4 of PLD 2-2, the 3rd outfan of PLD 2-2 connects the input of liquid crystal display screen 2-5, the 4th outfan of PLD 2-2 connects the input of real-time clock 2-6, the 5th outfan of PLD 2-2 connects the input of USB2-7, the input of the outfan linking number word signal processor 2-1 of keyboard 2-3;
Memorizer 2-4 such as Fig. 6 (a), shown in Fig. 6 (b), Fig. 6 (a) is NANDFLASH memorizer and digital signal processor 2-1 circuit theory diagrams, comprise resistance, electric capacity, the NANDFLASH memorizer, resistance is by first resistance R 101, second resistance R 102, the 3rd resistance R 17, the 4th resistance R 16, the 5th resistance R 15, the 6th resistance R 14 is formed, the model of described NANDFLASH memorizer is K9F1G08U0A, 19 feet of NANDFLASH memorizer U10 connect an end of first resistance R 101, the other end of first resistance R 101 connects an end of second resistance R 102 and connects the 3.3V power supply, the other end of the other end R102 of second resistance connects an end of the 3rd resistance R 17,7 feet of NANDFLASH memorizer U10, the A5 end of the other end linking number word signal processor 2-1 of the 3rd resistance R 17, the foot 9 of NANDFLASH memorizer U10 connects an end of the 4th resistance R 16, the A4 end of the other end linking number word signal processor 2-1 of the 4th resistance R 16,8 feet of NANDFLASH memorizer U10,18 feet are the H14 foot of linking number word signal processor 2-1 successively, the G14 foot, 17 feet of NANDFLASH memorizer U10 connect an end of the 5th resistance R 15, the K14 foot of the other end linking number word signal processor 2-1 of the 5th resistance R 15,16 feet of NANDFLASH memorizer U10 connect an end of the 6th resistance R 14, the L14 end of the other end linking number word signal processor 2-1 of the 6th resistance R 14,12 feet of NANDFLASH memorizer U10,37 feet link to each other and connect the 3.3V power supply; 29 feet of NANDFLASH memorizer U10～33 feet, 42 feet～44 feet are M9 foot, N9 foot, P9 foot, M8 foot, N8 foot, P8 foot, M7 foot, the N7 foot of linking number word signal processor 2-1 successively, and 13 feet of NANDFLASH memorizer U10,36 feet link to each other and ground connection;
Fig. 6 (b) is a SD memory circuitry schematic diagram, by resistance, the SD memorizer is formed, wherein, resistance is by first resistance R 10, second resistance R 11, the 3rd resistance R 18, the 4th resistance R 19, the 5th resistance R 12, the 6th resistance R 13 is formed, 1 foot of SD memorizer TF, 8 feet connect an end of first resistance R 10 respectively, one end of second resistance R 11, the other end of first resistance R 10, the other end of second resistance R 11,4 feet of SD memorizer TF link to each other and connect+the 3.3V power supply, 2 feet of SD memorizer TF connect an end of the 3rd resistance R 18,144 feet of PLD 2-2,5 feet of SD memorizer TF connect an end of the 4th resistance R 19, the D1 foot of digital signal processor 2-1,3 feet of SD memorizer TF connect an end of the 5th resistance R 12, the D3 foot of digital signal processor 2-1,7 feet of SD memorizer TF connect an end of the 6th resistance R 13, the E2 foot of digital signal processor 2-1, the 3rd resistance R 18, the 4th resistance R 19, the 5th resistance R 12, the other end of the 6th resistance R 13 links to each other and connects+the 3.3V power supply; Wherein the model of SD memorizer is TF CARD;
Liquid crystal display screen 2-5 as shown in Figure 7, by the bus driver chip, liquid crystal display screen, resistance is formed, the bus driver chip is made up of the first bus driver chip U21 and the second bus driver chip U22, resistance is made up of first resistance R 21 and second resistance R 22,19 feet of the first bus driver chip U21 connect 66 feet of PLD 2-2, one end of second resistance R 22,1 foot of the first bus driver chip U21 connects an end of first resistance R 21,1 foot of the second bus driver chip U22, the other end of first resistance R 21 connects the other end of second resistance R 22 and connects the 3.3V power supply, 2～9 feet of the first bus driver chip U21 are the B5 foot of linking number word signal processor 2-1 successively, the B6 foot, the A6 foot, the C6 foot, the B7 foot, the A7 foot, the B8 foot, the C8 foot, 11～18 feet of the first bus driver chip U21 connect 1 foot of liquid crystal display screen successively, 3 feet, 5 feet, 7 feet, 9 feet, 11 feet, 13 feet, 15 feet, the 10 foot ground connection of the first bus driver chip U21,1 foot of the second bus driver chip U22 connects the other end of first resistance R 21,5 feet of the second bus driver chip U22,7 feet are the K2 foot of linking number word signal processor 2-1 successively, the M1 foot, 17 feet of the second bus driver chip U22,15 feet, 13 feet connect 17 feet of liquid crystal display screen successively, 19 feet, 21 feet, 2 feet of the second bus driver chip U22,4 feet, 6 feet, 8 feet, 9 feet, 10 feet link to each other and ground connection;
Real-time clock 2-6 as shown in Figure 8, by real-time timepiece chip, resistance, electric capacity, crystal oscillator is formed, wherein, resistance is by first resistance R 96, second resistance R 97, the 3rd resistance R 98, the 4th resistance R 99 is formed, electric capacity is by first capacitor C 92, second capacitor C 93, the 3rd capacitor C 94 is formed, 1 foot of real-time timepiece chip U9 connects the end of crystal oscillator Y4, one end of first capacitor C 92, one end of second capacitor C 93, one end of the 3rd capacitor C 94, the other end of first capacitor C 92, the other end of second capacitor C 93, the other end of the 3rd capacitor C 94 links to each other and ground connection, the other end of crystal oscillator Y4 connects 2 feet of real-time timepiece chip U9,8 feet of real-time timepiece chip U9 connect battery, 7 feet of real-time timepiece chip U9 connect an end of first resistance R 96,6 feet of real-time timepiece chip U9 connect an end of second resistance R 97, the D2 foot of digital signal processor 2-1,5 feet of real-time timepiece chip U9 connect an end of the 3rd resistance R 98, the C1 end of digital signal processor 2-1,3 feet of real-time timepiece chip U9 connect an end of the 4th resistance R 99,1 foot of PLD 2-2, the other end of first resistance R 96, the other end of second resistance R 97, the other end of the 3rd resistance R 98, the other end of the 4th resistance R 99 links to each other and connects+the 3.3V power supply.
Claims (4)
1. portable dynamic brain electricity monitor, comprise host computer, it is characterized in that: this device also comprises eeg signal acquisition unit, electroencephalogramsignal signal analyzing memory element, the unitary input/output terminal of eeg signal acquisition connects first input/output terminal of electroencephalogramsignal signal analyzing memory element, and the first digital signal input/output terminal of electroencephalogramsignal signal analyzing memory element connects the input/output terminal of host computer.
2. portable dynamic brain electricity monitor according to claim 1, it is characterized in that: described eeg signal acquisition unit is by the simulation process module, analog to digital conversion circuit, driven-right-leg circuit and brain electrode are formed, wherein, brain electrode is by first brain electrode, second brain electricity level, the n brain electrode is formed, the outfan of brain electrode connects the input of simulation processing module by the line that leads, the outfan of simulation process module connects the input of analog to digital conversion circuit, the outfan of analog to digital conversion circuit is as the unitary outfan of eeg signal acquisition, and the elementary amplification circuit output end of modulus processing module connects the input of driven-right-leg circuit.
3. portable dynamic brain electricity monitor according to claim 2, it is characterized in that: described simulation process module suppresses circuit by radio frequency, elementary amplifying circuit, power frequency crest of flame circuit, back level amplification filtering circuit is formed, the outfan of brain electrode connects the input that radio frequency suppresses circuit, the outfan of radio frequency inhibition circuit connects the input of elementary amplifying circuit, the outfan of elementary amplifying circuit connects the input of power frequency crest of flame circuit, the outfan of power frequency crest of flame circuit connects the input of back level amplification filtering circuit, and the outfan of back level amplification filtering circuit is as the outfan of simulation process module.
4. portable dynamic brain electricity monitor according to claim 1, it is characterized in that: described electroencephalogramsignal signal analyzing memory element comprises digital signal processor, PLD, keyboard, memorizer, liquid crystal display screen, real-time clock, USB interface, first signal input output end of digital signal processor is as first input/output terminal of electroencephalogramsignal signal analyzing memory element, the input/output terminal of the second input/output terminal connected storage of digital signal processor, the 3rd input/output terminal of digital signal processor connects the input/output terminal of liquid crystal display screen, the 4th input/output terminal of digital signal processor connects the input/output terminal of real-time clock, the 5th input/output terminal of digital signal processor connects the input/output terminal of USB, the 6th input/output terminal of digital signal processor is as the second digital signal input/output terminal of electroencephalogramsignal signal analyzing memory element, the outfan of digital signal processor connects the input of PLD, first outfan of PLD connects the input of keyboard, the input of the second outfan connected storage of PLD, the 3rd outfan of PLD connects the input of liquid crystal display screen, the 4th outfan of PLD connects the input of real-time clock, the 5th outfan of PLD connects the input of USB, the input of the outfan linking number word signal processor of keyboard.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205762615U CN201840480U (en) | 2010-10-26 | 2010-10-26 | Portable dynamic electroencephalogram monitor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010205762615U CN201840480U (en) | 2010-10-26 | 2010-10-26 | Portable dynamic electroencephalogram monitor |
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| CN201840480U true CN201840480U (en) | 2011-05-25 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101966080A (en) * | 2010-10-26 | 2011-02-09 | 东北大学 | Portable active electroencephalogram monitor and control method thereof |
| CN102613971A (en) * | 2012-03-30 | 2012-08-01 | 北京品驰医疗设备有限公司 | Electroencephalograph (EEG)-based epilepsy detection and intervention device |
| CN103239227A (en) * | 2012-02-07 | 2013-08-14 | 联想(北京)有限公司 | Sleep quality detection device and sleep quality detection method |
| CN108542384A (en) * | 2018-03-09 | 2018-09-18 | 王永新 | A kind of brain wave intelligent monitor system and its method |
| CN112394226A (en) * | 2019-08-16 | 2021-02-23 | Oppo广东移动通信有限公司 | Signal detection circuit and electronic device |
| CN116584953A (en) * | 2022-12-30 | 2023-08-15 | 北京津发科技股份有限公司 | Improved electroencephalogram signal acquisition system and device |
-
2010
- 2010-10-26 CN CN2010205762615U patent/CN201840480U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101966080A (en) * | 2010-10-26 | 2011-02-09 | 东北大学 | Portable active electroencephalogram monitor and control method thereof |
| CN101966080B (en) * | 2010-10-26 | 2012-06-20 | 东北大学 | Portable active electroencephalogram monitor and control method thereof |
| CN103239227A (en) * | 2012-02-07 | 2013-08-14 | 联想(北京)有限公司 | Sleep quality detection device and sleep quality detection method |
| CN103239227B (en) * | 2012-02-07 | 2015-11-25 | 联想(北京)有限公司 | sleep quality detection device and detection method thereof |
| CN102613971A (en) * | 2012-03-30 | 2012-08-01 | 北京品驰医疗设备有限公司 | Electroencephalograph (EEG)-based epilepsy detection and intervention device |
| CN108542384A (en) * | 2018-03-09 | 2018-09-18 | 王永新 | A kind of brain wave intelligent monitor system and its method |
| CN112394226A (en) * | 2019-08-16 | 2021-02-23 | Oppo广东移动通信有限公司 | Signal detection circuit and electronic device |
| CN116584953A (en) * | 2022-12-30 | 2023-08-15 | 北京津发科技股份有限公司 | Improved electroencephalogram signal acquisition system and device |
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