CN201830238U - Frequency synthesis circuit - Google Patents
Frequency synthesis circuit Download PDFInfo
- Publication number
- CN201830238U CN201830238U CN2010205578710U CN201020557871U CN201830238U CN 201830238 U CN201830238 U CN 201830238U CN 2010205578710 U CN2010205578710 U CN 2010205578710U CN 201020557871 U CN201020557871 U CN 201020557871U CN 201830238 U CN201830238 U CN 201830238U
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- resistance
- main control
- control chip
- electric capacity
- frequency
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Abstract
The utility model relates to a frequency synthesis technology, in particular to a frequency synthesis circuit, solving the problems of large volume, complex debugging and inflexible control and use of the current frequency synthesis technology. The frequency synthesis circuit comprises a main control chip; an address terminal of the main control chip is connected with a frequency selection terminal; a counter input terminal of the main control chip is connected with a high-frequency signal source which comprises a tenth capacitor, an eleventh capacitor, a magnetic core and an integration amplifier circuit; and the counter input terminal of the main control chip is connected with the integration amplifier circuit by the tenth capacitor, and the magnetic core is connected with the integration amplifier circuit by the eleventh capacitor. The frequency synthesis circuit has simple structure and reasonable design, effectively solves the problems of large volume, complex debugging and inflexible control and use of the current frequency synthesis technology, and is applicable to frequency synthesis.
Description
Technical field
The utility model relates to frequency synthesis technique, specifically is a kind of frequency synthesizer circuit.
Background technology
Frequency synthesis technique is mainly used in various need Source Music, wireless launchers etc. in precise frequency and the warbled electronic equipment, and its function is the oscillator signal that accurately produces characteristic frequency.The frequency synthesis of electronic equipment in the past all is that frequency of oscillation with one or more quartz oscillator is as reference frequency, produce a series of harmonic wave by these reference frequencies, these harmonic waves have frequency stability and the accuracy same with quartz oscillator; Then, from a series of harmonic wave, take out two or more frequencies and make up, draw these frequencies and or poor, pass through after suitable mode handles, obtain needed frequency.Frequency mixer and filter that this frequency synthesis technique is required are more, thereby have that volume is big, debugging is complicated, inflexible problem is used in control, have restricted design of electronic devices thus.Be necessary for this reason to invent that a kind of volume is little, debugging is simple, novel frequency combiner circuit is flexibly used in control.
Summary of the invention
Existing frequency synthesis technique volume is big, debugging is complicated in order to solve, inflexible problem is used in control for the utility model, and a kind of frequency synthesizer circuit is provided.
The utility model is to adopt following technical scheme to realize: frequency synthesizer circuit comprises main control chip; The address end of main control chip is connected with frequency and selects terminal; The counter input of main control chip is connected with high-frequency signal source, and described high-frequency signal source comprises the tenth electric capacity, the 11 electric capacity, magnetic core and integrated operational amplifier circuit; Wherein, the counter input of main control chip links to each other with integrated operational amplifier circuit by the tenth electric capacity, and magnetic core links to each other with integrated operational amplifier circuit by the 11 electric capacity; The phase discriminator output of main control chip is connected with impedance matching circuit, and described impedance matching circuit comprises first resistance, second resistance, the 5th resistance, the 6th resistance, the 4th electric capacity and the 5th electric capacity; Wherein, the series arm that is formed by first resistance, the 5th resistance, the 6th resistance serial connection links to each other with the phase discriminator output of main control chip, the series arm that is formed by second resistance, the 4th capacitance series is connected between first resistance and the 5th resistance, and the 5th electric capacity is connected between the 5th resistance and the 6th resistance; Be connected with reference signal source between the reference oscillator input of main control chip and the output; Described reference signal source comprises crystal oscillator and first electric capacity-the 3rd electric capacity; Wherein, the crystal oscillator two ends link to each other with output with the reference oscillator input of main control chip respectively, first electric capacity links to each other with the reference oscillator output of main control chip, by second electric capacity with the 3rd electric capacity and connect the parallel branch that forms and link to each other with the reference oscillator input of main control chip; The power end of main control chip is connected with bleeder circuit, and described bleeder circuit comprises the 6th electric capacity-the 9th electric capacity, first inductance, the 3rd resistance and the 4th resistance; Wherein, the 3rd resistance links to each other with the power end of main control chip, and the 4th resistance links to each other with the power end of integrated operational amplifier circuit.
During work, power supply is powered to main control chip and integrated operational amplifier circuit respectively by bleeder circuit; Magnetic core and the 11 electric capacity are formed oscillating circuit and are sent oscillator signal, and oscillator signal is input to the counter input of main control chip after integrated operational amplifier circuit amplifies; Frequency selects terminal to utilize the divider ratio of the binary code of high-low level composition as reference frequency; The reference signal source output signal is as the reference signal of reference oscillator; Impedance matching circuit is as synthetic high-frequency signal output.Compare with existing frequency synthesis technique, frequency synthesizer circuit described in the utility model has that volume is little, debugging is simple, flexible characteristic is used in control.
The utility model is simple in structure, reasonable in design, efficiently solves that existing frequency synthesis technique volume is big, debugging is complicated, inflexible problem is used in control, is applicable to frequency synthesis.
Description of drawings
Fig. 1 is circuit theory diagrams of the present utility model.
Embodiment
Frequency synthesizer circuit comprises main control chip U1; The address end of main control chip U1 is connected with frequency and selects terminal U2; The counter input of main control chip U1 is connected with high-frequency signal source, and described high-frequency signal source comprises the tenth capacitor C the 10, the 11 capacitor C 11, magnetic core B1 and integrated operational amplifier circuit IC1; Wherein, the counter input of main control chip U1 links to each other with integrated operational amplifier circuit IC1 by the tenth capacitor C 10, and magnetic core B1 links to each other with integrated operational amplifier circuit IC1 by the 11 capacitor C 11; The phase discriminator output of main control chip U1 is connected with impedance matching circuit, and described impedance matching circuit comprises first resistance R 1, second resistance R 2, the 5th resistance R 5, the 6th resistance R 6, the 4th capacitor C 4 and the 5th capacitor C 5; Wherein, the series arm that is formed by first resistance R 1, the 5th resistance R 5, the 6th resistance R 6 serial connections links to each other with the phase discriminator output of main control chip U1, the series arm that is formed by second resistance R 2, the 4th capacitor C 4 serial connections is connected between first resistance R 1 and the 5th resistance R 5, and the 5th capacitor C 5 is connected between the 5th resistance R 5 and the 6th resistance R 6; Be connected with reference signal source between the reference oscillator input of main control chip U1 and the output; Described reference signal source comprises crystal oscillator XT1 and first electric capacity-the 3rd capacitor C 1-C3; Wherein, crystal oscillator XT1 two ends link to each other with output with the reference oscillator input of main control chip U1 respectively, first capacitor C 1 links to each other with the reference oscillator output of main control chip U1, by second capacitor C 2 with the 3rd capacitor C 3 and connect the parallel branch that forms and link to each other with the reference oscillator input of main control chip U1; The power end of main control chip U1 is connected with bleeder circuit, and described bleeder circuit comprises the 6th electric capacity-the 9th capacitor C 6-C9, first inductance L 1, the 3rd resistance R 3 and the 4th resistance R 4; Wherein, the 3rd resistance R 3 links to each other with the power end of main control chip U1, and the 4th resistance R 4 links to each other with the power end of integrated operational amplifier circuit IC1; During concrete enforcement, main control chip U1 adopts integrated circuit MC145151-2, and integrated operational amplifier circuit IC1 adopts four end integrated operational amplifier circuits.
Claims (1)
1. a frequency synthesizer circuit is characterized in that: comprise main control chip (U1); The address end of main control chip (U1) is connected with frequency and selects terminal (U2); The counter input of main control chip (U1) is connected with high-frequency signal source, and described high-frequency signal source comprises the tenth electric capacity (C10), the 11 electric capacity (C11), magnetic core (B1) and integrated operational amplifier circuit (IC1); Wherein, the counter input of main control chip (U1) links to each other with integrated operational amplifier circuit (IC1) by the tenth electric capacity (C10), and magnetic core (B1) links to each other with integrated operational amplifier circuit (IC1) by the 11 electric capacity (C11); The phase discriminator output of main control chip (U1) is connected with impedance matching circuit, and described impedance matching circuit comprises first resistance (R1), second resistance (R2), the 5th resistance (R5), the 6th resistance (R6), the 4th electric capacity (C4) and the 5th electric capacity (C5); Wherein, the series arm that is formed by first resistance (R1), the 5th resistance (R5), the 6th resistance (R6) serial connection links to each other with the phase discriminator output of main control chip (U1), the series arm that is formed by second resistance (R2), the 4th electric capacity (C4) serial connection is connected between first resistance (R1) and the 5th resistance (R5), and the 5th electric capacity (C5) is connected between the 5th resistance (R5) and the 6th resistance (R6); Be connected with reference signal source between the reference oscillator input of main control chip (U1) and the output; Described reference signal source comprises crystal oscillator (XT1) and first electric capacity-the 3rd electric capacity (C1-C3); Wherein, crystal oscillator (XT1) two ends link to each other with output with the reference oscillator input of main control chip (U1) respectively, first electric capacity (C1) links to each other with the reference oscillator output of main control chip (U1), by second electric capacity (C2) with the 3rd electric capacity (C3) and connect the parallel branch that forms and link to each other with the reference oscillator input of main control chip (U1); The power end of main control chip (U1) is connected with bleeder circuit, and described bleeder circuit comprises the 6th electric capacity-the 9th electric capacity (C6-C9), first inductance (L1), the 3rd resistance (R3) and the 4th resistance (R4); Wherein, the 3rd resistance (R3) links to each other with the power end of main control chip (U1), and the 4th resistance (R4) links to each other with the power end of integrated operational amplifier circuit (IC1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205578710U CN201830238U (en) | 2010-10-12 | 2010-10-12 | Frequency synthesis circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205578710U CN201830238U (en) | 2010-10-12 | 2010-10-12 | Frequency synthesis circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201830238U true CN201830238U (en) | 2011-05-11 |
Family
ID=43968751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010205578710U Expired - Fee Related CN201830238U (en) | 2010-10-12 | 2010-10-12 | Frequency synthesis circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201830238U (en) |
-
2010
- 2010-10-12 CN CN2010205578710U patent/CN201830238U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110511 Termination date: 20131012 |