CN201774614U - Hardware circuit of composite video conversion interface - Google Patents

Abstract

The utility model discloses a hardware circuit of a composite video conversion interface, which belongs to a part of a three-dimensional display system consisting of two ways of composite video signal input, a subsequent liquid-crystal display screen and a power switchboard. The hardware circuit comprises an FPGA (Field Programmable Gate Array), an ADV7181B video decoding chip, a P89LPC935FDH single-chip microcomputer; the single-chip microcomputer is connected with the ADV7181B video decoding chip for I2C configuration; and an external crystal oscillator, the ADV7181B video decoding chip, the power switchboard and the liquid-crystal display screen are respectively connected with the FPGA.

Description

The hardware circuit of composite video translation interface

Technical field

The utility model relates to the 3 d display device field, and the digital interface of 3 d display device especially is specially a kind of hardware circuit of composite video translation interface.

Background technology

Along with developing rapidly of computer, multimedia and digital communication, make that video technique obtains promoting and advancing, make that also the interface conversion problem between the different digital display device becomes increasingly conspicuous.Particularly in the stereo display technique field, IMAQ is the important component part of real time image processing system, to the current stereo-picture of real-time demonstration, composite video signal is treated as key technology, so the hardware circuit design of composite video translation interface more and more comes into one's own.

The utility model content

The purpose of this utility model provides a kind of hardware circuit of composite video translation interface, with realization the vision signal of the pal mode of input is changed.

In order to achieve the above object, the technical scheme that the utility model adopted is:

The hardware circuit of composite video translation interface, include fpga chip, described fpga chip is circumscribed with crystal oscillating circuit, power switch circuit, liquid crystal display screen, it is characterized in that: also include video decoding chip and single-chip microcomputer, the Data Input Interface of described video decoding chip is connected with the communication of outer video signal source, the data output interface of video decoding chip is connected the I of described single-chip microcomputer with the Data Input Interface communication of FPGA ²C interface is connected with the communication interface of described video decoding chip.

The hardware circuit of described composite video translation interface is characterized in that: the model of described video decoding chip is ADV7181B, and described single-chip microcomputer model is P89LPC935FDH.

Major function of the present utility model is to have realized the vision signal of pal mode of input is changed.Interface circuit uses the ADV7181B chip that decoding video signal is handled, and decoded signal is ITU_R656 standard 16 bit data signals.

The pal mode vision signal constitutes extremely complicated, comprising picture signal, line synchronizing signal, horizontal blanking signal, field sync signal, field blanking signal, leading Eq pulse and post-equalizing pulse etc.ADV7181B can detect the simulated television baseband complex signal with the pal mode of transformation standard automatically, exports 16 composite video data, supports the input of 6 road analog video signals.ADV7181B realizes easy control by the I2C bus, can export row, field sync signal simultaneously, uses the P89LPC935FDH single-chip microcomputer to carry out the I2C configuration.

In stereo display, show that in real time key is to solve the decoding problem of two-way composite video signal, ADV7181B is mainly bearing the task that the video data of simulating camera is decoded, and the CVBS analog signal of Phase Alternation Line system is changed into the YCrCb digital signal.The interface of the used liquid crystal display screen of stereo display is a digital interface, so need not carry out the D/A conversion again, can directly put screen from the digital signal that ADV7181B comes out.

Description of drawings

Fig. 1 is the utility model theory diagram.

Fig. 2 carries out I for single-chip microcomputer ²The circuit theory diagrams of C configuration.

Fig. 3 is an analog video signal decoding circuit schematic diagram.

Embodiment

As shown in Figure 1.The hardware circuit of composite video translation interface, include fpga chip, fpga chip is circumscribed with crystal oscillating circuit, power switch circuit, liquid crystal display screen, also includes video decoding chip and single-chip microcomputer, the model of video decoding chip is ADV7181B, and the single-chip microcomputer model is P89LPC935FDH.The Data Input Interface of video decoding chip is connected with the communication of outer video signal source, and the data output interface of video decoding chip is connected the I of single-chip microcomputer with the Data Input Interface communication of FPGA ²C interface is connected with the communication interface of video decoding chip.

ADV7181B provides an I2C interface, can be used for linking to each other with main control chip, carries out read-write operation with the register to its inside, thus the operating state of control ADV7181B.But through the decoded vision signal of ADV7181B, must keep correct sequential corresponding relation, could completely inerrably recover original video image.The sequential of ADV7181B output comprises signals such as capable field synchronization, row field blanking, line frequency field frequency and an identification.ADV7181B inside has 240 control registers, can set various functions with real ADV7181B by disposing these control registers.The function of ADV7181B is to gather the analog video signal of pal mode among the design, and carries out the A/D conversion with the clock frequency of 27MHz, with export 8 bit wides, form is the digital signal of YCbCr4:2:2.Under this required, as long as 21 registers of ADV7181B are configured, remaining register was the later default value of system reset.The address and the configuration data of these 21 registers are as shown in table 1.

The register parameters allocation list of table 1:ADV7181B.

Register address

?31h

32h

33h

34h

35h

36h

37h

The parameter that is provided with

?1Ah

81h

84h

00h

00h

7Dh

A1h

Register address

?E5h

E6h

E7h

0Eh

15h

17h

1Dh

The parameter that is provided with

?41h

84h

06h

80h

00h

41h

40h

Register address

?0Fh

3Ah

3Dh

3Fh

50h

C3h

C4h

The parameter that is provided with

?40h

16h

C3h

E4h

04h

05h

80h

As shown in Figure 2.Though FPGA also has the ability of configuration I2C program, uses very loaded down with trivial details.Here we use the P89LPC935FDH single-chip microcomputer that ADV7181B is carried out the I2C configuration.

For the analog signals such as CVBS of input, through behind the ADV7181B, output be YCrCb signal and HS, the VS signal, these are exactly the digital video signal that needs, and have also just solved the problem of digital video source.It should be noted that/the RESET signal also is very important, and low level will restart ADV7181B, and different with the CVBS signal is that this signal is provided by the user.

The ADV7181B input signal is the CVBS analog signal, output be COMDATA, HS, VS, Field signal.

The COMDATA signal is the YCrCb signal that meets ITU-R656, and the signal of COMDATA is formed: EAV, SAV, BLANK, ACTIVE VIDEO.In 1440 useful signals, 720 brightness Y sampling words are arranged, blue difference Cb and red difference Cr still have 360 sampling words respectively; Y, Cr, Cb signal are the ratios with 4:2:2, intert and arrange, and this meets the YUV422 standard, and SAV can be used as and detect the sign that useful signal begins as the separation of blank signal and useful signal simultaneously.Horizontal blanking (data between EAV and the SAV) and vertical blanking are filled with 80/10 usually.In the CVBS signal of pal mode, each line data all is made up of 720 YUV signal, adds blank signal and EAV, SAV.

Analog video signal decoding circuit schematic diagram as shown in Figure 3, analog signal CVBS enters the ADV7181B chip from AIN6, this schematic diagram has realized that the CVBS signal is converted into correlated digital signals such as COMDATA, HS, VS, Field, can directly correspond to the digital interface of liquid crystal display screen, the image that energy display simulation video camera takes on the liquid crystal display screen.

Claims (2)

1. the hardware circuit of composite video translation interface, include fpga chip, described fpga chip is circumscribed with crystal oscillating circuit, power switch circuit, liquid crystal display screen, it is characterized in that: also include video decoding chip and single-chip microcomputer, the Data Input Interface of described video decoding chip is connected with the communication of outer video signal source, the data output interface of video decoding chip is connected the I of described single-chip microcomputer with the Data Input Interface communication of FPGA ²C interface is connected with the communication interface of described video decoding chip.

2. the hardware circuit of composite video translation interface according to claim 1 is characterized in that: the model of described video decoding chip is ADV7181B, and described single-chip microcomputer model is P89LPC935FDH.

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