CN201758122U - Chip circuit utilizing reasonable distribution of transverse pads and longitudinal pads - Google Patents
Chip circuit utilizing reasonable distribution of transverse pads and longitudinal pads Download PDFInfo
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- CN201758122U CN201758122U CN2010202819838U CN201020281983U CN201758122U CN 201758122 U CN201758122 U CN 201758122U CN 2010202819838 U CN2010202819838 U CN 2010202819838U CN 201020281983 U CN201020281983 U CN 201020281983U CN 201758122 U CN201758122 U CN 201758122U
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- storage array
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Abstract
The utility model provides a chip circuit utilizing the reasonable distribution of transverse pads and longitudinal pads. The chip circuit comprises a storage array and a peripheral circuit on one side of the storage array, wherein a convex part and a concave part are arranged on the storage array, and the peripheral circuit is electrically connected with the storage array. The chip circuit is characterized in that the transverse pads and the longitudinal pads are further included, wherein the transverse pads are arranged at the convex part of the storage array, while the longitudinal pads are arranged at the concave part of the storage array; and the transverse pads and the longitudinal pads are electrically connected with the storage array and the peripheral circuit. The utility model has the advantages that the combination of the transverse pads and the longitudinal pads exactly complements the convex part and the concave part, that is, the longitudinal pads fully utilize the area of the concave part, and the transverse pads are arranged at the convex part to reduce the whole layout area of a chip; and the chip circuit effectively avoids area waste and the decline of circuit performance, and shortens the wiring distance and time delay between the pads and the peripheral circuit, so as to increase the access speed of the chip.
Description
Technical field
The utility model relates to a kind of storage chip, is specifically related to a kind of chip circuit that utilizes horizontal pad and vertical pad rational deployment.
Background technology
At present, the largest portion that accounts for the memory chip layout area is a storage array.Memory array is well-regulated, also has irregular.For the situation of rule, whole array can be aligned to a rectangle.And for irregular situation, whole array can't be arranged in the rectangle of a rule, but an irregular shape.As shown in Figure 1, for will place a general layout design method of many pads in the prior art on irregular one side of storage array.Fig. 1 is not the schematic diagram of a complete chip layout, and has included only storage array, the pad on the irregular limit of storage array and peripheral circuit.Storage array 101 is irregular " 7 " font.Array below layout one row's pad 102, each pad has all used vertical pad 103 becomes possibility so that place more pad.
Its shortcoming is that because the scrambling of storage array 101 has been vacated the area shown in 105, this part area has just been wasted fully.If the partial circuit in the peripheral circuit 104 is split the also zone of layout to 105, incited somebody to action at interval a very big storage array zone so between this two parts circuit, cause communication and sequential variation between two parts circuit, influence chip performance.
The utility model content
The utility model provides a kind of chip circuit that utilizes horizontal pad and vertical pad rational deployment, to make full use of the excess area that brings owing to the storage array scrambling, the scaled down version area of pictural surface makes the access speed performance of chip increase to a certain extent on the basis that does not reduce other performances of chip simultaneously to reduce cost.
For achieving the above object, the utility model provides a kind of chip circuit that utilizes horizontal pad and vertical pad rational deployment, and this chip circuit comprises:
Storage array; This storage array is provided with some projections and some sunk parts;
Be arranged on above-mentioned storage array peripheral circuit on one side; This peripheral circuit is connected with the storage array circuit;
It is characterized in that this chip circuit also comprises the some horizontal pad of the protuberance office that is arranged on storage array; And,
Be arranged on some vertical pad of the depressed part office of storage array;
Above-mentioned horizontal pad and vertically pad respectively with above-mentioned storage array and peripheral circuit between circuit be connected.
The width of above-mentioned horizontal pad is greater than vertical pad; The height of this vertical pad is greater than horizontal pad.
The size shape of above-mentioned some horizontal pads and the projection of storage array are suitable.
The size shape of above-mentioned some vertical pads and the sunk part of storage array are suitable.
The utility model is a kind of to utilize horizontal pad to compare with prior art with the chip circuit of vertical pad rational deployment, its advantage is, the utility model is provided with some horizontal pads and vertical pad, laterally pad and vertically the combination of pad just in time reach complementary with the irregular limit projection and the sunk part of storage array, vertically pad has made full use of the area of the sunk part on the irregular limit of storage array; Projection on the irregular limit of storage array is provided with the height that horizontal pad has then reduced the entire chip domain, reduced the area of entire chip domain, reduced chip cost, simultaneously, owing to do not have vacant area of the prior art, so effectively prevented the waste of area or the decline of circuit performance.While, wiring distance from the pad to the peripheral circuit and time-delay were also shortened to some extent owing to the chip layout height reduces, thereby had promoted the access speed of chip.
Description of drawings
Fig. 1 is the circuit arrangement map of prior art chip circuit;
Fig. 2 utilizes the circuit arrangement map of a kind of embodiment of chip circuit of horizontal pad and vertical pad rational deployment for the utility model is a kind of;
Fig. 3 utilizes the circuit arrangement map of a kind of embodiment of chip circuit of horizontal pad and vertical pad rational deployment for the utility model is a kind of;
Fig. 4 utilizes the circuit arrangement map of a kind of embodiment of chip circuit of horizontal pad and vertical pad rational deployment for the utility model is a kind of.
Embodiment
Below in conjunction with description of drawings embodiment of the present utility model.
Each embodiment of circuit layout among Fig. 2, Fig. 3 and Fig. 4, do not represent the circuit devcie layout type of a complete chip, just a part wherein is used to highlight a kind of architectural feature of utilizing its circuit layout of chip circuit of horizontal pad and vertical pad rational deployment of the utility model.
As shown in Figure 2, the utility model provides a kind of chip circuit that utilizes horizontal pad and vertical pad rational deployment, and it comprises storage array 201, and is arranged on the peripheral circuit 204 on storage array 201 sides, some horizontal pads 203 and vertical pad 202.This storage array 201 is " 7 " font, and one bar limit is irregular limit, and this irregular limit is provided with a projection and a sunk part.Peripheral circuit 204 is pressed close to a straight flange setting of storage array 201, simultaneously, exists circuit to be connected between peripheral circuit 204 and the storage array 201.
Be provided with the horizontal pad 203 of several settings parallel to each other in the protuberance office on storage array 201 irregular limits, be provided with vertical pad 202 of some settings parallel to each other in the depressed part office on storage array 201 irregular limits, simultaneously, laterally a limit of pad 203 and vertical pad 202 all parallels with the limit of storage array 201.Laterally pad 203 and vertical pad 202 exist circuit to be connected respectively with between storage array 201 and the peripheral circuit 204, and the partial circuit of forming memory chip connects and device layout.
The transverse width of horizontal pad 203 is greater than vertical pad 202, and vertical height of vertical pad 202 is greater than described horizontal pad 203.The shape size of some horizontal pads 203 is suitable with the projection on storage array 201 irregular limits, and the sunk part on the size shape of some vertical pads 202 and storage array 201 irregular limits is suitable.Simultaneously because vertically pad 202 and laterally pad 203 length difference in height, filled up on the storage array 201 irregular limits poor between the projection and sunk part, after layout was finished, laterally pad 203 and vertical pad 202 remained on the same straight line with respect to the outside of storage array 201.
As shown in Figure 3, utilize the another kind of embodiment of the chip circuit of horizontal pad and vertical pad rational deployment for the utility model is a kind of.It comprises storage array 201, and is arranged on the peripheral circuit 204 on storage array 201 sides, some horizontal pads 203 and vertical pad 202.This storage array 201 is " protruding " font, and one bar limit is irregular limit, and a projection is arranged on the middle part on irregular limit, and two sunk parts are arranged on the both sides of projection.Peripheral circuit 204 is pressed close to a straight flange setting of storage array 201, simultaneously, exists circuit to be connected between peripheral circuit 204 and the storage array 201.
Be provided with the horizontal pad 203 of several settings parallel to each other in the protuberance office at middle part, storage array 201 irregular limit, be provided with vertical pad 202 of some settings parallel to each other in the depressed part office of both sides, storage array 201 irregular limit, simultaneously, laterally a limit of pad 203 and vertical pad 202 all parallels with the limit of storage array 201.Horizontal pad 203 and vertically exist circuit to be connected between pad 202 and storage array 201 and the peripheral circuit 204, the partial circuit connection and the device layout of formation memory chip.
The transverse width of horizontal pad 203 is greater than vertical pad 202, and vertical height of vertical pad 202 is greater than described horizontal pad 203.The shape size of some horizontal pads 203 is suitable with the projection on storage array 201 irregular limits, and the sunk part on the size shape of some vertical pads 202 and storage array 201 irregular limits is suitable.Simultaneously because vertically pad 202 and laterally pad 203 length difference in height, filled up on the storage array 201 irregular limits poor between the projection and sunk part, after layout was finished, laterally pad 203 and vertical pad 202 remained on the same straight line with respect to the outside of storage array 201.
As shown in Figure 4, utilize the another kind of embodiment of the chip circuit of horizontal pad and vertical pad rational deployment for the utility model is a kind of.It comprises storage array 201, and is arranged on the peripheral circuit 204 on storage array 201 sides, some horizontal pads 203 and vertical pad 202.This storage array 201 is " recessed " font, and one bar limit is irregular limit, and a sunk part is arranged on the middle part on irregular limit, and two projections are separately positioned on the both sides of irregular limit sunk part.Peripheral circuit 204 is pressed close to a straight flange setting of storage array 201, simultaneously, exists circuit to be connected between peripheral circuit 204 and the storage array 201.
Be provided with the horizontal pad 203 of several settings parallel to each other in the protuberance office of both sides, storage array 201 irregular limit, be provided with vertical pad 202 of some settings parallel to each other in the depressed part office at middle part, storage array 201 irregular limit, simultaneously, laterally a limit of pad 203 and vertical pad 202 all parallels with the limit of storage array 201.Horizontal pad 203 and vertically exist circuit to be connected between pad 202 and storage array 201 and the peripheral circuit 204, the partial circuit connection and the device layout of formation memory chip.
The transverse width of horizontal pad 203 is greater than vertical pad 202, and vertical height of vertical pad 202 is greater than described horizontal pad 203.The shape size of some horizontal pads 203 is suitable with the projection on storage array 201 irregular limits, and the sunk part on the size shape of some vertical pads 202 and storage array 201 irregular limits is suitable.Simultaneously because vertically pad 202 and laterally pad 203 length difference in height, filled up on the storage array 201 irregular limits poor between the projection and sunk part, after layout was finished, laterally pad 203 and vertical pad 202 remained on the same straight line with respect to the outside of storage array 201.
The utility model adopts vertical pad 202 to fill up the area of the sunk part on storage array 201 irregular limits, made full use of the area of the sunk part on storage array 201 irregular limits, projection on storage array 201 irregular limits is provided with horizontal pad 203 simultaneously, then reduced the height of entire chip domain, remedy the sunk part on storage array 201 irregular limits and the difference in height between the projection, can again not take the domain space more.On the prior art basis, more efficient use the domain space of the irregular memory chip of array, reduced chip cost thereby reduced chip area; This layout type has effectively prevented the decline of the chip performance that the fractionation circuit causes in addition; Owing to reduced chip height, shortened peripheral circuit 204 and made the access speed of chip make moderate progress simultaneously to the wiring distance between horizontal pad 203 and the vertical pad 202.
Although content of the present utility model has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to restriction of the present utility model.After those skilled in the art have read foregoing, for multiple modification of the present utility model with to substitute all will be conspicuous.Therefore, protection range of the present utility model should be limited to the appended claims.
Claims (4)
1. one kind is utilized the horizontal pad and the vertical chip circuit of pad rational deployment, and this chip circuit comprises:
Storage array (201); Described storage array (201) is provided with some projections and some sunk parts;
Be arranged on described storage array (201) peripheral circuit (204) on one side; Described peripheral circuit (204) is connected with storage array (201) circuit;
It is characterized in that this chip circuit also comprises the some horizontal pad (203) of the protuberance office that is arranged on described storage array (201); And,
Be arranged on some vertical pad (202) of the depressed part office of described storage array (201);
Described horizontal pad (203) is connected with peripheral circuit (204) circuit with described storage array (201) respectively with vertical pad (202).
2. a kind of chip circuit that utilizes horizontal pad and vertical pad rational deployment as claimed in claim 1 is characterized in that the width of described horizontal pad (203) is greater than described vertical pad (202); The height of described vertical pad (202) is greater than described horizontal pad (203).
3. a kind of chip circuit that utilizes horizontal pad and vertical pad rational deployment as claimed in claim 1 is characterized in that the projection of the size shape of described some horizontal pads (203) and described storage array (201) is suitable.
4. a kind of chip circuit that utilizes horizontal pad and vertical pad rational deployment as claimed in claim 1 is characterized in that the sunk part of the size shape of described some vertical pads (202) and described storage array (201) is suitable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202819838U CN201758122U (en) | 2010-08-05 | 2010-08-05 | Chip circuit utilizing reasonable distribution of transverse pads and longitudinal pads |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202819838U CN201758122U (en) | 2010-08-05 | 2010-08-05 | Chip circuit utilizing reasonable distribution of transverse pads and longitudinal pads |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201758122U true CN201758122U (en) | 2011-03-09 |
Family
ID=43645412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010202819838U Expired - Lifetime CN201758122U (en) | 2010-08-05 | 2010-08-05 | Chip circuit utilizing reasonable distribution of transverse pads and longitudinal pads |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201758122U (en) |
-
2010
- 2010-08-05 CN CN2010202819838U patent/CN201758122U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: SHANGHAI FUDAN MICROELECTRONICS GROUP COMPANY LIMI Free format text: FORMER NAME: FUDAN MICROELECTRONICS CO., LTD., SHANGHAI |
|
| CP01 | Change in the name or title of a patent holder |
Address after: 200433, building 4, Fudan Science Park, No. 127 Guotai Road, Shanghai, Yangpu District Patentee after: Shanghai Fudan Microelectronic Group Co., Ltd. Address before: 200433, building 4, Fudan Science Park, No. 127 Guotai Road, Shanghai, Yangpu District Patentee before: Fudan Microelectronics Co., Ltd., Shanghai |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20110309 |