CN201733292U - Signal processing system and digital receiver - Google Patents
Signal processing system and digital receiver Download PDFInfo
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- CN201733292U CN201733292U CN 201020259818 CN201020259818U CN201733292U CN 201733292 U CN201733292 U CN 201733292U CN 201020259818 CN201020259818 CN 201020259818 CN 201020259818 U CN201020259818 U CN 201020259818U CN 201733292 U CN201733292 U CN 201733292U
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Abstract
The utility model is applied to the technical field of signal processing, providing a signal processing system and a digital receiver. The system comprises a DSP chip and an FPGA chip, wherein the DSP chip is taken as a main processor and is used for the target detection and the constant false alarm rate, and the FPGA chip is connected with the DSP chip, is taken as a co-processor of the DSP chip, and is used for the digital down conversion and the pulse compression. The signal processing system and the digital receiver can complete the computation with more conditional jumps and proper data stream such as the target detection and the constant false alarm rate by the DSP chip which is taken as the main processor of the signal processing system and complete the computation with single algorithm and higher computation speed such as the digital down conversion and the pulse compression by the FPGA chip which is taken as the co-processor of the DSP chip, and can effectively use the advantages of the DSP chip and the FPGA chip, thereby being capable of effectively improving the data transmission quantity and the computation speed. Furthermore, the signal processing system and the digital receiver have the characteristics of flexible framework, good programmability, strong expandability, high reliability and the like, and are good in performance.
Description
Technical field
The utility model belongs to the signal processing technology field, relates in particular to a kind of signal processing system and digital receiver.
Background technology
At present, signal processing technology expands to each application rapidly, and is more and more higher to the performance index requirement of signal processing system.Wherein the implementation handled of real time digital signal has multiplely, for different applications, the scope of application and index request, can select different processor systems for use.Treatment system commonly used has three kinds: Digital Signal Processing (DSP, Digital Signal Processing), application-specific integrated circuit (ASIC) (ASIC, Application-Specific Intergrated Circuits), field programmable gate array (FPGA, Field Programmable Gate Array).
Wherein, finish signal processing by single Digital Signal Processing (DSP) tangible deficiency is arranged, be that mainly volume of transmitted data is restricted, and arithmetic speed is slow, though adopt parallel processing technique can improve the arithmetic speed of Digital Signal Processing (DSP) system, but parallel processing makes data transmission rate improve greatly, the data-bus width that DSP itself is fixing and the signal integrity of high speed data transfer make the realization of parallel processing become very complicated, and the huge decrease in efficiency of system becomes the bottleneck of System Signal Processing.
In sum, finish signal processing by single Digital Signal Processing (DSP) in the prior art, volume of transmitted data is restricted, and arithmetic speed is slow.
The utility model content
The purpose of this utility model is to provide a kind of signal processing system, is intended to solve in the prior art common single excessively Digital Signal Processing (DSP) and finishes signal processing, and volume of transmitted data is restricted, and the slow problem of arithmetic speed.
The utility model is achieved in that a kind of signal processing system, and described system comprises:
As dsp chip primary processor, that be used to detect target and constant false alarm rate;
Be connected with described dsp chip, as the coprocessor of described dsp chip, be used for the fpga chip of Digital Down Convert and pulse compression.
Further, described system also comprises:
Be connected with described FPGA, be used for the analog signal conversion of input is become the analog to digital converter of digital signal.
Further again, described dsp chip specifically comprises:
Module of target detection is used to detect target;
The constant false alarm rate detection module is used to detect constant false alarm rate.
Further, described module of target detection comprises:
The moving-target detecting unit is used to detect moving-target.
Further, described fpga chip comprises:
Be used to produce the digital oscillator of digital sine burst and digital cosine burst;
Second digital multiplier of first digital multiplier of the digital cosine burst that digital signal that is used for the output of mixing analog to digital converter that is connected with digital oscillator and digital oscillator produce and the digital sine burst of digital signal that is used for the output of mixing analog to digital converter and digital oscillator generation;
Respectively the low pass filter that is connected successively with first digital multiplier and second digital multiplier, be used to adjust low pass filter output amplitude gain control module and be used for the pulse compression module of pulse compression;
Described dsp chip is provided with the DSP control interface of the pulse pressure parameter of the gain parameter of parameter, gain control module of the frequency that is used to control described digital oscillator, low pass filter and described pulse compression module.
The utility model embodiment also provides a kind of digital receiver, and described digital receiver is equipped with signal processing system, and described signal processing system comprises:
As dsp chip primary processor, that be used to detect target and constant false alarm rate;
Be connected with described dsp chip, as the coprocessor of described dsp chip, be used for the fpga chip of Digital Down Convert and pulse compression.
Further, described signal processing system also comprises:
Be connected with described FPGA, be used for the analog signal conversion of input is become the analog to digital converter of digital signal.
Further again, described dsp chip specifically comprises:
Module of target detection is used to detect target;
The constant false alarm rate detection module is used to detect constant false alarm rate.
Further, described module of target detection comprises:
The moving-target detecting unit is used to detect moving-target.
Further, described fpga chip comprises:
Be used to produce the digital oscillator of digital sine burst and digital cosine burst;
Second digital multiplier of first digital multiplier of the digital cosine burst that digital signal that is used for the output of mixing analog to digital converter that is connected with digital oscillator and digital oscillator produce and the digital sine burst of digital signal that is used for the output of mixing analog to digital converter and digital oscillator generation;
Respectively the low pass filter that is connected successively with first digital multiplier and second digital multiplier, be used to adjust low pass filter output amplitude gain control module and be used for the pulse compression module of pulse compression;
Described dsp chip is provided with the DSP control interface of the pulse pressure parameter of the gain parameter of parameter, gain control module of the frequency that is used to control described digital oscillator, low pass filter and described pulse compression module.
The utility model compared with prior art, beneficial effect is: by the dsp chip as the primary processor of signal processing system, finish and detect target and this computing that redirect of class condition is more, data flow is moderate of constant false alarm rate, by finishing Digital Down Convert as the fpga chip of the coprocessor of described dsp chip and the single arithmetic speed of this class algorithm of pulse compression is had relatively high expectations, effectively utilize the advantage of dsp chip and fpga chip, thereby can effectively improve volume of transmitted data and arithmetic speed.
And have that framework is flexible, programmability good, extensibility reaches characteristics such as reliability height by force, possess good performance.
Description of drawings
Fig. 1 is the module frame chart of the signal processing system that provides of the utility model embodiment;
Fig. 2 is the module frame chart of the signal processing system that provides of another embodiment of the utility model;
Fig. 3 is the module frame chart of the fpga chip that provides of the utility model embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer,, the utility model is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
In the embodiment of the invention, by dsp chip as the primary processor of signal processing system, finish and detect target and this computing that redirect of class condition is more, data flow is moderate of constant false alarm rate, by finishing Digital Down Convert as the fpga chip of the coprocessor of described dsp chip and the single arithmetic speed of this class algorithm of pulse compression is had relatively high expectations, effectively utilize the advantage of dsp chip and fpga chip, thereby can effectively improve volume of transmitted data and arithmetic speed.
And have that framework is flexible, programmability good, extensibility reaches characteristics such as reliability height by force, possess good performance.
A kind of signal processing system, described system comprises:
As dsp chip primary processor, that be used to detect target and constant false alarm rate;
Be connected with described dsp chip, as the coprocessor of described dsp chip, be used for the fpga chip of Digital Down Convert and pulse compression.
A kind of digital receiver, described digital receiver is equipped with signal processing system, and described signal processing system comprises:
As dsp chip primary processor, that be used to detect target and constant false alarm rate;
Be connected with described dsp chip, as the coprocessor of described dsp chip, be used for the fpga chip of Digital Down Convert and pulse compression.
Below in conjunction with specific embodiment realization of the present utility model is described in detail:
Embodiment one:
See also Fig. 1, a kind of signal processing system that the utility model embodiment provides comprises:
As dsp chip 1 primary processor, that be used to detect target and constant false alarm rate;
1 that be connected with described dsp chip, as the coprocessor of described dsp chip 1, be used for the fpga chip 2 of Digital Down Convert and pulse compression.
In embodiment of the present utility model, by dsp chip as the primary processor of signal processing system, finish and detect target and this computing that redirect of class condition is more, data flow is moderate of constant false alarm rate, by finishing Digital Down Convert as the fpga chip of the coprocessor of described dsp chip and the single arithmetic speed of this class algorithm of pulse compression is had relatively high expectations, effectively utilize the advantage of dsp chip and fpga chip, thereby can effectively improve volume of transmitted data and arithmetic speed.
And have that framework is flexible, programmability good, extensibility reaches characteristics such as reliability height by force, possess good performance.
Embodiment two:
See also Fig. 2, a kind of signal processing system that the utility model embodiment provides also comprises:
Be connected with described FPGA, be used for the analog signal conversion of input is become the analog to digital converter (ADC) 3 of digital signal.
In embodiment of the present utility model, described dsp chip 1 is provided with the external interface 4 that is used to connect external equipment.
In embodiment of the present utility model, described fpga chip 2 is provided with the RS422 interface 5 that is used to connect external equipment output.
Give external equipment by RS422 interface 5 exportable difference serial signals.
Embodiment three:
In embodiment of the present utility model, described dsp chip 1 specifically comprises:
Module of target detection is used to detect target;
Constant false alarm rate detection module (CFAR) is used to detect constant false alarm rate.
Described module of target detection comprises:
Moving-target detecting unit (MTD) is used to detect moving-target.
Embodiment four:
See also Fig. 3, in embodiment of the present utility model, described fpga chip 2 specifically comprises:
First digital multiplier 22 that is connected with digital oscillator 21 and second digital multiplier 26;
Low pass filter (FIR) 23, gain control module 24, the pulse compression module 25 that is connected successively with first digital multiplier 22 and second digital multiplier 26 respectively;
Described dsp chip 1 is provided with the DSP control interface 11 of the pulse pressure parameter of the gain parameter of parameter, gain control module 24 of the frequency that is used to control described digital oscillator 21, low pass filter 23 and described pulse compression module 25.
In embodiment of the present utility model, described digital oscillator 21, multiplication module 22 and 26, low pass filter 23 constitute the Digital Down Convert unit, are used to carry out Digital Down Convert.
In embodiment of the present utility model, the frequency configuration signal input pin of described fpga chip 2 is connected with the frequency configuration signal output pin of dsp chip 1, and described dsp chip 1 sends to digital oscillator 21 by the pin that is connected with the frequency configuration signal.
In embodiment of the present utility model, the output of digital oscillator module and multiplication module 22,26 input be connected.Described digital oscillator 21 is used to produce digital sine burst and digital cosine burst.The frequency of oscillation of digital oscillator 21 is controlled by frequency word.
In embodiment of the present utility model, first multiplier 22 is used for the digital signal of mixing analog to digital converter 3 outputs and the digital cosine burst that digital oscillator 21 produces.
In embodiment of the present utility model, the filter parameter signalization input pin of fpga chip 2 is connected with the filter parameter signalization output pin of dsp chip 1, and described dsp chip 1 sends to low pass filter 23 by the pin that is connected with the filter parameter signalization.
In embodiment of the present utility model, the bandwidth of the filter of low pass filter blocks 23 depends on signal bandwidth.The output data rate F0=Fs/D of filter.D is that extraction yield equals 2,4,8,16,32,64.Fs is input data transmission rate (being equal to signal sampling rate).
In embodiment of the present utility model, the gain of fpga chip 2 is provided with input pin and with the gain of dsp chip 1 output pin is set and is connected, and described dsp chip 1 sends to gain control module 24 by the pin that is connected with gain set.
Further, gain control module 24 specifically is used for adjusting by per step 0.03dB the output amplitude of low pass filter 23.
In embodiment of the present utility model, the pulse pressure parameter of fpga chip 2 is provided with input pin and with the pulse pressure parameter of dsp chip 1 output pin is set and is connected, and described dsp chip 1 sends to pulse compression module 25 by the pin that is connected with pulse pressure parameter signalization.
In embodiment of the present utility model, pulse compression is undertaken by time domain pulse pressure (convolution) way, and the convolution exponent number can be provided with.
In embodiment of the present utility model, pulse compression module 25 is connected with the input pin of dsp chip by I road output pin, the Q road output pin of FPGA, is used for the two-way orthogonal signalling of transmission pulse compression module 25 outputs.
In embodiment of the present utility model, following register is arranged in the fpga chip 2 and need preset: 1. 2. 3. 4. 5. pulse pressure convolution coefficient (signal waveform parameter) of pulse pressure (adopting the time domain pulse pressure) exponent number of gain control parameter of extraction yield of the frequency word of NCO.All register adopts DSP memory mapped mode to preset.Functional module that fpga chip 2 is all and register add and constitute preprocessor together.
Embodiment five:
The utility model embodiment also provides a kind of digital receiver, and described receiver is equipped with above-mentioned signal processing system.
Signal processing system of the present utility model and digital receiver, by dsp chip as the primary processor of signal processing system, finish and detect target and this computing that redirect of class condition is more, data flow is moderate of constant false alarm rate, by finishing Digital Down Convert as the fpga chip of the coprocessor of described dsp chip and the single arithmetic speed of this class algorithm of pulse compression is had relatively high expectations, effectively utilize the advantage of dsp chip and fpga chip, thereby can effectively improve volume of transmitted data and arithmetic speed.
And have that framework is flexible, programmability good, extensibility reaches characteristics such as reliability height by force, possess good performance.
The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.
Claims (10)
1. a signal processing system is characterized in that, described system comprises:
As dsp chip primary processor, that be used to detect target and constant false alarm rate;
Be connected with described dsp chip, as the coprocessor of described dsp chip, be used for the fpga chip of Digital Down Convert and pulse compression.
2. signal processing system as claimed in claim 1 is characterized in that, described system also comprises:
Be connected with described FPGA, be used for the analog signal conversion of input is become the analog to digital converter of digital signal.
3. signal processing system as claimed in claim 1 is characterized in that, described dsp chip specifically comprises:
Module of target detection is used to detect target;
The constant false alarm rate detection module is used to detect constant false alarm rate.
4. signal processing system as claimed in claim 3 is characterized in that, described module of target detection comprises:
The moving-target detecting unit is used to detect moving-target.
5. signal processing system as claimed in claim 2 is characterized in that, described fpga chip comprises:
Be used to produce the digital oscillator of digital sine burst and digital cosine burst;
Second digital multiplier of first digital multiplier of the digital cosine burst that digital signal that is used for the output of mixing analog to digital converter that is connected with digital oscillator and digital oscillator produce and the digital sine burst of digital signal that is used for the output of mixing analog to digital converter and digital oscillator generation;
Respectively the low pass filter that is connected successively with first digital multiplier and second digital multiplier, be used to adjust low pass filter output amplitude gain control module and be used for the pulse compression module of pulse compression;
Described dsp chip is provided with the DSP control interface of the pulse pressure parameter of the gain parameter of parameter, gain control module of the frequency that is used to control described digital oscillator, low pass filter and described pulse compression module.
6. a digital receiver is characterized in that, described digital receiver is equipped with signal processing system, and described signal processing system comprises:
As dsp chip primary processor, that be used to detect target and constant false alarm rate;
Be connected with described dsp chip, as the coprocessor of described dsp chip, be used for the fpga chip of Digital Down Convert and pulse compression.
7. digital receiver as claimed in claim 6 is characterized in that, described signal processing system also comprises:
Be connected with described FPGA, be used for the analog signal conversion of input is become the analog to digital converter of digital signal.
8. digital receiver as claimed in claim 6 is characterized in that, described dsp chip specifically comprises:
Module of target detection is used to detect target;
The constant false alarm rate detection module is used to detect constant false alarm rate.
9. digital receiver as claimed in claim 8 is characterized in that, described module of target detection comprises:
The moving-target detecting unit is used to detect moving-target.
10. digital receiver as claimed in claim 7 is characterized in that, described fpga chip comprises:
Be used to produce the digital oscillator of digital sine burst and digital cosine burst;
Second digital multiplier of first digital multiplier of the digital cosine burst that digital signal that is used for the output of mixing analog to digital converter that is connected with digital oscillator and digital oscillator produce and the digital sine burst of digital signal that is used for the output of mixing analog to digital converter and digital oscillator generation;
Respectively the low pass filter that is connected successively with first digital multiplier and second digital multiplier, be used to adjust low pass filter output amplitude gain control module and be used for the pulse compression module of pulse compression;
Described dsp chip is provided with the DSP control interface of the pulse pressure parameter of the gain parameter of parameter, gain control module of the frequency that is used to control described digital oscillator, low pass filter and described pulse compression module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 201020259818 CN201733292U (en) | 2010-07-14 | 2010-07-14 | Signal processing system and digital receiver |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201020259818 CN201733292U (en) | 2010-07-14 | 2010-07-14 | Signal processing system and digital receiver |
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| CN201733292U true CN201733292U (en) | 2011-02-02 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107688168A (en) * | 2016-08-03 | 2018-02-13 | 南京理工大学 | A kind of unknown signaling detecting system of spectral aliasing |
| CN110289849A (en) * | 2013-09-20 | 2019-09-27 | 阿尔特拉公司 | Mixed architecture for signal processing |
| EP3598645A3 (en) * | 2013-09-20 | 2020-04-01 | Altera Corporation | Hybrid architecture for signal processing |
-
2010
- 2010-07-14 CN CN 201020259818 patent/CN201733292U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110289849A (en) * | 2013-09-20 | 2019-09-27 | 阿尔特拉公司 | Mixed architecture for signal processing |
| EP3598645A3 (en) * | 2013-09-20 | 2020-04-01 | Altera Corporation | Hybrid architecture for signal processing |
| CN110289849B (en) * | 2013-09-20 | 2023-08-11 | 阿尔特拉公司 | Hybrid architecture for signal processing |
| CN107688168A (en) * | 2016-08-03 | 2018-02-13 | 南京理工大学 | A kind of unknown signaling detecting system of spectral aliasing |
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Granted publication date: 20110202 Termination date: 20120714 |