CN201673907U - Integrated structure of photosensitive chip and processing chip - Google Patents
Integrated structure of photosensitive chip and processing chip Download PDFInfo
- Publication number
- CN201673907U CN201673907U CN2010201979863U CN201020197986U CN201673907U CN 201673907 U CN201673907 U CN 201673907U CN 2010201979863 U CN2010201979863 U CN 2010201979863U CN 201020197986 U CN201020197986 U CN 201020197986U CN 201673907 U CN201673907 U CN 201673907U
- Authority
- CN
- China
- Prior art keywords
- chip
- substrate
- connecting circuit
- face
- heat dissipating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
The utility model relates to an integrated structure of a photosensitive chip and a processing chip, which comprises a base plate, a connecting circuit board, a photosensitive chip and a microprocessor chip, wherein the photosensitive chip and the microprocessor chip are respectively and electrically connected with the upper side and the lower side of the connecting circuit board; and the connecting circuit board is encapsulated in the base plate; and the base plate, the connecting circuit board, the photosensitive chip and the microprocessor chip are connected to form a whole module. The photosensitive chip and a microprocessor are integrally encapsulated without being separately encapsulated, so that the use is convenient, and the encapsulation cost of the chip is reduced.
Description
Technical field
The utility model relates to a kind of integrated morphology of chip, is meant the integrated morphology that a kind of sensitive chip and microprocessor chip are packaged together especially.
Background technology
As everyone knows, along with the very general life that has entered into people of the various photographic goods of the progress of society, wherein, traditional old-fashioned apparatus for making a video recording mainly is an image-forming principle of utilizing convex lens, the light of subject emission or reflection by camera lens imaging on the focal plane, is come document image by the chemical change of the photosensitive material silver bromide on the film.
The access mode of the machine photochemistry principle of taking with traditional old-fashioned apparatus for making a video recording is different, and what digital photography equipment of today adopted is the digitlization memory module.Sensitive chip and digital signal processing chip have all been adopted in the camera of digital vedio recording equipment by the ISO semi-conducting material manufacturing.Digital camera sensitive chip when work can be transformed into electric charge with the light that captures, convert electric charge to digital signal by analog to digital converter again, by digital signal processing chip the digital picture signal parameter is optimized processing then, be stored at last in the built-in hard disk or flash memory disk of camera, can pass through the display display image simultaneously.The color rendition of captured scenery and Color Range no longer rely on the quality of film, photosensitivity is also no longer fixed because of film, so the shooting effect of digital vedio recording equipment is better, and can see captured picture effect immediately, also can select to preserve or deletion, not worry wasting resource.
Sensitive chip and process chip become the core component of digital photography equipment with its outstanding function for above-mentioned digital photography equipment, and connected mode between sensitive chip and the process chip and set-up mode have often determined the quality of whole digital photography equipment.
Its inner sensitive chip and process chip all are separate settings with regard to the digital photography equipment that occurs on the market now, in concrete production all is independently to be arranged on the pcb board sensitive chip and process chip respectively, and sensitive chip is encapsulation separately, and process chip also is to encapsulate separately.This structural design mode many technical problems can occur in concrete practice, so at first need respectively occupy certain space because both are two kinds of chips that encapsulate separately, make that the circuit board section volume of digital vedio recording equipment is bigger; Secondly, so thereby because being the more processing step supports that need of encapsulation separately, both make the processing method complexity in concrete production, and this is the major defect for conventional art.
Summary of the invention
The utility model provides the integrated morphology of a kind of sensitive chip and process chip, substrate, connecting circuit plate, sensitive chip and microprocessor chip are packaged together in the utility model, the chip that utilizes the technical solution of the utility model to produce is easy to use, need not separately encapsulation separately, reduced the Chip Packaging cost, and this is to be main purpose of the present utility model.
The technical scheme that the utility model adopted is: the integrated morphology of sensitive chip and process chip, it comprises substrate, connecting circuit plate, sensitive chip and microprocessor chip, this sensitive chip and this microprocessor chip are to be connected electrically in up and down both sides of this connecting circuit plate respectively, and, this connecting circuit plate is encapsulated in this substrate, makes this substrate, this connecting circuit plate, this sensitive chip and this microprocessor chip be connected to form an integral module.
Aforesaid this substrate has end face, bottom surface and side, and wherein, this side is connected between this end face and this bottom surface, and this end face is arranged with out a cavity downwards certainly.
Be attached with the metallic conduction heat dissipating layer on this end face of this substrate, this bottom surface and this side, be attached with the tusche layer on this metallic conduction heat dissipating layer, by forming some end faces contact on this end face that is isolated in this substrate of this tusche layer, on this bottom surface of this substrate, form some bottom contact, do this end face contact and some this bottom contact and encircle respectively on this end face and this bottom surface that is located at this substrate.
This connecting circuit plate has upper surface and lower surface, wherein, this upper surface is provided with the sensitive chip contact, this lower surface is provided with the process chip contact and substrate connects electric shock, this sensitive chip is arranged on this upper surface of this connecting circuit plate, and be electrically connected with this sensitive chip contact of this upper surface by signal connecting line, this microprocessor chip is arranged on this lower surface of this connecting circuit plate, and is electrically connected with this process chip contact of this lower surface by signal connecting line.
This connecting circuit plate connection is arranged on this end face of this substrate, this substrate connection of this connecting circuit plate is connected electrically on this end face contact of this substrate, this moment, this microprocessor chip is arranged in this cavity of this substrate, this heat dissipating layer in this cavity is positioned at the below of this microprocessor chip, be provided with hot transfer layer between this heat dissipating layer and this microprocessor chip, also be covered with top cover on this substrate, this top cover is made by well-illuminated material.
Aforesaid this metallic conduction heat dissipating layer is made by metallic copper, is set with heat dissipating layer in this cavity of this substrate, and this heat dissipating layer is made by metallic copper.
Aforesaid this hot transfer layer comprises silicon gel part and black glue part, and wherein, this silicon gel part is connected between this heat dissipating layer and this microprocessor chip, is located at around this microprocessor chip and should black glue partly encircle.
The beneficial effects of the utility model are: the integrated morphology of this sensitive chip of the present utility model and process chip is arranged in concrete the use to be used as the light sensing control module in the digital photography equipment, when the utility model is arranged in the digital photography equipment, also this light signal is converted to the signal of telecommunication by this sensitive chip sensing external optical signal, then by this connecting circuit plate this signal of telecommunication is transferred in this microprocessor chip and handle, last control signal is after treatment outwards transmitted by the contact of this substrate.
As mentioned above, because this sensitive chip of the present utility model and this microprocessor chip are to be connected electrically in up and down both sides of this connecting circuit plate respectively, and this connecting circuit plate by overall package in this substrate, can be by simple package together by structural design of the present utility model with this sensitive chip and this microprocessor chip, independently module use of conduct in concrete production, thereby can simplify this sensitive chip greatly and promote production efficiency with the technology that is connected of this microprocessor chip, compared with prior art, the integrated encapsulation of sensitive chip of the present utility model and microprocessor, easy to use, need not separately encapsulation separately, reduced the Chip Packaging cost.
Description of drawings
Fig. 1 is a cross-sectional view of the present utility model;
Fig. 2 is a decomposing schematic representation of the present utility model;
Fig. 3 is the generalized section of substrate of the present utility model;
Fig. 4 is the vertical view of substrate of the present utility model;
Fig. 5 is the upward view of substrate of the present utility model;
Signal when Fig. 6 is work of the present utility model transmits schematic diagram.
Embodiment
Shown in Fig. 1 to 6, the integrated morphology of sensitive chip and process chip, it comprises substrate 10, connecting circuit plate 20, sensitive chip 30 and microprocessor chip 40.
Shown in Fig. 1 to 2, wherein, this sensitive chip 30 and this microprocessor chip 40 are to be connected electrically in this connecting circuit plate respectively about in the of 20 both sides, and, this connecting circuit plate 20 is encapsulated in this substrate 10, makes this substrate 10, this connecting circuit plate 20, this sensitive chip 30 and this microprocessor chip 40 be connected to form an integral module.
The integrated morphology of this sensitive chip of the present utility model and process chip is arranged in concrete the use in the digital photography equipment as the light sensing control module and uses, and the relatively more typical product of this digital photography equipment is digital camera, digital gamma camera and makes a video recording first-class.
When the utility model is arranged in the digital photography equipment, also this light signal is converted to the signal of telecommunication by these sensitive chip 30 sensing external optical signals, then by this connecting circuit plate 20 this signal of telecommunication is transferred in this microprocessor chip 40 and handle, last control signal is after treatment outwards transmitted by the contact of this substrate 10.
As mentioned above, because this sensitive chip 30 of the present utility model and this microprocessor chip 40 are to be connected electrically in this connecting circuit plate respectively about in the of 20 both sides, and this connecting circuit plate 20 by overall package in this substrate 10, can be by simple package together by structural design of the present utility model with this sensitive chip 30 and this microprocessor chip 40, in concrete production,, promote production efficiency with the technology that is connected of this microprocessor chip 40 thereby can simplify this sensitive chip 30 greatly as independently module use.
Shown in Fig. 1 to 5, this substrate 10 has end face 11, bottom surface 12 and side 13, and wherein, this side 13 is connected between this end face 11 and this bottom surface 12, and this end face 11 is arranged with out a cavity 14 downwards certainly.
Be attached with metallic conduction heat dissipating layer 15 on this end face 11 of this substrate 10, this bottom surface 12 and this side 13.
This metallic conduction heat dissipating layer 15 is made by metallic copper.
Be attached with tusche layer 16 on this metallic conduction heat dissipating layer 15.
By forming some end faces contact 111 on this end face 11 that is isolated in this substrate 10 of this tusche layer 16, on this bottom surface 12 of this substrate 10, form some bottom contact 121.
Some these end face contacts 111 and some this bottom contact 121 are encircled respectively on this end face 11 and this bottom surface 12 that is located at this substrate 10.
Be set with heat dissipating layer 141 in this cavity 14 of this substrate 10, this heat dissipating layer 141 is made by metallic copper.
This connecting circuit plate 20 has upper surface 21 and lower surface 22, and wherein, this upper surface 21 is provided with sensitive chip contact 211, and this lower surface 22 is provided with process chip contact 221 and substrate connects electric shock.
This sensitive chip 30 is arranged on this upper surface 21 of this connecting circuit plate 20, and is electrically connected with this sensitive chip contact 211 of this upper surface 21 by signal connecting line L.
This microprocessor chip 40 is arranged on this lower surface 22 of this connecting circuit plate 20, and is electrically connected with this process chip contact 221 of this lower surface 22 by signal connecting line L.
These connecting circuit plate 20 connections are arranged on this end face 11 of this substrate 10, and this substrate connection of this connecting circuit plate 20 is connected electrically on this end face contact 111 of this substrate 10, and this moment, this microprocessor chip 40 is arranged in this cavity 14 of this substrate 10.
This heat dissipating layer 141 in this cavity 14 is positioned at the below of this microprocessor chip 40.
Between this heat dissipating layer 141 and this microprocessor chip 40, be provided with hot transfer layer 60.
This hot transfer layer 60 comprises silicon gel part 61 and black glue part 62, and wherein, this silicon gel part 61 is connected between this heat dissipating layer 141 and this microprocessor chip 40.
Be located at the effect that this microprocessor chip 40 reaches protection this signal connecting line L and heat transmission all around and should deceive glue part 62 rings.
Also be covered with top cover 70 on this substrate 10, this top cover 70 is made by well-illuminated material and is made things convenient for these sensitive chip 30 sensitization to play the effect of security protection simultaneously.
Shown in arrow among Fig. 6, the utility model at first also is converted to the signal of telecommunication with this light signal by these sensitive chip 30 sensing external optical signals in work, this signal of telecommunication is passed in this microprocessor chip 40 by this signal connecting line L and handles, and then this substrate by this connecting circuit plate 20 of control signal after treatment connects and gets an electric shock and this end face contact 111 of this substrate 10 is passed on this substrate 10 last this bottom contact 121 by this substrate 10 and outwards transmits.
This heat dissipating layer 141 in hot transfer layer 60, this cavity 14 and this metallic conduction heat dissipating layer 15 carry out chip cooling and make integral product possess good heat dissipation characteristics the utility model by this in work.
Claims (4)
1. the integrated morphology of sensitive chip and process chip, it comprises substrate, connecting circuit plate, sensitive chip and microprocessor chip, it is characterized in that: this sensitive chip and this microprocessor chip are to be connected electrically in up and down both sides of this connecting circuit plate respectively, and, this connecting circuit plate is encapsulated in this substrate, makes this substrate, this connecting circuit plate, this sensitive chip and this microprocessor chip be connected to form an integral module.
2. the integrated morphology of sensitive chip as claimed in claim 1 and process chip is characterized in that: this substrate has end face, bottom surface and side, and wherein, this side is connected between this end face and this bottom surface, and this end face is arranged with out a cavity downwards certainly,
Be attached with the metallic conduction heat dissipating layer on this end face of this substrate, this bottom surface and this side, be attached with the tusche layer on this metallic conduction heat dissipating layer, by forming some end faces contact on this end face that is isolated in this substrate of this tusche layer, on this bottom surface of this substrate, form some bottom contact, doing this end face contact and some this bottom contact encircles respectively on this end face and this bottom surface that is located at this substrate
This connecting circuit board has upper surface and lower surface; Wherein, Be provided with the sensitive chip contact on this upper surface; Be provided with process chip contact and substrate on this lower surface and connect electric shock; This sensitive chip is arranged on this upper surface of this connecting circuit board; And be electrically connected with this sensitive chip contact of this upper surface by signal connecting line; This microprocessor chip is arranged on this lower surface of this connecting circuit board; And be electrically connected with this process chip contact of this lower surface by signal connecting line
This connecting circuit plate connection is arranged on this end face of this substrate, this substrate connection of this connecting circuit plate is connected electrically on this end face contact of this substrate, this moment, this microprocessor chip is arranged in this cavity of this substrate, this heat dissipating layer in this cavity is positioned at the below of this microprocessor chip, be provided with hot transfer layer between this heat dissipating layer and this microprocessor chip, also be covered with top cover on this substrate, this top cover is made by well-illuminated material.
3. the integrated morphology of sensitive chip as claimed in claim 2 and process chip is characterized in that: this metallic conduction heat dissipating layer is made by metallic copper, is set with heat dissipating layer in this cavity of this substrate, and this heat dissipating layer is made by metallic copper.
4. the integrated morphology of sensitive chip as claimed in claim 3 and process chip, it is characterized in that: this hot transfer layer comprises silicon gel part and black glue part, wherein, this silicon gel part is connected between this heat dissipating layer and this microprocessor chip, is located at around this microprocessor chip and should black glue partly encircle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201979863U CN201673907U (en) | 2010-05-19 | 2010-05-19 | Integrated structure of photosensitive chip and processing chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201979863U CN201673907U (en) | 2010-05-19 | 2010-05-19 | Integrated structure of photosensitive chip and processing chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201673907U true CN201673907U (en) | 2010-12-15 |
Family
ID=43331315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010201979863U Expired - Fee Related CN201673907U (en) | 2010-05-19 | 2010-05-19 | Integrated structure of photosensitive chip and processing chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201673907U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11297210B2 (en) | 2018-01-30 | 2022-04-05 | Vivo Mobile Communication Co., Ltd. | Camera module, method for assembling camera module, and mobile terminal |
-
2010
- 2010-05-19 CN CN2010201979863U patent/CN201673907U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11297210B2 (en) | 2018-01-30 | 2022-04-05 | Vivo Mobile Communication Co., Ltd. | Camera module, method for assembling camera module, and mobile terminal |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20130077257A1 (en) | Electronic device and image sensor heat dissipation structure | |
| US20190364184A1 (en) | Camera module, circuit board assembly and manufacturing method thereof, and electronic device with camera module | |
| CN205248278U (en) | Image sensor encapsulation | |
| CN208754401U (en) | A kind of heat radiating type camera module | |
| US20110285890A1 (en) | Camera module | |
| US11153471B2 (en) | Through-hole electrode substrate | |
| TW200830870A (en) | Package module and electronic assembly for image sensor device and fabrication method thereof | |
| TW201110676A (en) | Electronic assembly for an image sensing device, wafer level lens set | |
| CN202120913U (en) | Thin-type image capturing module | |
| US20090256222A1 (en) | Packaging method of image sensing device | |
| TW201103128A (en) | Image sensor and the method for package of the same | |
| CN103681702A (en) | Methods and apparatus for sensor module | |
| CN109274876A (en) | Photosensory assembly and its packaging method, lens module, electronic equipment | |
| KR101300316B1 (en) | Camera Module | |
| CN210629641U (en) | Photosensitive assembly, camera module and electronic equipment | |
| CN101197359A (en) | Image sensor module | |
| CN206865596U (en) | Camera module and its photosensory assembly | |
| TW200950505A (en) | Image sensor structure and integrated lens module thereof | |
| JP2016033963A (en) | Semiconductor package ane manufacturing method of the same, and image pickup device | |
| JP2009049973A (en) | Cmos image sensor package | |
| CN201311932Y (en) | High temperature resistant integrated molding videography group | |
| US20190244998A1 (en) | Imaging devices, camera modules, and fabrication methods thereof | |
| CN201673907U (en) | Integrated structure of photosensitive chip and processing chip | |
| JP2015041971A (en) | Image sensor and imaging device | |
| JP2018125319A (en) | Module, method of manufacturing the same, and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101215 Termination date: 20120519 |