CN201667660U - Modularized IEEE1588 clock transparent transmission structure of Ethernet switch - Google Patents
Modularized IEEE1588 clock transparent transmission structure of Ethernet switch Download PDFInfo
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- CN201667660U CN201667660U CN2010201250603U CN201020125060U CN201667660U CN 201667660 U CN201667660 U CN 201667660U CN 2010201250603 U CN2010201250603 U CN 2010201250603U CN 201020125060 U CN201020125060 U CN 201020125060U CN 201667660 U CN201667660 U CN 201667660U
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Abstract
The utility model discloses a modularized IEEE1588 clock transparent transmission structure of an Ethernet switch, which is characterized in that a transparent transmission module is formed by Ethernet Phy with IEEE1588 hardware and common Ethernet Phy which are connected through an FPGA to realize the peer-to-peer transparent transmission of IEEE1588v1 and v2.0 messages. The IEEE1588 clock transparent transmission module can be externally arranged outside a common switch and can also be arranged in the common switch to ensure that the common switch has the IEEE1588 clock peer-to-peer transparent transmission function. When the IEEE1588 clock transparent transmission module is applied, common Ethernet Phy ports are connected with the network port of the common switch and the Ethernet Phy ports with the IEEE1588 hardware are connected with equipment ports supporting an IEEE1588 clock or are used for the cascade connection between switches. A module capable of realizing IEEE1588 cascade connection at least requires more than three pairs of Ethernet Phy, wherein at least three Ethernet Phy are provided with IEEE1588 hardware and generally four pairs of Phy are used for realizing IEEE1588 cascade connection.
Description
Technical field
The utility model is Ethernet switch modular i EEE 1588 clock transparent transmission structures, and its technical field relates to the accurate regularly application enhancements of agreement of IEEE1588, is a kind of clock transparent transmission modular structure.This clock transparent transmission module can be connected with common Ethernet switch, makes general switch possess accurate timing function.
Background technology
It is AgilentLaboratories (Agilent laboratory) exploitation that IEEE 1588 (network TT﹠C system accurate clock synchronization protocol) begins.Be adopted as international standard by IEEE at last, its front page obtains the IEEE approval in November, 2002.
IEEE 1588 agreements mainly are to make the precision clock in the distributed network keep synchronous with other clocks, defined a kind of Precision Time Protocol PTP (Precision TimeProtocol) thus, it is synchronous to be used for adopting clock in transducer, actuator and the other-end equipment of distributed bus system of multicasting technologies to carry out the submicrosecond level to standard ethernet or other.
IEEE 1588 design initial are to be used for measuring and control system, are generalized to association areas such as telecommunication and electric power system gradually.
IEEE 1588 is divided into two kinds with the clock in the whole network, ordinary clock OC (OrdinaryClock) and boundary clock BC (Boundary Clock), the clock that has only a PTP communication port is an ordinary clock, the clock that an above PTP communication port is arranged is a boundary clock, and each PTP port provides independently PTP communication.Wherein, boundary clock is used on the relatively poor network equipment of certainty such as switch and the router usually.Can be divided into master clock to clock again from the correspondence and from clock, any in theory clock can both be realized master clock and from the function of clock, but in a PTP communication subnet master clock can only be arranged.
Optimum clock in the whole system is highest clock Grandmaster Clock, and best stability, accuracy, certainty etc. are arranged.Automatically select the interior master clock of each subnet by best master clock algorithm (BestMaster Clock).Each system has only a former master clock, and has only a master clock in each subnet, keeps synchronously from clock and master clock.
2003 ODVA (open network supply of equipment ACSA) plan in fact the time joining day synchronous service among the universal industrial protocol CIP (Common Industrial Protocol) that control uses, be referred to as CIP Sync, as real-time extension to Ethernet/IP-CIP.
EPSG (Ethernet Powerlink standard consortium) is used in IEEE1588 in a plurality of real-time section synchronous communication of leap in third edition basis, and distributed application is provided.Only need standard ethernet hardware, do not need special ASIC s, but must real time communication be separated with non-realtime traffic by bridge or router.
Siemens Company also is devoted to revise its PROFInet V3 with IEEE 1588, all needs special ASIC s.
The drawback of existing IEEE1588 boundary clock: add the IEEE1588 boundary clock in the Ethernet switch the inside, generally need the special ASIC chip, need to revise original switch system structure, need embed chip at MAC layer and PHY interlayer, original product all needs to revise, and has increased development cost.
Summary of the invention
The purpose of this utility model is in order to overcome the deficiency of above-mentioned existing IEEE 1588 boundary clock technology, this transparent transmission module is coupled together by FPGA by the Ethernet Phy and the common Ethernet Phy of band IEEE 1588 hardware, realizes the end-to-end transparent transmission of IEEE 1588v1 and v2.0 message.This IEEE1588 clock transparent transmission module can be external in the general switch outside, also can be placed on the general switch the inside, makes the end-to-end transparent transmission function of general switch band IEEE1588 clock.This IEEE1588 clock transparent transmission module is when using, and common Ethernet Phy mouth connects the general switch network interface, and the Ethernet Phy mouth of band IEEE 1588 hardware connects the device port of supporting IEEE 1588 clocks, perhaps is used for the cascade between the switch.The module of realization IEEE1588 cascade needs the Ethernet Phy more than 3 couples at least, wherein has the Ethernet Phy of 3 band IEEE 1588 hardware at least, and 4 couples of Phy have been adopted in common realization.
The purpose of this utility model reaches by the following technical programs:
As shown in Figure 1, the phy interface that connects band IEEE 1588 agreements of 4 (or more) by the FPGA that supports the PTP agreement by MII or GMII mouth, corresponding 4 common phy interfaces of connection again, the phy interface clock of the IEEE 1588 that FPGA is synchronously all, revising the chronometer time of PTP input and output stabs, realize the transparent transmission of IEEE 1588 clock protocols, guarantee accurate timing accuracy.
As shown in Figure 4, the phy interface of two band IEEE 1588 agreements of this module can be used for cascade, group of switches is become chain or other topological structures, still guarantee the precision transmission of IEEE 1588 agreements, thereby IEEE 1588 precision interval clocks of whole network are linked together, and do not need to change original switch architecture.
Advantage of the present utility model: because this modular construction has adopted transparent transmission mode, switch does not originally need to revise, and just can cross increase IEEE 1588 agreements, has reduced development cost, has increased application flexibility.。
Description of drawings
Fig. 1 is Ethernet switch modular i EEE 1588 clock transparent transmission structure charts, and mainly PHY, the common Ethernet PHY by FPGA that supports the PTP agreement and band IEEE 1588 agreements forms, and couples together by MII mouth or GMII mouth between them.
Fig. 2 is the sketch of Ethernet switch modular i EEE 1588 clock transparent transmission structures, and wherein the PHY of IEEE 1588 agreements is with in 1,2,3,4 expressions, the common Ethernet PHY of 5,6,7,8 expressions.
Fig. 3 represents the connected mode of IEEE 1588 clock transparent transmission modules and general switch, links to each other with general switch by 5,6,7,8 mouthfuls.1,2,3,4 mouthfuls can link to each other with the equipment of band IEEE 1588 agreements, or carry out the cascade of clock transparent transmission module.
Fig. 4 has represented the cascade of 3 clock transparent transmission modules, and each module is together in series by 3,4 mouthfuls, guarantees the IEEE 1588 accurate regularly transmission of agreement, realizes the cascade teletransmission of precision interval clock.
Embodiment
Describe the embodiment of the utility model Ethernet switch modular i EEE1588 clock transparent transmission structure in detail below in conjunction with accompanying drawing.
With the ethernet device that modular i EEE 1588 clock transparent transmission structures link to each other, can be two layers switch, also can be three-tier switch, can be 100 m switch, also can be gigabit switch.
With reference to figure 1 as can be known, support the FPGA of PTP agreement and PHY, the common Ethernet PHY of band IEEE 1588 agreements, communicate by MII mouth or GMII mouth between them, realize the synchronous all the time of 1588 mouthfuls of each IEEE, and the PTP frame of input and output is write real-time chronometer time stab by FPGA.
With reference to figure 3 as can be known, when IEEE 1588 clock transparent transmission modules are connected with general switch, link to each other with general switch by 5,6,7,8 mouthfuls.1,2,3,4 mouthfuls can link to each other with the equipment of band IEEE1588 agreement, or carry out the cascade of clock transparent transmission module.
With reference to figure 4 as can be known, cascade when many clock transparent transmission modules, each module is together in series by 2 IEEE 1588PHY mouths, and the subscriber equipment of remaining IEEE1588PHY mouth connecting band IEEE 1588 clocks is realized the cascade teletransmission of subscriber equipment IEEE 1588 precision interval clocks.
Claims (4)
1. Ethernet switch modular i EEE 1588 clock transparent transmission structures, it is characterized in that: the transparent transmission module is coupled together by FPGA by the Ethernet Phy and the common Ethernet Phy of band IEEE 1588 hardware, realizes the end-to-end transparent transmission of IEEE 1588v1 and v2.0 message.This IEEE1588 clock transparent transmission module is when using, and common Ethernet Phy mouth connects the general switch network interface, and the Ethernet Phy mouth of band IEEE 1588 hardware connects the device port of supporting the IEEE1588 clock, perhaps is used for the cascade between the switch.
2. Ethernet switch modular i EEE 1588 clock transparent transmission structures according to claim 1, its feature also is: this IEEE1588 clock transparent transmission module can be external in the general switch outside, also can be placed on the general switch the inside, make the end-to-end transparent transmission function of general switch band IEEE1588 clock.
3. Ethernet switch modular i EEE 1588 clock transparent transmission structures according to claim 1, its feature also is: the module of realization IEEE 1588 cascades needs the Ethernet Phy more than 3 couples at least, wherein have the Ethernet Phy of 3 band IEEE 1588 hardware at least, 4 couples of Phy have been adopted in common realization.
4. Ethernet switch modular i EEE 1588 clock transparent transmission structures according to claim 1, its feature also is: the Ethernet Phy mouth of this module can be 10M, 100M, 1000M speed, also can be light mouth or electricity mouth.
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102215078A (en) * | 2011-06-09 | 2011-10-12 | 国网电力科学研究院 | Method for realizing hardware timestamp based on FPGA (field programmable gate array) |
US9432330B2 (en) | 2013-05-29 | 2016-08-30 | Huawei Technologies Co., Ltd. | Data interaction method, apparatus, and system |
CN114362874A (en) * | 2022-03-21 | 2022-04-15 | 北京国科天迅科技有限公司 | Master clock equipment determining method and device, electronic equipment and storage medium |
-
2010
- 2010-03-03 CN CN2010201250603U patent/CN201667660U/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102215078A (en) * | 2011-06-09 | 2011-10-12 | 国网电力科学研究院 | Method for realizing hardware timestamp based on FPGA (field programmable gate array) |
US9432330B2 (en) | 2013-05-29 | 2016-08-30 | Huawei Technologies Co., Ltd. | Data interaction method, apparatus, and system |
CN114362874A (en) * | 2022-03-21 | 2022-04-15 | 北京国科天迅科技有限公司 | Master clock equipment determining method and device, electronic equipment and storage medium |
CN114362874B (en) * | 2022-03-21 | 2022-08-12 | 北京国科天迅科技有限公司 | Master clock equipment determining method and device, electronic equipment and storage medium |
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Granted publication date: 20101208 Termination date: 20150303 |
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