CN201655808U - Groove-type high-power MOS device - Google Patents
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- CN201655808U CN201655808U CN2010200032372U CN201020003237U CN201655808U CN 201655808 U CN201655808 U CN 201655808U CN 2010200032372 U CN2010200032372 U CN 2010200032372U CN 201020003237 U CN201020003237 U CN 201020003237U CN 201655808 U CN201655808 U CN 201655808U
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Abstract
The utility model relates to a groove-type high-power MOS device and a manufacturing method thereof. An overlooking plane of the groove-type high-power MOS device is provided with a cellular area positioned on a semiconductor substrate and a terminal protection structure. The cellular area is positioned in the center area of the semiconductor substrate. The terminal protection structure is positioned on the periphery of the cellular area. The cellular area adopts a groove structure. Cellulars in the cellular area are connected in parallel into a whole body by conductive polycrystalline silicons in the cellular groove. The terminal protection structure comprises a voltage dividing protection area positioned in the inner ring of the terminal protection structure and a cut-off protection area positioned in the outer ring of the terminal protection structure. The voltage resistance capability of the voltage dividing protection area is improved by arranging a main junction and at least one voltage dividing ring in the voltage dividing protection area. According to the voltage resistant requirement, the width of a field oxide above the voltage dividing ring can be regulated so as to conveniently regulate the distance between the voltage dividing rings and improve voltage resistance of the device. The utility model improves the voltage-resistant property of the device and reduce the manufacturing cost of the device.
Description
Technical field
The utility model relates to a kind of MOS device, especially a kind of groove type high-power MOS device.
Background technology
Power MOS (Metal Oxide Semiconductor) device generally includes cellular region and is positioned at the terminal protection structure of cellular region periphery; The cellular integrated level and the terminal protection structure of cellular region directly affect Devices Characteristics, as feature conducting resistance and voltage endurance capability.And under the prerequisite that does not influence device performance, reduce the processing cost that the photoetching number of plies of making the MOS device can directly reduce the MOS device.At present, power MOS (Metal Oxide Semiconductor) device commonly used need be through 7 layer photoetching manufacturings; When lithography layer was reduced to 5 layers, processing cost can save 29%.Chinese patent ZL200410074901.1 discloses " semiconductor device and manufacture method thereof "; in its disclosed terminal protection structure; utilize around the annular well region of cellular region and form the dividing potential drop protection zone, polysilicon gate is drawn to be positioned at above the semiconductor substrate and partly and is taken on field oxide.
Yet, in the structure shown in patent ZL200410074901.1 accompanying drawing 2,, promptly be close to second conductive type layer of outmost turns cellular and the PN junction that first conductive type epitaxial layer constitutes owing in the dividing potential drop protection zone, have only main knot; Device voltage is only shared by main knot in the dividing potential drop protection zone.Stride on field oxide and taken one section polycrystalline, when the drain electrode end making alive, described semiconductor structure has following problems:
1, since in the described dividing potential drop protection zone in main become a partner second conductive type layer of answering and the cellular region second conductive type layer be same manufacturings layer, the therefore master's concentration and degree of depth basically identical of interior second conductive type layer of concentration, the degree of depth and cellular region of second conductive type layer of answering of becoming a partner.If keep the described concentration and the degree of depth at the especially main knot fringe region of main knot, when drain electrode end adds forward voltage, can cause main knot edge electric field strength strong excessively so, reduce the device withstand voltage ability; If when main knot fringe region increases the concentration of well region and the degree of depth, though raising that can be to a certain degree is withstand voltage, need to increase at least photoetching and corresponding some processing steps could be realized, can increase manufacturing cost like this.
2, taking grid on field oxide draws polycrystalline and grid and draws between field oxide below the polycrystalline and constituted the polycrystalline field plate structure.When drain electrode end adds positive voltage (corresponding to N type MOS device), semiconductor substrate surface under the polycrystalline field plate can form the inversion layer with the semiconductor substrate conductivity type opposite, this inversion layer is consistent with main knot conduction type, and link to each other with main knot, form a surface leakage channel, increased the risk of surface leakage.
3, be positioned at above the substrate and part is taken grid on the field oxide and drawn that polysilicon need increase a photoetching and corresponding processing step could be realized, can increase the manufacturing cost of MOS device like this.
Summary of the invention
The purpose of this utility model is to overcome the deficiencies in the prior art, and a kind of groove type high-power MOS device is provided, and it has improved the device withstand voltage characteristic, has reduced the manufacturing cost of device.
The technical scheme that provides according to the utility model, described groove type high-power MOS device, on the top plan view of described MOS device, comprise the cellular region and the terminal protection structure that are positioned on the semiconductor substrate, described cellular region is positioned at the center of semiconductor substrate, and terminal protection structure is positioned at the periphery of cellular region; Described cellular region adopts groove structure, and cellular is by the conductive polycrystalline silicon in the cellular groove and unify in the cellular region; Described terminal protection structure comprises the dividing potential drop protection zone that is positioned at its inner ring and is positioned at the protection zone of ending of its outer ring; Its innovation is:
On the top plan view of described MOS device, described dividing potential drop protection zone comprises at least two circle field oxides, and described field oxide all is looped around the periphery of cellular region;
On the cross section of described MOS device, the dividing potential drop protection zone comprises main knot and at least one potential dividing ring; Described master becomes the cellular groove of contiguous dividing potential drop protection zone and second conductive type layer and the formed PN junction of first conductive type epitaxial layer between contiguous described cellular groove field oxide; Described potential dividing ring is the PN junction that forms between second conductive type layer between the opposite field oxide layer and first conductive type epitaxial layer; Described potential dividing ring is positioned at the outside of main knot; Described main first conductive type epitaxial layer isolation that utilizes field oxide and field oxide below between the potential dividing ring of tying with corresponding contiguous master of tying; Utilize first conductive type epitaxial layer of field oxide and field oxide below isolated between described adjacent potential dividing ring; It is isolated that corresponding vicinity is ended the second conduction type interlayer employing field oxide and first conductive type epitaxial layer below the field oxide of protection zone in second conductive type layer in the protection zone and the dividing potential drop protection zone; Corresponding second conductive type layer and first metal connects into equipotential in the described main knot;
Described first conductive type layer comprises first conductivity type substrate that is positioned at semiconductor substrate bottom and is positioned at first conductive type epitaxial layer above first conductivity type substrate, and the first conduction type injection region that is positioned at the first conductive type epitaxial layer top; Described second conductive type layer is positioned at the top of first conductive type epitaxial layer; The surface of described first conductivity type substrate is second interarea of semiconductor substrate, and the surface of first conductive type epitaxial layer is first interarea of semiconductor substrate; Described first metal is positioned at the cellular region top;
On the cross section of described MOS device, described dividing potential drop protection zone is corresponding to being provided with grid exit groove in the main knot; Described grid exit groove is positioned at second conductive type layer, and the degree of depth stretches into first conductive type epitaxial layer of second conductive type layer below; The superficial growth of described grid exit trench wall has the insulated gate oxide layer, is deposited with conductive polycrystalline silicon in above-mentioned grid exit groove; The notch of described grid exit groove is provided with second ohmic contact hole, and described grid exit groove and second ohmic contact hole top is provided with second metal, and the interior conductive polycrystalline silicon of described second metal and grid exit groove contacts; Described dividing potential drop protection zone covers by insulating medium layer corresponding to the outer remainder of second ohmic contact hole is set.
On the cross section of described MOS device, cellular region adopts groove structure, and described cellular groove is positioned at second conductive type layer, and the degree of depth stretches into first conductive type epitaxial layer of second conductive type layer below; The superficial growth of described cellular trench wall has the insulated gate oxide layer, is deposited with conductive polycrystalline silicon in growth has the cellular groove of insulated gate oxide layer; In the cellular region cellular by being positioned at the cellular groove conductive polycrystalline silicon and unify; Corresponding outer wall top is provided with the first conduction type injection region between the interior adjacent cellular groove of described cellular region, and the described first conduction type injection region contacts with cellular groove outer wall; The notch of described cellular groove is coated with insulating medium layer; The top of described cellular groove both sides is equipped with first ohmic contact hole, and described cellular groove and first ohmic contact hole top are deposited with first metal; Second conductive type layer in described first metal and the cellular region contacts, and second conductive type layer of cellular groove both sides is connected into equipotential.
On the cross section of described MOS device, describedly comprise second conductive type layer and be positioned at the first conduction type injection region on the second conductive type layer top by the protection zone; Described in the protection zone in second conductive type layer and interior second conductive type layer of cellular region, the dividing potential drop protection zone second conductive type layer be same manufacturing layer; Described ending in the protection zone is provided with the 3rd ohmic contact hole corresponding to top, the first conduction type injection region, in described the 3rd ohmic contact hole the 3rd metal is set, and described the 3rd metal contacts with the first conduction type injection region; Described by covering by insulating medium layer corresponding to the remainder that is provided with outside the 3rd ohmic contact hole in the protection zone.
On the cross section of described MOS device, the top of second conductive type layer is covered by insulating medium layer and field oxide in the described potential dividing ring, forms the potential dividing ring of floating.Described first conductivity type substrate is provided with drain electrode end.Described insulating medium layer is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
Described " first conduction type " and " second conduction type " are among both, and for N type metal-oxide-semiconductor field effect transistor, first conduction type refers to the N type, and second conduction type is the P type; For P type metal-oxide-semiconductor field effect transistor, first conduction type is just in time opposite with N type metal-oxide-semiconductor field effect transistor with the type of the second conduction type indication.
Advantage of the present utility model:
1, in the dividing potential drop protection zone, adopt the structure that comprises main knot and at least one potential dividing ring, improved the voltage endurance capability of MOS device and the reliability of device withstand voltage.
2, in the described dividing potential drop protection zone, adopt the structure that comprises main knot and at least one potential dividing ring, saved, reduced the manufacturing cost of device to increasing reticle and the corresponding processing step that the main knot edge second conductive type layer concentration and the degree of depth are provided with.
3, utilize and on the grid exit groove second metal is set and draws grid, saved polycrystalline reticle and concerned process steps, reduced manufacturing cost.
4, the utility model structure only needs 5 reticle and corresponding processing step, compares the MOS structure that needs 7 reticle, and manufacturing cost reduces about 29%.
Description of drawings
Fig. 1 is the vertical view of the utility model MOS device.
Fig. 2～Fig. 5 for the A-A of Fig. 1 to the concrete process implementing profile of analysing and observe, wherein:
Fig. 2 is the cutaway view after forming field oxide on first interarea.
Fig. 3 is formed on the cutaway view behind the formation groove structure in second conductive type layer.
Fig. 4 is the cutaway view after the formation first conduction type injection region structure.
The cutaway view of Fig. 5 behind deposit insulating medium layer on first interarea.
Cutaway view behind Fig. 6 deposit and the etching sheet metal.
Embodiment
The utility model is described in further detail below in conjunction with concrete drawings and Examples.
Show as Fig. 1～Fig. 6: with N type MOS device is example, and the utility model comprises cellular region 1, dividing potential drop protection zone 2, by protection zone 3, field oxide 4, N+ substrate 5, N type epitaxial loayer 6, P trap 7, N+ injection region 8, insulated gate oxide layer 9, conductive polycrystalline silicon 10, cellular groove 11, grid exit groove 12, insulating medium layer 13, first metal 14, second metal 15, the 3rd metal 16, drain electrode end 17, main knot 18, potential dividing ring 19, first ohmic contact hole 20, second ohmic contact hole 21, the 3rd ohmic contact hole 22 and photoresist 23.
Fig. 1 is the vertical view of described N type MOS device.As shown in Figure 1: in the center of described MOS device is cellular region 1, and the periphery of described cellular region 1 is a terminal protection structure, terminal protection structure comprise the dividing potential drop protection zone 2 that is positioned at its inner ring and be positioned at its outer ring by protection zone 3.Described cellular region 1 adopts groove structure, and cellular region 1 is by the conductive polycrystalline silicon 10 in the cellular groove 11 and unify.Described cellular region 1 links to each other by the conductive polycrystalline silicon in the groove 10 corresponding to the grid exit groove in the cellular groove 11 of outmost turns and the dividing potential drop protection zone 2 12.Grid exit in the described dividing potential drop protection zone 2 forms pectinate texture.Be provided with the field oxide 4 of four circles around cellular region 1 in the described dividing potential drop protection zone 2, described field oxide 4 is isolated the P trap in the dividing potential drop protection zone 27 with the N type epitaxial loayer 6 of field oxide below; Described vicinity by the N type epitaxial loayer 6 of the field oxide 4 of protection zone 3 and described field oxide 4 belows with dividing potential drop protection zone 2 with isolated by protection zone 3.
Fig. 6 is a structure cutaway view of the present utility model.As shown in Figure 6: on the cross section of N type MOS device, growth has N type epitaxial loayer 6 on the described N+ substrate 5; The surface of described N type epitaxial loayer 6 is as first interarea of semiconductor substrate, and N+ substrate 5 is as second interarea of semiconductor substrate.On the interface of described MOS device, cellular region 1 adopts groove structure, and described cellular groove 11 is positioned at P trap 7, and the degree of depth stretches in the N type epitaxial loayer 6 of P trap 7 belows.The growth of described cellular groove 11 inner wall surface has insulated gate oxide layer 9, thereafter, is deposited with conductive polycrystalline silicon 10 in the inner wall surface growth has the cellular groove 11 of insulated gate oxide layer 9; In the cellular region 1 cellular groove 11 by being positioned at cellular groove 11 conductive polycrystalline silicon 10 and unify; The notch of cellular groove 11 is coated with insulating medium layer 13, and the top of the both sides of cellular groove 11 all is provided with first ohmic contact hole 20.11 tops of described adjacent cellular groove are provided with N+ injection region 8, and described N+ injection region 8 contacts with the outer wall of cellular groove 11.Described cellular region 1 top is deposited with first metal, 14, the first metals 14 and fills first ohmic contact hole 20; P trap 7 in first metal 14 and the cellular region 1 contacts, and described first metal 14 connects into equipotential with the P trap 7 of cellular groove 11 both sides.Described N+ injection region 8 contacts with first metal 14, and first metal 14 connects into equipotential with N+ injection region 8 corresponding in the cellular region 1.
On the cross section of N type MOS device, described dividing potential drop protection zone 2 comprises main knot 18 and at least one potential dividing ring 19, and described potential dividing ring 19 is positioned at the outside of main knot 18, has shown the structure of three potential dividing rings 19 in the diagram of the present utility model.Described main knot 18 is isolated by the N type epitaxial loayer 6 of field oxide 4 and field oxide 4 belows with the potential dividing ring 19 of contiguous described main knot 18; The P trap 7 that the cellular groove 11 that described main knot 18 is contiguous dividing potential drop protection zone 2 in the cellular region 1 and the field oxide of contiguous described cellular groove 11 are 4 and the PN junction of 6 formation of N type epitaxial loayer.P trap 7 and N type epitaxial loayer 6 formed PN junctions that described potential dividing ring 19 is 4 of opposite field oxide layers.19 N type epitaxial loayers 6 by field oxide 4 and field oxide 4 belows of described adjacent potential dividing ring are isolated.Be provided with grid exit groove 12 in the described main knot 18, described grid exit groove 12 inner wall surface growth has insulated gate oxide layer 9, be deposited with conductive polycrystalline silicon 10 in growth has the grid exit groove 12 of insulated gate oxide layer 9, grid exit groove 12 is in parallel by conductive polycrystalline silicon in the groove 10 and cellular groove 11.The notch of described grid exit groove 12 is provided with second ohmic contact hole, 21, the second ohmic contact hole, 21 tops and is deposited with second metal 15, and described second metal 15 is used to form the gate terminal of MOS device.Corresponding to being set, second ohmic contact hole, 21 outer remainders cover in the described dividing potential drop protection zone 2 by insulating medium layer 4.P trap 7 tops in the described potential dividing ring 19 are covered by insulating medium layer 13 and field oxide 4, form potential dividing ring 19 structures of floating.When the potential dividing ring in the described dividing potential drop protection zone 2 19 was one, the horizontal range of the P trap 7 in protection zone 3 and 7 of the contiguous described P traps that ends protection zone 3 was greater than the thickness of N type epitaxial loayer 6.When the potential dividing ring 19 in the described dividing potential drop protection zone 2 during more than, the P trap 7 in protection zone 3 can suitably dwindle with the horizontal range of 7 of the contiguous described P traps that ends protection zone 3.For guaranteeing the safe in utilization of described MOS device; when contiguous potential dividing ring by protection zone 3 exhausts fully; the horizontal width of depletion layer when described vicinity exhausts greater than described potential dividing ring 19 fully by the width of the field oxide 4 of protection zone 3, and leave certain distance margin.
The width of described grid exit groove 12 is greater than the width of cellular groove 11, and grid exit groove 12 is same manufacturing layer with cellular groove 11, and grid exit groove 12 is identical with the degree of depth of cellular groove 11.Described dividing potential drop protection zone 2 is with isolated by field oxide 4 and the N type epitaxial loayer 6 of field oxide 4 belows of protection zone 3 by outmost turns, and the horizontal range of described P trap 7 in protection zone 3 and 19 of the contiguous potential dividing rings that ends protection zone 3 is greater than N type epitaxial loayer 6 thickness.
On the cross section of described MOS device, comprise P trap 7 and the N+ injection region 8 that is positioned at P trap 7 tops by protection zone 3; 8 tops, described N+ injection region are provided with the 3rd ohmic contact hole 22, and described the 3rd ohmic contact hole 22 tops are provided with the 3rd metal 16; Described the 3rd metal 16 contacts with N+ injection region 8.Described first metal 14, second metal 15 and the 3rd metal 16 are same manufacturing layer.Described cellular region 1, dividing potential drop protection zone 2 and the P trap 7 in protection zone 3 are same manufacturing layer, have the identical degree of depth and concentration.The described protection zone 3 of ending is covered by insulating medium layer 13 corresponding to the 3rd ohmic contact hole 22 outer remainders are set.
On the cross section of described MOS device, described N+ substrate 5 is provided with drain electrode end 17.
The structure of above-mentioned MOS device, realize by following processing step:
A, provide the first conductive type semiconductor substrate with two relative interareas, described two relative interareas comprise first interarea and second interarea; The bottom surface of described N+ substrate 5 is second interarea, and N type epitaxial loayer 6 is first interarea with N+ substrate 5 corresponding upper surfaces;
B, one deck field oxide 4 of on described first interarea, growing;
C, optionally shelter and etching field oxide 4 (ground floor photoetching), form the field oxides 4 of at least two circles around the semiconductor substrate center, described field oxide 4 is positioned at the outer ring of semiconductor substrate, as shown in Figure 2;
Described field oxide 4 corrosion can be selected corrosion of wet method isotropic or plasma anisotropic etching;
D, on above-mentioned first interarea, the deposit hard mask layer, described hard mask layer can adopt LPTEOS (plasma-enhanced tetraethyl orthosilicate), thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride, forms hard mask by photoetching and anisotropic etching thereafter;
E, optionally shelter and the etching hard mask layer, form the hard mask (second layer photoetching) of etching groove, and etching forms groove on first interarea, obtains cellular groove 11, grid exit groove 12 simultaneously; Described etching groove adopts plasma anisotropic etching, form the trenched side-wall (angle of trenched side-wall and semiconductor substrate is not less than 88 degree) of near vertical, gash depth need be considered the needs of component characteristic parameter, and described gash depth is generally 1 μ m～2 μ m, as shown in Figure 3;
F, in described trench wall superficial growth insulated gate oxide layer 9; Described insulated gate oxide layer 9 adopts the high-temperature furnace tube process growth;
G, in the growth of described inner wall surface has the groove of insulated gate oxide layer 9 deposit conductive polycrystalline silicon 10; Described conductive polycrystalline silicon 10 is boiler tube growth or chemical vapour deposition (CVD) heavy doping N type polysilicon;
H, etching are removed the conductive polycrystalline silicon 10 on first interarea, obtain conductive polycrystalline silicon 10 in the groove;
I, on first interarea, the autoregistration ion injects p type impurity, and forms the cellular region 1 P trap 7 corresponding with terminal protection structure by knot; Described injection p type impurity ion is generally the boron ion;
J, on described first interarea, utilize photoresist 23, carry out source region photoetching (the 3rd layer photoetching), and inject the N type foreign ion of high concentration, and by knot obtain being positioned at cellular region 1 with by 3 corresponding N+ injection regions 8, protection zone, as shown in Figure 4;
On the cross section of described MOS device, the N+ injection region 8 in the described cellular region 1 is distributed in the outer wall top of 11 correspondences of adjacent cellular groove, and described N+ injection region 8 contacts with cellular groove 11 outer walls; Described 10 distribution P traps, 7 tops, N+ injection region in protection zone 3; N+ injection region 8 is same manufacturing layer with N+ injection region 8 in protection zone 3 in the described cellular region 1, and its doping depth is identical with concentration;
K, on above-mentioned first interarea, deposit insulating medium layer 13, described dielectric 13 is USG, PSG or BPSG;
L, described dielectric laminar surface is carried out chemico-mechanical polishing, the insulating medium layer 13 that obtains having an even surface;
M, on the insulating medium layer that has an even surface, carry out hole photoetching (the 4th layer photoetching) and etching, obtain first ohmic contact hole 20, second ohmic contact hole 21 and the 3rd ohmic contact hole 22 simultaneously, as shown in Figure 5;
N, above described first interarea deposited metal, by optionally sheltering and etching sheet metal (layer 5 photoetching), form first metal 14, second metal 15 and the 3rd metal 16 simultaneously, as shown in Figure 6.
As shown in Figure 6: the working mechanism of the utility model MOS device is: be provided with grid exit groove 12 corresponding to main the knot in 18 in the described dividing potential drop protection zone 2; Described grid exit groove 12 is by the extension of outmost turns cellular groove 11 corresponding in the cellular region 1, be filled with conductive polycrystalline silicon 10 in the grid exit groove 11, the conductive polycrystalline silicons 10 of filling in the corresponding cellular groove 11 of described conductive polycrystalline silicon 10 and cellular region 1 link to each other.The grid exit groove 12 that described outmost turns cellular groove 11 extends constitutes pectinate texture, second ohmic contact hole 21 is set above the notch of described grid exit groove 12, by in the grid exit groove 12 and second ohmic contact hole 21, filling second metal 15, just the grid in the cellular region 1 can be drawn; Disclosed grid lead-out mode among the patent of the comparing ZL 200410074901.1, it is to form in grid exit groove 12 that grid of the present utility model is drawn, need on semiconductor substrate, not leave conductive polycrystalline silicon 12, therefore can save a polycrystalline reticle, provide cost savings.
Described dividing potential drop protection zone 2 comprises main knot 18 and at least one potential dividing ring 19, and described potential dividing ring 19 is around the center of cellular region 1; When MOS device normal bias, source ground, drain electrode end 17 adds forward bias, the main knot 18 anti-depletion layers that form partially.Because the concentration of the N type epitaxial loayer 6 of the main knot 18 of composition is much smaller than the concentration of P trap 7, so depletion layer is mainly expanded to N type epitaxial loayer 6 one sides.When the depletion layer expansion of horizontal direction touches the potential dividing ring 19 of close cellular region 1, majority carrier in the P trap 7 of described potential dividing ring 19 correspondences will flow into depletion layer, makes potential dividing ring 19 be become the electrical opposite electric polarity of P trap 7 majority carriers of band and potential dividing ring 19 by electric neutrality; The horizontal component of electric field that described potential dividing ring 19 produces is opposite with the horizontal component of electric field direction of former main knot depletion layer, thereby has played the purpose of sharing main junction voltage.In like manner, when outwards expansion of depletion region continuation, when touching the potential dividing ring 19 of outer ring, described potential dividing ring 19 plays identical effect, expand to outmost turns potential dividing ring 19 until depletion layer, the potential lines of described depletion layer closes at the field oxide 4 of the semiconductor substrate surface in outmost turns potential dividing ring 19 outsides.Because the direction bias voltage is weakened by potential dividing ring 19; therefore compare the accompanying drawing 2 disclosed dividing potential drop protection zones 2 of having only main knot 18 among the ZL200410074901.1; the utility model is in whole dividing potential drop protection zone 2; especially the electric field of outmost turns potential dividing ring 19 edges and semiconductor substrate surface intersection can be more average; avoid internal field strong excessively, caused the situation of premature breakdown to take place easily.And; the accompanying drawing 2 disclosed structures among the ZL200410074901.1 of comparing; need be by increasing the mode that the photoetching number of plies realizes increasing dividing potential drop protection zone 2 interior P trap 7 edge concentration and the degree of depth; P trap 7 diffuses to form simultaneously with cellular region 1 interior P trap 7 in the dividing potential drop of the present utility model protection zone 2; therefore save the photoetching number of plies, further reduced cost.
On the cross section of described MOS device, described dividing potential drop protection zone 2 comprises that main knot 18 and at least one potential dividing ring 19 constitute, and the quantity of potential dividing ring 19 is determined that by the actual withstand voltage demand of device withstand voltage high more, potential dividing ring quantity is many more; The distance that the distance that the potential dividing ring of described master's knot 18 and contiguous main knot 18 is 19 and adjacent two potential dividing rings are 19 need be determined by concrete requirement of withstand voltage and die area requirement, distance is too near, and the dividing potential drop deleterious is apart from too far away, the dividing potential drop effect also can be influenced, and can increase die area.Spacing between the potential dividing ring 19 mainly realizes by the width of regulating the field oxide 4 above it.The width of described outmost turns field oxide 4 is usually greater than field oxide 4 width of all the other inner rings, prevents that mainly depletion region touches when fully exhausting by protection zone 3 near the potential dividing ring 19 by protection zone 3, avoids break-through to take place.
The utility model utilizes first metal 14 and second metal 15 to draw the source terminal and the gate terminal of MOS device respectively, described second metal 15 links to each other with conductive polycrystalline silicon 10 in the grid exit groove 12 by grid exit groove 12 tops second ohmic contact hole 21, constituted the gate terminal of MOS device, easy to operate, reduced the use of polycrystalline plate, reduce the use of reticle, reduced the processing cost of MOS device.
Claims (6)
1. a groove type high-power MOS device on the top plan view of described MOS device, comprises the cellular region and the terminal protection structure that are positioned on the semiconductor substrate, and described cellular region is positioned at the center of semiconductor substrate, and terminal protection structure is positioned at the periphery of cellular region; Described cellular region adopts groove structure, and cellular is by the conductive polycrystalline silicon in the cellular groove and unify in the cellular region; Described terminal protection structure comprises the dividing potential drop protection zone that is positioned at its inner ring and is positioned at the protection zone of ending of its outer ring; It is characterized in that:
On the top plan view of described MOS device, described dividing potential drop protection zone comprises at least two circle field oxides, and described field oxide all is looped around the periphery of cellular region;
On the cross section of described MOS device, the dividing potential drop protection zone comprises main knot and at least one potential dividing ring; Described master becomes the cellular groove of contiguous dividing potential drop protection zone and second conductive type layer and the formed PN junction of first conductive type epitaxial layer between contiguous described cellular groove field oxide; Described potential dividing ring is the PN junction that forms between second conductive type layer between the opposite field oxide layer and first conductive type epitaxial layer; Described potential dividing ring is positioned at the outside of main knot; Described main first conductive type epitaxial layer isolation that utilizes field oxide and field oxide below between the potential dividing ring of tying with corresponding contiguous master of tying; Utilize first conductive type epitaxial layer of field oxide and field oxide below isolated between described adjacent potential dividing ring; It is isolated that corresponding vicinity is ended the second conduction type interlayer employing field oxide and first conductive type epitaxial layer below the field oxide of protection zone in second conductive type layer in the protection zone and the dividing potential drop protection zone; Corresponding second conductive type layer and first metal connects into equipotential in the described main knot;
Described first conductive type layer comprises first conductivity type substrate that is positioned at semiconductor substrate bottom and is positioned at first conductive type epitaxial layer above first conductivity type substrate, and the first conduction type injection region that is positioned at the first conductive type epitaxial layer top; Described second conductive type layer is positioned at the top of first conductive type epitaxial layer; The surface of described first conductivity type substrate is second interarea of semiconductor substrate, and the surface of first conductive type epitaxial layer is first interarea of semiconductor substrate; Described first metal is positioned at the cellular region top;
On the cross section of described MOS device, described dividing potential drop protection zone is corresponding to being provided with grid exit groove in the main knot; Described grid exit groove is positioned at second conductive type layer, and the degree of depth stretches into first conductive type epitaxial layer of second conductive type layer below; The superficial growth of described grid exit trench wall has the insulated gate oxide layer, is deposited with conductive polycrystalline silicon in above-mentioned grid exit groove; The notch of described grid exit groove is provided with second ohmic contact hole, and described grid exit groove and second ohmic contact hole top is provided with second metal, and the interior conductive polycrystalline silicon of described second metal and grid exit groove contacts; Described dividing potential drop protection zone covers by insulating medium layer corresponding to the outer remainder of second ohmic contact hole is set.
2. groove type high-power MOS device according to claim 1, it is characterized in that: on the cross section of described MOS device, cellular region adopts groove structure, and described cellular groove is positioned at second conductive type layer, and the degree of depth stretches into first conductive type epitaxial layer of second conductive type layer below; The superficial growth of described cellular trench wall has the insulated gate oxide layer, is deposited with conductive polycrystalline silicon in growth has the cellular groove of insulated gate oxide layer; In the cellular region cellular by being positioned at the cellular groove conductive polycrystalline silicon and unify; Corresponding outer wall top is provided with the first conduction type injection region between the interior adjacent cellular groove of described cellular region, and the described first conduction type injection region contacts with cellular groove outer wall; The notch of described cellular groove is coated with insulating medium layer; The top of described cellular groove both sides is equipped with first ohmic contact hole, and described cellular groove and first ohmic contact hole top are deposited with first metal; Second conductive type layer in described first metal and the cellular region contacts, and second conductive type layer of cellular groove both sides is connected into equipotential.
3. groove type high-power MOS device according to claim 1 is characterized in that: on the cross section of described MOS device, describedly comprise second conductive type layer and be positioned at the first conduction type injection region on the second conductive type layer top by the protection zone; Described in the protection zone in second conductive type layer and interior second conductive type layer of cellular region, the dividing potential drop protection zone second conductive type layer be same manufacturing layer; Described ending in the protection zone is provided with the 3rd ohmic contact hole corresponding to top, the first conduction type injection region, in described the 3rd ohmic contact hole the 3rd metal is set, and described the 3rd metal contacts with the first conduction type injection region; Described by covering by insulating medium layer corresponding to the remainder that is provided with outside the 3rd ohmic contact hole in the protection zone.
4. groove type high-power MOS device according to claim 1 is characterized in that: on the cross section of described MOS device, the top of second conductive type layer is covered by insulating medium layer and field oxide in the described potential dividing ring, forms the potential dividing ring of floating.
5. groove type high-power MOS device according to claim 1 is characterized in that: described first conductivity type substrate is provided with drain electrode end.
6. according to the described groove type high-power MOS device of one of claim 1 to 4, it is characterized in that: described insulating medium layer is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
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| CN2010200032372U CN201655808U (en) | 2010-01-15 | 2010-01-15 | Groove-type high-power MOS device |
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| CN2010200032372U CN201655808U (en) | 2010-01-15 | 2010-01-15 | Groove-type high-power MOS device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106571395A (en) * | 2016-10-31 | 2017-04-19 | 珠海格力电器股份有限公司 | Trench type metal-oxide semiconductor power device and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106571395A (en) * | 2016-10-31 | 2017-04-19 | 珠海格力电器股份有限公司 | Trench type metal-oxide semiconductor power device and manufacturing method thereof |
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