CN201654183U - Chip test signal distribution circuit and multiplex chip test system - Google Patents
Chip test signal distribution circuit and multiplex chip test system Download PDFInfo
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- CN201654183U CN201654183U CN2010201524162U CN201020152416U CN201654183U CN 201654183 U CN201654183 U CN 201654183U CN 2010201524162 U CN2010201524162 U CN 2010201524162U CN 201020152416 U CN201020152416 U CN 201020152416U CN 201654183 U CN201654183 U CN 201654183U
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- operational amplifier
- chip
- distributor circuit
- detection signal
- output terminal
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Abstract
The utility model discloses a chip test signal distribution circuit and a multiplex chip test system. The distribution circuit comprises a first operational amplifier and a plurality of second operational amplifiers; the positive input end of the first operational amplifier is connected with divider resistors and a first blocking capacitor, and the first operational amplifier receives chip test signals; the second operational amplifiers are connected in parallel, the positive input end of each second operational amplifier is connected to the output end of the first operational amplifier, the output end of each second operational amplifier is connected with a second blocking capacitor, and the second operational amplifiers output the chip test signals via the second blocking capacitors. The test system comprises at least one of an oscillograph, a logic analyzer, a FPGA for checking a chip to be tested and a reference multimedia device. The chip test signal distribution circuit and the multiplex chip test system can simultaneously carry out multiple tests on the chip, thus increasing the efficiency of chip tests and shortening the time of chip tests.
Description
Technical field
The utility model relates to signal circuit, more specifically, relates to a kind of distributor circuit of chip detection signal and the chip detecting system that multichannel detects.
Background technology
Along with development of integrated circuits, each technical field of society all can use semi-conductor chip, particularly in the equipment such as televisor, video disc player, all is integrated with multimedia process chip such as video or audio frequency.The equipment of integrated multimedia process chip is before dispatching from the factory, and the technician can carry out the detection of various aspects to the multimedia chip in the equipment, and passes through the processing procedure of FPGA proofing chip,
With the televisor is example, referring to Fig. 1, be used to verify the FPGA of Video processing, when the processing capacity of chip is verified, need and to connect relevant detection equipment by the test signal that inputs or outputs of FPGA, for example: the signal processing module that the output signal of video is connected various functions, to detect the whether correct deal with data of certain chip in this televisor and can further handle by connected signal processing module, or joint detection instrument, as oscillograph, the televisor that maybe input signal of this chip is connected simultaneously other televisor manufacturer, whether variant with the checking chip processing capacity result that FPGA was verified and other televisor manufacturer's televisor result.
At present above-mentioned testing process is to detect successively, as measured signal is connected oscillograph, after the detection waveform, connects signal processing module again, after the processing of detection chip is whether correct, does the detection of others again.Because measured signal has only one tunnel output, can not expand output interface, can only detect successively.
The utility model content
The utility model aims to provide a kind of distributor circuit of chip detection signal, has only one tunnel output to solve above-mentioned chip under test, can not expand the problem of output interface.
According to an aspect of the present utility model, a kind of distributor circuit of chip detection signal is provided, comprising: first operational amplifier, the positive input terminal of first operational amplifier connects the divider resistance and first partiting dc capacitor, receiving chip detection signal; A plurality of second operational amplifiers parallel with one another, the positive input terminal of each second operational amplifier is connected to the output terminal of first operational amplifier, the output terminal of each second operational amplifier is connected with second partiting dc capacitor respectively, via the second partiting dc capacitor pio chip detection signal.
Further, the output terminal of first operational amplifier and second operational amplifier feeds back respectively and is connected to its negative input end separately.
Another aspect of basic utility model, the chip detecting system that also provides a kind of multichannel to detect comprises above-mentioned distributor circuit, the positive input terminal of first operational amplifier of distributor circuit is connected to the FPGA that sends the chip detection signal; The output terminal of each second operational amplifier of distributor circuit is connected to checkout equipment respectively.
Further, checkout equipment comprises oscillograph, logic analyser, multimedia equipment and has in the processing module of resolving audio frequency, video data function at least one.
Further, multimedia equipment is televisor or video disc player.
According to another aspect of the present utility model, the chip detecting system that also provides a kind of multichannel to detect comprises above-mentioned distributor circuit, and the positive input terminal of first operational amplifier of distributor circuit connects the signal generator that sends the chip detection signal; The output terminal of each second operational amplifier of distributor circuit is connected to checkout equipment respectively.
Further, checkout equipment comprises the FPGA of oscillograph, logic analyser, checking chip under test and at least one in the benchmark multimedia equipment.
Further, the benchmark multimedia equipment is televisor or video disc player.
By the distributor circuit of chip detection signal of the present utility model, expanded the output interface of detection signal, can insert more checkout equipment; Detection system of the present utility model can insert a plurality of checkout equipments simultaneously by distributor circuit and detect, owing to realize chip is carried out multinomial detection simultaneously, has improved the efficient of detection chip, has shortened the time of detection chip.
Description of drawings
Accompanying drawing is used to provide further understanding of the present utility model, constitutes the application's a part, and illustrative examples of the present utility model and explanation thereof are used to explain the utility model, do not constitute improper qualification of the present utility model.In the accompanying drawings:
Signal transmission synoptic diagram when Fig. 1 shows detection chip;
Fig. 2 shows the synoptic diagram of first kind of detection system of the present utility model;
Fig. 3 shows the synoptic diagram of second kind of detection system of the present utility model;
Fig. 4 shows distributor circuit schematic diagram of the present utility model.
Embodiment
For clearly demonstrating scheme of the present utility model, provide preferred embodiment below and be described with reference to the accompanying drawings the utility model.
Referring to Fig. 2, Fig. 2 is first kind of detection system synoptic diagram of the present utility model, when detecting by FPGA, the chip detection signal of handling back output from FPGA produces multichannel output by distributor circuit, the fpga chip verification platform can connect multimedia equipment by distributor circuit, multimedia equipment can be televisor or video disc player etc., all can carry out multichannel output by distributor circuit, has wide range of applications.The output terminal of distributor circuit connects checkout equipments such as oscillograph, logic analyser, multimedia equipment and/or processing module respectively, and processing module is the parsing audio frequency of all kinds of different vendors or the processing module of video capability.Each checkout equipment can detect simultaneously, obtains each testing result, because the technology difference of the processing module of different vendor can verify whether the output result of the chip functions in the FPGA platform has versatility.
For different detections, this distributor circuit also can export detection signal to tested chip, as shown in Figure 3, Fig. 3 is the synoptic diagram of second kind of detection system of the present utility model, the detection signal that inputs to chip that comes automatic signal generator exports benchmark multimedia equipment and FPGA verification platform respectively to through distributor circuit, and FPGA is used for the checking of chip in the various multimedia equipments, multimedia equipment can be video disc player, televisor etc., has wide range of applications.If multimedia equipment is a televisor, whether then the benchmark multimedia equipment among Fig. 3 is the satisfactory benchmark televisor of another one performance or other manufacturer's a televisor, identical with the treatment effect of benchmark televisor with the treatment effect of verifying this fpga chip, the treatment effect with other manufacturer's televisor is identical.Because distributor circuit has multichannel output, can also connect checkout equipments such as oscillograph, logic analyser and/or processing module.
The distributor circuit of the utility model chips detection signal can select the computing of various ways such as four high guaily unit, six amplifiers to amplify chip, does not disturb mutually with consistance and each the road signal that satisfies output signal.Provide a kind of embodiment below, circuit among this embodiment adopts four high guaily unit, three forms of distributing, and be applied in the detection of handling interchange vision signal chip in the televisor, the schematic diagram of circuit structure can be referring to Fig. 4, because the chip detection signal of televisor is an AC signal, after so the chip detection signal of input is imported through VIN, behind partiting dc capacitor C1 filtration direct current signal, through positive input terminal 3 pin of operational amplifier U1A, export positive input terminal 5 pin of the operational amplifier U1B of three parallel connections to by 1 pin, positive input terminal 10 pin of operational amplifier U1C and positive input terminal 12 pin of operational amplifier U1D.Operational amplifier U1A is first operational amplifier, and operational amplifier U1B, U1C and U1D are second operational amplifier, series connection mutually between first operational amplifier and each second operational amplifier.
Export through partiting dc capacitor C2 after the output terminal 7 pin output signals of operational amplifier U1B, accordingly, through partiting dc capacitor C3 output, export through partiting dc capacitor C4 after the output terminal 14 pin output signals of operational amplifier U1D after the output terminal 8 pin output signals of operational amplifier U1C.Positive input terminal at operational amplifier U1A also is connected with divider resistance R1, R2, to satisfy the quiescent operation point voltage.
The chip detection signal is passed to three output terminal VO1, VO2 and VO3, and each output terminal can connect the FPGA platform of a checkout equipment, proofing chip function or benchmark multimedia equipment etc.The output terminal of each operational amplifier all feeds back to its negative input end.Output terminal 1 pin of operational amplifier U1A feeds back to its negative input end 2 pin, output terminal 7 pin of operational amplifier U1B feed back to its negative input end 6 pin, output terminal 8 pin of operational amplifier U1C feed back to its negative input end 9 pin, and output terminal 14 pin of operational amplifier U1D feed back to its negative input end 13 pin.Thereby realize output in 1: 1 of signal, from satisfying the consistance of signal output.
When detecting, also can select the circuit of N amplifier, N-1 forms of distribution according to actual conditions for multichannel; Can also adopt the circuit of a plurality of distribution chip detection signals, thereby realize multichannel output.For example: the distributor circuit shown in Fig. 4 can distribute three road detection signals, the vision signal of distributing multichannel if desired, also can adopt this distributor circuit to build multichannel output, connect a distributor circuit again in the 7 pin output as therein operational amplifier U1B, can realize five tunnel outputs.
By the distributor circuit of chip detection signal of the present utility model, expanded the input and output interface of chip under test, can insert the multichannel checkout equipment simultaneously; Multichannel chip detecting system of the present utility model can be realized chip functions is carried out multinomial detection simultaneously, has improved the efficient of detection chip, has shortened the time of detection chip; By connecting different checkout equipments, realize stronger versatility and multiple parallel testing process.
The above is a preferred embodiment of the present utility model only, is not limited to the utility model, and for a person skilled in the art, the utility model can have various changes and variation.All within spirit of the present utility model and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within the protection domain of the present utility model.
Claims (7)
1. the distributor circuit of a chip detection signal is characterized in that, comprising:
First operational amplifier, the positive input terminal of described first operational amplifier connects the divider resistance and first partiting dc capacitor, receives described chip detection signal;
A plurality of second operational amplifiers parallel with one another, the positive input terminal of each described second operational amplifier is connected to the output terminal of described first operational amplifier, the output terminal of each described second operational amplifier is connected with second partiting dc capacitor respectively, exports described chip detection signal via described second partiting dc capacitor.
2. distributor circuit according to claim 1 is characterized in that, the output terminal of described first operational amplifier and second operational amplifier feeds back respectively and is connected to its negative input end separately.
3. the chip detecting system that multichannel detects is characterized in that comprise the described distributor circuit of claim 1, the positive input terminal of first operational amplifier of described distributor circuit is connected to the FPGA that sends described chip detection signal; The output terminal of each second operational amplifier of described distributor circuit is connected to checkout equipment respectively.
4. chip detecting system according to claim 3 is characterized in that, described checkout equipment comprises oscillograph, logic analyser, multimedia equipment and has in the processing module of resolving audio frequency, video data function at least one.
6, chip detecting system according to claim 3 is characterized in that, described multimedia equipment is televisor or video disc player.
5. the chip detecting system that multichannel detects is characterized in that, comprises the described distributor circuit of claim 1, and the positive input terminal of first operational amplifier of described distributor circuit connects the signal generator that sends described chip detection signal; The output terminal of each second operational amplifier of described distributor circuit is connected to checkout equipment respectively.
6. chip detecting system according to claim 5 is characterized in that, described checkout equipment comprises the FPGA of oscillograph, logic analyser, checking chip under test and at least one in the benchmark multimedia equipment.
7. chip detecting system according to claim 5 is characterized in that, described benchmark multimedia equipment is televisor or video disc player.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201524162U CN201654183U (en) | 2010-03-24 | 2010-03-24 | Chip test signal distribution circuit and multiplex chip test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201524162U CN201654183U (en) | 2010-03-24 | 2010-03-24 | Chip test signal distribution circuit and multiplex chip test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201654183U true CN201654183U (en) | 2010-11-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010201524162U Expired - Fee Related CN201654183U (en) | 2010-03-24 | 2010-03-24 | Chip test signal distribution circuit and multiplex chip test system |
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| Country | Link |
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| CN (1) | CN201654183U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105606984A (en) * | 2015-12-18 | 2016-05-25 | 中国电子科技集团公司第四十一研究所 | Multi-parameter parallel test system and method of semiconductor wafer test |
| CN108989965A (en) * | 2018-08-09 | 2018-12-11 | 珠海格力智能装备有限公司 | Audio detection device and method |
-
2010
- 2010-03-24 CN CN2010201524162U patent/CN201654183U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105606984A (en) * | 2015-12-18 | 2016-05-25 | 中国电子科技集团公司第四十一研究所 | Multi-parameter parallel test system and method of semiconductor wafer test |
| CN105606984B (en) * | 2015-12-18 | 2019-04-09 | 中国电子科技集团公司第四十一研究所 | A kind of the multi-parameter parallel test system and method for test semiconductor wafer |
| CN108989965A (en) * | 2018-08-09 | 2018-12-11 | 珠海格力智能装备有限公司 | Audio detection device and method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101124 Termination date: 20130324 |