CN201607732U - Device for reducing random yield defect - Google Patents
Device for reducing random yield defect Download PDFInfo
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- CN201607732U CN201607732U CN2009202694469U CN200920269446U CN201607732U CN 201607732 U CN201607732 U CN 201607732U CN 2009202694469 U CN2009202694469 U CN 2009202694469U CN 200920269446 U CN200920269446 U CN 200920269446U CN 201607732 U CN201607732 U CN 201607732U
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Abstract
The utility model provides a device for reducing random yield defect, which comprises a critical area analyzing device, a critical area accumulating device, a circuit adjustment device and a comparison device, wherein the critical area analyzing device is used for analyzing critical areas, so as to obtain the open-circuit critical areas and short-circuit critical areas of a plurality of circuits to be corrected respectively; the critical area accumulating device is used for weighing and accumulating the open-circuit critical area and short-circuit critical area of each circuit to be corrected, so as to obtain the accumulated value; the circuit adjustment device is used for expanding and widening each circuit to be corrected to different degrees at the same time; the critical area analyzing device receives the different adjustment quantities and sequentially calculates the open-circuit critical area and short-circuit critical area of each adjusted circuit to be corrected; the critical area accumulating device receives the adjusted open-circuit critical area and short-circuit critical and sequentially obtains a plurality of adjusted accumulated values; and the comparison device is used for comparing the adjusted accumulated values, so as to determine the optimal adjustment quantity combination of the expansion and widening of each circuit to be corrected.
Description
Technical field
The utility model is about reducing the device of yield defective at random, particularly about widening (wire widening) to reduce the device of yield defective at random by circuit expansion (wire spreading) and circuit.
Background technology
The failure mode of the modal defective of yield at random is open circuit and short circuit, and it is because the particulate (particles) that accident drops in the manufacture of semiconductor causes.Though semiconductor dust free room or operator's console will be removed above the particulate of specification as much as possible,, still can be attached to the inefficacy that causes circuit on the integrated circuit (IC) chip because of particulate is improper when importing the nanoscale advanced process.
Generally speaking, non-conductive particulate is if the open circuit generation of (or claiming to open circuit) then probably can be caused in the centre of the metallic circuit predefined paths that just in time drops, and the probability of this generation is decided on this non-conductive atomic attachment position and diameter thereof.Conductive particle is if the generation of short circuit then probably can be caused in the gap in the two metallic circuit predefined paths that just in time drop again, and the same probability that takes place also is attachment position and the diameter thereof that depends on this conductive particle.If require semiconductor dust free room or operator's console to improve its cleanliness factor, as if can improve the Problem of Failure of above-mentioned open circuit and short circuit, but certainly will cause the significantly increase of manufacturing expense.If can in the circuit design flow process, consider the potential generation reason of these problems, then can effectively reduce the generation probability of the follow-up defective of yield at random, even reduce the cost input of the cleanliness factor requirement of semiconductor manufacturing industry.
For in the circuit design flow process, considering the problem of yield defective at random in advance, critical area analysis (Critical Area Analysis has been proposed at present; CAA) method, can be in the circuit design flow process via the circuit pattern of analyzing back winding placement (post-routing layout), and effectively predict the generation probability of the above-mentioned defective of yield at random.At the circuit that produces open circuit or short circuit probably, can be opened a way or the critical area of short circuit according to this method.Analyze for reducing the short circuit critical area of gained, effectively there is scope in the then many corrigendum steps that can take the circuit expansion with what reduce that particulate at random causes short circuit.Similarly, analyze for reducing the open circuit critical area of gained, then manyly can take corrigendum step that circuit widens effectively to have a scope with what reduce that particulate at random causes open circuit.
Fig. 1 is that tradition takes the step of circuit expansion to reduce the synoptic diagram of short circuit critical area.Circuit 11 and circuit 12 are because of adjoining among the figure, and therefore if suitably the conductive particle at random of diameter drops in the short circuit critical area CAs, then circuit 11 meetings and circuit 12 form short circuits.Therefore, a line segment 111 of circuit 11 can be expanded left, can be reduced short circuit critical area CAs by this.Line segment 111 after the expansion of circuit 11 ' clearly can increase path, that is open circuit critical area CAo can relatively increase because of this path.
After the circuit spread step was carried out, the corrigendum step that can then take circuit to widen further reduced the open circuit critical area.Yet, can increase the short circuit critical area again probably when when expanding back line segment 111 ' carry out circuit and widen.Therefore, (minimization) method that minimizes of tradition critical area is successively carried out the step that circuit is expanded and circuit is widened, obviously can't obtain the equilibrium point an of the best at open a way critical area and short circuit critical area efficiently, needing to experience repeatedly trial and wrong (trial and error) just can have preferable result.
Given this, electric design automation (Electronic Design Automation) industry needs a kind of automatic and efficient reduction method of yield defective at random, for solving the problem that present circuit design met with.
The utility model content
The reduction of the utility model one embodiment is the device of yield defective at random, comprises: a critical area analytical equipment, and the critical area analysis of layout of carrying out a chip is to obtain open circuit critical area and the short circuit critical area that several wait to correct circuit respectively; One critical area adding up device multiply by this open circuit critical area and short circuit critical area of waiting to correct in the circuit each respectively the weight number and adds up and obtain an accumulated value; One circuit adjusting gear, this is waited to correct in the circuit each carry out the different adjustment amounts that circuit expansion and circuit are widened simultaneously, wherein this critical area analytical equipment is accepted these different adjustment amounts and is calculated this in regular turn and wait to correct each adjusted open circuit critical area and short circuit critical area in the circuit, and this critical area adding up device is accepted these adjusted open circuit critical areas and the short circuit critical area obtains several adjusted accumulated values in regular turn again; And a comparison means, relatively this several adjusted accumulated value best adjustment amount combination to determine that circuit expansion that this waits to correct in the circuit each and circuit are widened.
The reduction of the present embodiment device of yield defective at random comprises an equipment more in addition, and this is waited to correct in the circuit corrigendum that each carries out best adjustment amount combination that this corresponding circuit expansion and circuit widen.
The utility model reduces the device of yield defective at random can be automatic and efficient reduction yield defective at random, widens value with the circuit propagation of the best and circuit and align, and the problem of yield defective also can significantly reduce at random.
Description of drawings
Fig. 1 is that tradition takes the step of circuit expansion to reduce the synoptic diagram of short circuit critical area;
Fig. 2 is according to the reduction of an embodiment of the present utility model process flow diagram of yield defective method at random;
Fig. 3 is according to the synoptic diagram that carries out the circuit corrigendum that circuit is expanded and circuit is widened among the embodiment of the present utility model; And
Fig. 4 is according to the reduction of an embodiment of the present utility model device calcspar of yield defective at random.
Embodiment
The utility model is a kind of reduction device of yield defective at random in this direction of inquiring into.In order to understand the utility model up hill and dale, detailed step and composition will be proposed in following description.Apparently, execution of the present utility model is not defined in the specific details that the technician was familiar with of circuit design.On the other hand, well-known composition or step are not described in the details, with the restriction of avoiding causing the utility model unnecessary.Preferred embodiment meeting of the present utility model is described in detail as follows, yet except these detailed descriptions, the utility model can also be implemented in other embodiments widely, and scope of the present utility model do not limited, its with after claims be as the criterion.
Fig. 2 is according to the reduction of an embodiment of the present utility model process flow diagram of the method for yield defective at random.After the placement and coiling (placement and routing) step of electric design automation, the deviser can obtain an ic design layout figure, shown in step 21.In addition, wafer manufacturing plant need provide a pair of weight number, gives similar and different weighted value Wopen and Wshort at open circuit and short circuit in the yield defective at random respectively.This can be according to makers' conductive particle of wafer and the non-conductive atomic ratio that exists to the weight number, or causes the relative influence property of process rate loss and decide.
Shown in step 22, carry out the critical area analysis according to this layout and get open circuit critical area and the short circuit critical area of respectively waiting to correct circuit then.For reducing calculated amount, this critical area analysis can be a kind of analysis process through simplifying, that is the express-analysis pattern of setting up is estimated open circuit critical area and short circuit critical area.This open circuit critical area CAo and short circuit critical area CAs that waits to correct in the circuit each be multiply by the weight number respectively and adds up and obtains an accumulated value CA, shown in step 23.
Shown in step 24, wait to correct in the circuit combination that each carries out the different adjustment amounts that circuit expansion and circuit widen simultaneously at this, for example: change side direction (perpendicular line footpath direction) the propagation WS_amount of local line and change the live width WW_amount of local line.Shown in step 25, if adjustment amount does not reach the limit, for example: adjustment amount does not reach violates DRC (Design Rule Check; DRC) the limit is then got back to the critical area analysis (critical area CAo and short circuit critical area CA open a way) of the combination of the above-mentioned different adjustment amounts of step 22 and step 23 execution and the calculating of accumulated value CA.If adjustment amount has reached the limit, then execution in step 26, relatively calculate each accumulated value CA of gained, thereby obtain the optimization that circuit is expanded and circuit the is widened corrigendum combination that those wait to correct circuit.For example: find out minimum accumulated value CA, wait to correct the optimization corrigendum combination of circuit as this by the adjustment amount combination that the circuit expansion and the circuit of this minimum accumulated value CA correspondence are widened.At last, can carry out the corrigendum that circuit is expanded and circuit is widened to those circuits to be corrected according to the optimization corrigendum combination of gained, shown in step 27.
Can be according to above-mentioned steps with accumulated value CA with following formulate:
CA＝Wshort×CAs(WW_amount，WS_amount)+Wopen×CAo(WW_amount，WS_amount) (1)
Wherein (WW_amount is that to represent CAs be the function of WW_amount and WS_amount WS_amount) to CAs; (WW_amount is that to represent CAo be the function of WW_amount and WS_amount WS_amount) to CAo.
The CA of above-listed formula (1) also is the function of WW_amount and WS_amount, therefore can obtain the optimum value of CA by changing WW_amount and WS_amount.The present embodiment optimum value is a minimum value, that is considers the weight ratio of open circuit and short circuit in the yield defective at random, and the minimum value that adds up after obtain opening a way critical area and the weighting of short circuit critical area.
Fig. 3 is according to the synoptic diagram that carries out the circuit corrigendum that circuit is expanded and circuit is widened among the embodiment of the present utility model.Circuit 31 and circuit 32 are because of adjoining among the figure, and therefore if suitably the conductive particle at random of diameter drops in the short circuit critical area 33, then circuit 31 meetings and circuit 32 form short circuits.Therefore, a line segment 311 of circuit 31 can be expanded left, can be reduced short circuit critical area CAs by this.Line segment 311 after the expansion of circuit 31 ' clearly can increase path, that is therefore open circuit critical area CAo can need consider the corrigendum that circuit is widened simultaneously relatively because of this path increases.Calculated value by step shown in Figure 2 and optimization formula (1) can obtain the propagation WS_amount that line segment 311 protrudes out a S left, and expansion back line segment 311 ' some need be W ' by former live width W increase live width WW_amount.The combination S of this propagation WS_amount and live width WW_amount and W ' are optimization corrigendum combination, make circuit designers and wafer manufacturing plant be met the corrigendum circuit of expectation most.
Fig. 4 is according to the reduction of an embodiment of the present utility model device calcspar of yield defective at random.Reducing at random, the device 40 of yield defective comprises more equipment 45 of a critical area analytical equipment 41, a critical area adding up device 42, a circuit adjusting gear 43, a comparison means 44 and.This critical area analytical equipment 41 is critical area analyses of carrying out the layout of a chip, just can obtain open circuit critical area CAo and short circuit critical area CAs that several wait to correct circuit respectively.Then, this critical area adding up device 42 multiply by this open circuit critical area CAo and short circuit critical area CAs that waits to correct in the circuit each respectively weight and counts Wopen and Wshort and add up and obtain an accumulated value CA.This circuit adjusting gear is waited to correct in the circuit change that each carries out the different adjustment amounts that circuit expansion and circuit widen simultaneously to this, this critical area analytical equipment 41 is accepted these different adjustment amounts then, and calculate in regular turn this wait to correct each adjusted open circuit critical area CAo1 in the circuit ... CAoN and short circuit critical area CAs1 ... CAsN, again this critical area adding up device 42 accept these adjusted open circuit critical area CAo1 ... CAoN and short circuit critical area CAs1 ... CAsN obtain in regular turn several adjusted accumulated value CA1 ... CAN.This comparison means 44 relatively this several adjusted accumulated value CA1 ... the size of CAN, this waits to correct best adjustment amount combination CAoX and the CAsX that the circuit of each is expanded and circuit is widened in the circuit to use decision.Then, more best adjustment amount combination CAoX that 45 pairs of these these circuits of waiting to correct each execution correspondence in the circuit of equipment are expanded and circuit is widened and the corrigendum of CAsX, so this circuit to be corrected can be widened the value levelling with the circuit propagation and the circuit of the best, and the problem of yield defective also can significantly reduce at random.Obviously this device 40 can be automatic and the efficient reduction incidence of yield defective at random, can solve the relevant issues that present circuit design met with.
Technology contents of the present utility model and technical characterstic disclose as above, yet the personage who is familiar with this technology still may be based on teaching of the present utility model and announcement and done all replacement and modifications that does not deviate from the utility model spirit.Therefore, protection domain of the present utility model should be not limited to those disclosed embodiments, and should comprise various do not deviate from replacement of the present utility model and modifications, and is contained by following application claims.
Claims (8)
1. one kind is reduced the device of yield defective at random, it is characterized in that comprising:
One critical area analytical equipment, the critical area analysis of layout of carrying out a chip is to obtain open circuit critical area and the short circuit critical area that several wait to correct circuit respectively;
One critical area adding up device is waited to correct in the circuit each open circuit critical area and the computing and add up and obtain an accumulated value respectively of short circuit critical area with this;
One circuit adjusting gear, this is waited to correct in the circuit each carry out the different adjustment amounts that circuit expansion and circuit are widened simultaneously, wherein this critical area analytical equipment is accepted these different adjustment amounts and is calculated this in regular turn and wait to correct each adjusted open circuit critical area and short circuit critical area in the circuit, and this critical area adding up device is accepted these adjusted open circuit critical areas and the short circuit critical area obtains several adjusted accumulated values in regular turn again; And
One comparison means, relatively these several adjusted accumulated value waits to correct the best adjustment amount combination that the circuit of each is expanded and circuit is widened in the circuit to determine this.
2. according to the device of claim 1, it is characterized in that it comprises an equipment more in addition, it waits to correct in the circuit corrigendum that each carries out best adjustment amount combination that this corresponding circuit expansion and circuit widen to this.
3. according to the device of claim 1, it is characterized in that, wherein this critical area adding up device is accepted several weight numbers, and this open circuit critical area and short circuit critical area of waiting to correct in the circuit each be multiply by adding up in the lump in this weight number respectively and obtains this accumulated value.
4. according to the device of claim 1, it is characterized in that, this comparison means this several adjusted accumulated value and find minimum value in these accumulated values relatively wherein, the adjustment amount of this circuit expansion of the minimum value correspondence of this accumulated value and the adjustment amount that this circuit is widened are this optimization corrigendum combinations of waiting to correct in the circuit each.
5. according to the device of claim 3, it is characterized in that wherein these several weight numbers are that generation probability according to open circuit and short circuit in the yield defective at random determines numerical values recited.
6. according to the device of claim 3, it is characterized in that wherein these several weight numbers are to determine numerical values recited according to makers' conductive particle of wafer and the non-conductive atomic ratio that exists.
7. according to the device of claim 3, it is characterized in that wherein this layout is a back winding placement.
8. according to the device of claim 3, it is characterized in that wherein this critical area analysis is an express-analysis pattern of estimating open circuit critical area and short circuit critical area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202694469U CN201607732U (en) | 2009-10-30 | 2009-10-30 | Device for reducing random yield defect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202694469U CN201607732U (en) | 2009-10-30 | 2009-10-30 | Device for reducing random yield defect |
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| Publication Number | Publication Date |
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| CN201607732U true CN201607732U (en) | 2010-10-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2009202694469U Expired - Lifetime CN201607732U (en) | 2009-10-30 | 2009-10-30 | Device for reducing random yield defect |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI641960B (en) * | 2017-04-05 | 2018-11-21 | 敖翔科技股份有限公司 | Intelligent caa failure pre-diagnosis method and system for design layout |
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2009
- 2009-10-30 CN CN2009202694469U patent/CN201607732U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI641960B (en) * | 2017-04-05 | 2018-11-21 | 敖翔科技股份有限公司 | Intelligent caa failure pre-diagnosis method and system for design layout |
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| C14 | Grant of patent or utility model | ||
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Granted publication date: 20101013 |