CN201569743U

CN201569743U - Russian ILS (instrument landing system) monitor

Info

Publication number: CN201569743U
Application number: CN2009202516442U
Authority: CN
Inventors: 王志军
Original assignee: Tianjin 764 Communication and Navigation Technology Corp
Current assignee: Tianjin 764 Communication and Navigation Technology Corp
Priority date: 2009-12-11
Filing date: 2009-12-11
Publication date: 2010-09-01
Anticipated expiration: 2019-12-11

Abstract

The utility model relates to a Russian ILS monitor comprising a monitor and a monitoring circuit arranged inside the monitor, wherein, the monitoring circuit comprises a control analogue switch, an A/D sampling chip, an FPGA module, an FRAM memory, a DSP processor and a serial module, the FPGA module is connected with the A/D sampling chip, the control analogue switch and the DSP processor respectively, the control analogue switch is connected with the A/D sampling chip, and the DSP processor is connected with the FRAM memory and the serial module respectively. The utility model has the following benefits: the Russian ILS monitor is improved by increasing the number of signals available to the monitor and the number of BIT verification signals available to each unit; in lieu of the original singlechip, a high-speed DSP capable of conducting periodic measurement on 3 occasions in the period of 1 second helps the monitor process at a higher rate; and the use of the 14-bit high-precision A/D chip with a higher sampling rate increases the measuring precision of the monitor to 0.3mV.

Description

Russia's blindness monitoring device

Technical field

The utility model relates to a kind of blind landing navigation product monitoring system made in Russia, particularly a kind of Russia blindness monitoring device.

Background technology

Monitor is a vitals in the whole navigation product, and function is the duty of the complete machine of monitoring comprehensively, in real time and accurately, and can in time produce corresponding alarm signal at fault-signal.

Comprehensive, the real-time and the accuracy of monitor monitors data are the key technical indexes of monitor.The existing monitors disappearance is to complete machine receiver and transmitter carrier frequency, the fixed delay of range finding extension set signal and the monitoring of pulse width; Existing monitor is practical finishes the various computings of whole process, the slow monitoring of finishing whole signal in 3 seconds of processing speed for the 89C196 single-chip microcomputer; The A/D chip that existing monitor measurement data is used is the outputs of 12 bit data, and the sampling input range is-10V-+10V, is 5mV on the measurement data precision, the actual conditions of characterization signal accurately, and error ratio is bigger.

Summary of the invention

In view of the defective that prior art exists, the utility model provides the blind system monitoring device of Russia that a kind of monitor signal is complete, computing speed is very fast, sampling rate is higher, measuring accuracy is higher.

The utility model for achieving the above object, the technical scheme of being taked is: a kind of Russia blindness monitoring device, comprise monitor, it is characterized in that: also comprise the observation circuit that is arranged in the monitor, described observation circuit comprises: control analog switch, A/D sampling A, FPGA module, FRAM storer, dsp processor and serial port module, described FPGA module is connected with A/D sampling A, control analog switch, dsp processor respectively, described control analog switch is connected with the A/D sampling A, and described dsp processor is connected with FRAM storer, serial port module respectively.

The beneficial effects of the utility model are: improve and improve blind landing monitor made in Russia, completion also increases the signal of monitor monitors, has increased each unit B IT validation signal; Adopt DSP at a high speed to substitute original single-chip microcomputer, all monitor signal periodic measurements 3 times can have been improved processing speed in 1 second time; Use high-precision A/D chip of 14, sampling rate is higher, and it is more accurate that measuring accuracy is brought up to 0.3mV.

Description of drawings

Fig. 1 is for the utility model circuit connection block diagram and as Figure of abstract.

Fig. 2 is that the utility model FPGA inside modules circuit connects block diagram.

Embodiment

As shown in Figure 1, Russia's blindness monitoring device, comprise monitor, also comprise the observation circuit that is arranged in the monitor, observation circuit comprises: control analog switch, A/D sampling A, FPGA module, FRAM storer, dsp processor and serial port module, the FPGA module is connected with A/D sampling A, control analog switch, dsp processor respectively, and the control analog switch is connected with the A/D sampling A, and dsp processor is connected with FRAM storer, serial port module respectively.

As shown in Figure 2, the internal monitoring treatment circuit structure of FPGA module is: A/D module, frequency measurement module, DME module, ISL module, AC-DC-BIT module and BLOCK-BIT module are connected with clock frequency division module and dsp interface respectively, and described A/D module is connected with phaselocked loop.

To monitor the signal of processing in the foregoing circuit:

1, monitor the multiple analog level signal that interface board is sent here, these signals comprise:

1300Hz, the 2100Hz pulse signal of reflection navigation channel audibility factor;

1300Hz, the 2100Hz pulse signal of reflection width audibility factor;

1300Hz, the 2100Hz pulse signal of reflection aperture audibility factor;

The dc level signal of reflection ILS (instrument landing) transmitter emissive power;

The dc level signal of reflection DME (DME transponder) transmitter emissive power.

2, the monitoring power level :+5V ,+15V ,-15V.

3, the audio signal frequency of monitoring sound signal plate generation: 12.5Hz, 2100Hz, 1300Hz.

4, the carrier frequency of generation is closed in monitoring frequently.

5, the self check of monitor itself: by the signal measurement channel linear self check of testing oneself of self-correcting signal generation unit.

6, measure DME transponder pulse width, measurement DME reply pulse spacing time, measurement DME transponder pulse fixed delay time.

7, with master control but and communication, the storage main control unit sends that each signal is pre-, the setting of alarming threshold here; The various measured values that monitor is measured are sent to main control unit; When measured signal value surpasses alarm or alarms thresholding in advance, monitor is sent alarm, is alarmed signal in advance to primary controller, shows each warning light simultaneously.

Principle of work:

1, audibility factor is measured: receive the pulse signal from navigation channel, aperture and the width of interface unit, select input signal respectively by the control analog switch, use high-speed sampling A/D that pulse is adopted among the inner FIFO of FPGA, send among the DSP, the level of measuring and calculating 1300 and 2100 calculates audibility factor.

2, power measurement: by the power voltage that the selection of control analog switch need be measured, press linear scaling measuring and calculating performance number, power reference need be calibrated by master control, is finished by DSP and measures calculating.

3, operating voltage is measured: the operating voltage by the selection of control analog switch is measured enters the A/D converted measurement.

4, survey frequency: gating will be surveyed signal, finishes unit interval counting frequency measurement in FPGA inside, and the frequency measurement signal comprises the 12.5Hz of audio unit, 1300Hz, and 2100Hz and frequency close the carrier frequency of output.

5, transponder pulse is measured: inner by measuring transponder pulse calculating pulse width, recurrent interval at FPGA; Calculate the transponder pulse fixed delay by the edge pulse that ranging receiver and transmitter are sent.

6, the signal calibration of testing oneself: master control is provided with 1300 and 2100 fixing pulse height ratios to audio unit, send into this unit by interface unit then, compare the intrinsic linear coefficient of obtaining passage with setting value, the linearity of calibration measurement passage is measured with the self calibration that reaches monitor unit.

Malfunction monitoring and alarm: this unit deposits the alarm and the early warning thresholding of each signal that master control is sent into by serial ports among the FRAM in, after detecting signal at every turn, result calculated and thresholding are compared, whether detection signal is alarmed, then alarm status and result of calculation are sent into main control unit by serial ports, implement the change action of corresponding alarm demonstration and active and standby machine then by master control.

Claims

1. Russia's blindness monitoring device, comprise monitor, it is characterized in that: also comprise the observation circuit that is arranged in the monitor, described observation circuit comprises: control analog switch, A/D sampling A, FPGA module, FRAM storer, dsp processor and serial port module, described FPGA module is connected with A/D sampling A, control analog switch, dsp processor respectively, described control analog switch is connected with the A/D sampling A, and described dsp processor is connected with FRAM storer, serial port module respectively.

2. Russia according to claim 1 blindness monitoring device, it is characterized in that: the internal monitoring treatment circuit structure of described FPGA module is: A/D module, frequency measurement module, DME module, ISL module, AC-DC-BIT module and BLOCK-BIT module are connected with clock frequency division module and dsp interface respectively, and described A/D module is connected with phaselocked loop.