CN201556196U - Multi-screen splicing display processor - Google Patents
Multi-screen splicing display processor Download PDFInfo
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- CN201556196U CN201556196U CN2009202377435U CN200920237743U CN201556196U CN 201556196 U CN201556196 U CN 201556196U CN 2009202377435 U CN2009202377435 U CN 2009202377435U CN 200920237743 U CN200920237743 U CN 200920237743U CN 201556196 U CN201556196 U CN 201556196U
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Abstract
The utility model relates to a multi-screen splicing display processor, and is particularly suitable for multi-screen splicing display processing of high resolution images. The multi-screen splicing display processor is characterized in that at least one dispatching pre-possessing branch circuit is provided with a high-speed serialization device in front of which an image segmentation device is serially connected and is used for segmenting a complete image into a plurality of sub-images; and the dispatching pretreatment branch circuits are combined into one way before the image segmentation device, and form a multi-way parallel connection after the same. The entity device structure provided by the utility model has a better real-time performance when used for processing images, especially high resolution images.
Description
Technical field
The utility model relates to the multi-screen splicing video-stream processor, is particularly useful for high-definition picture is carried out the multi-screen splicing display process.
Background technology
Needing the occasion of large screen display image, a plurality of screen splicings can got up form a giant-screen, carrying out multi-screen splicing and show that each screen is responsible for one of them part of display image, each screen is called a concatenation unit screen.For example will be on as the giant-screen of being made up of four concatenation unit screen a, b, c, d of Fig. 1 show complete image (comprising complete image first and several complete images of complete image the second grade) from the outside constantly simultaneously at a frame, what adopt at present is multi-screen splicing video-stream processor shown in Fig. 2,6.
As Fig. 2, high speed serialization scheduling bus front end is connected to many scheduling pre-treatment branch roads in parallel, every scheduling pre-treatment is propped up route format conversion apparatus, frame rate conversion device and high speed serialization makeup and is put successively that serial connection forms, and the analog or digital picture signal that format conversion apparatus is used for the foreign format that will be imported converts the digital signal of local form to; The frame rate conversion device uses the signal frame per second conversion cost ground frame per second of frame buffer district with outside source, for fear of the picture break-up problem that causes because of the mistiming that writes and read, the frame buffer district should have at least three, image (comprising complete image first and several complete images of complete image the second grade) in the frame buffer district in the branch road before many scheduling need be read concurrently with the form of frame synchronization, three two field pictures are read in turn to realize the continuous broadcast of image in the same frame buffer district herein; The state that conversion of signals is become to be fit to carry out the high-speed serial bus transmission is put in the high speed serialization makeup, comprises steps such as packing, coding, serial conversion.Same the frame rate conversion device and the high speed serialization makeup of dispatching in the pre-treatment branch road put and can be realized by the different hardware module in the same programmable logic device (PLD) fpga chip.
As Fig. 6, the task of high speed serialization scheduling bus is that the signal dispatching of self scheduling pre-treatment is in the future given respectively and concatenation unit screen a, b, c, four parallel scheduling aftertreatment branch roads that d is corresponding.Suppose only to consider complete image first and complete image second among Fig. 1, scheduling aftertreatment branch road a needs the top of processes complete image first and the upper left quarter of complete image second, scheduling aftertreatment branch road b only needs the upper right quarter of processes complete image second, scheduling aftertreatment branch road c needs the bottom of processes complete image first and the lower left quarter of complete image second, and scheduling aftertreatment branch road d only needs the right lower quadrant of processes complete image second.Therefore the signal of complete image first and complete image second need be provided scheduling aftertreatment a, c when carrying out high speed serialization scheduling bus at least, and only need provide complete image second to get final product at least to scheduling aftertreatment branch road b, d, shear by each scheduling aftertreatment branch road; High speed serialization scheduling bus also can be dispatched the part that aftertreatment need handle according to each complete image first and complete image second are sheared the part that the back provides its needs to handle to each scheduling aftertreatment branch road.
As Fig. 6, high speed serialization scheduling bus rear end is connected to many scheduling aftertreatment branch roads in parallel, every scheduling aftertreatment is propped up route and is separated high speed serialization device, image zoom circuit, image integration processing unit and show that output unit is connected in series successively and form, and having multi-channel parallel (promptly separate the high speed serialization device and the image zoom circuit has multi-channel parallel) to be used for handling respectively multiple image (for example image first and image second) before the image integration processing unit, is one the tunnel afterwards.The image zoom circuit is used for image zoom is become to be adapted at the size that shows on corresponding and the concatenation unit screen, the image integration processing unit is used for returning through the image of the multi-channel parallel of image zoom synthetic one the tunnel, shows through showing that output unit outputs on the corresponding concatenation unit screen.
The shortcoming of above-mentioned multi-screen splicing video-stream processor is, when the input high-definition picture, scheduling pre-treatment branch road required data quantity transmitted before image zoom will increase greatly, and the transmission frame per second will descend, and has influence on follow-up image zoom and handles frame per second.Promptly allow to keep former transmission frame per second, the processing frame per second of high-definition picture being carried out image zoom also can finally cause the real-time variation of multi-screen splicing display process well below the processing frame per second to normal image.
The utility model content
The utility model purpose
The utility model will provide the multi-screen splicing video-stream processor, and its entity apparatus structure can especially have preferable real-time during high-definition picture being used to handle image.
Technical scheme
The utility model provides the multi-screen splicing video-stream processor for this reason, comprises high speed serialization scheduling bus,
High speed serialization scheduling bus front end is connected to many scheduling pre-treatment branch roads in parallel, and every scheduling pre-treatment is propped up route format conversion apparatus, frame rate conversion device and high speed serialization makeup and put successively that serial connection forms,
High speed serialization scheduling bus rear end is connected to many scheduling aftertreatment branch roads in parallel, every scheduling aftertreatment is propped up route and is separated high speed serialization device, image zoom circuit, image integration processing unit and show that output unit is connected in series successively and form, and before the image integration device, multi-channel parallel is arranged, be one the tunnel afterwards
It is characterized in that,
High speed serialization makeup at least one scheduling pre-treatment branch road is serially connected with the image segmentation device before putting, and is used for a width of cloth complete image is divided into several subimages; This scheduling pre-treatment branch road was one the tunnel before the image segmentation device, was multi-channel parallel afterwards.
Beneficial effect
Because at least one scheduling pre-treatment branch road, be serially connected with the image segmentation device, this scheduling pre-treatment branch road was one the tunnel before the image segmentation device, be multi-channel parallel afterwards, so this scheduling pre-treatment branch road can be divided into a width of cloth complete image several subimages and correspondingly divide multipath transmission, has improved the transmission frame per second.In scheduling aftertreatment branch road, existing multi-screen splicing video-stream processor can only be used for the big not split image of a width of cloth is carried out image zoom, and the processing frame per second of image zoom is low; Multi-screen splicing video-stream processor of the present utility model can be used in several subimages are carried out image zoom concurrently, the processing frame per second height of image zoom, under given processing frame per second requires, the not split image big to a width of cloth carries out image zoom, needs superior performance but the high image zoom equipment of price; Several little subimages are carried out image zoom concurrently, only need many group poor-performings but cheap image zoom circuit, total cost still is lower than one group of superior performance, the high image zoom circuit of price.In sum, the utility model with above-mentioned entity apparatus structure can have preferable real-time when being used to handle high-definition picture.Utilize entity apparatus structure of the present utility model to carry out the performed computer program of multi-screen splicing display process and should be different from the computer program of in existing entity apparatus structure, carrying out.
Description of drawings
Fig. 1 is the synoptic diagram that shows complete image first and complete image second on the giant-screen of being made up of four concatenation unit screen a, b, c, d at a frame constantly simultaneously.
Fig. 2 is the scheduling pre-treatment branch road of background technology and the structured flowchart of high speed serialization scheduling bus.
Fig. 3 is the structured flowchart of the utility model scheduling pre-treatment branch road embodiment one.
Fig. 4 is the structured flowchart of the utility model scheduling pre-treatment branch road embodiment two.
Fig. 5 is the structured flowchart of the utility model scheduling pre-treatment branch road embodiment three.
Fig. 6 is the scheduling aftertreatment branch road of background technology and the structured flowchart of high speed serialization scheduling bus.
Fig. 7 is the structured flowchart of the utility model scheduling aftertreatment branch road a.
Fig. 8 is the frame rate conversion operation chart in the utility model scheduling pre-treatment branch road embodiment one, two.
Fig. 9 is the frame rate conversion operation chart in the utility model scheduling pre-treatment branch road embodiment three.
Among each figure, solid box presentation-entity device, frame of broken lines is represented virtual functional module/storage area/operation steps.
Embodiment
In order on as the giant-screen of forming by four concatenation unit screen a, b, c, d of Fig. 1, to show several complete images that comprise complete image first and complete image second constantly simultaneously, adopt multi-screen splicing video-stream processor hereinafter described to dispatch pre-treatment, high-speed serial bus scheduling and scheduling aftertreatment successively at a frame.
High speed serialization scheduling bus front end is connected to many scheduling pre-treatment branch roads in parallel, every scheduling pre-treatment is propped up route format conversion apparatus, frame rate conversion device and high speed serialization makeup and is put successively that serial connection forms, and the analog or digital picture signal that format conversion apparatus is used for the foreign format that will be imported converts the digital signal of local form to; The frame rate conversion device uses the signal frame per second conversion cost ground frame per second of frame buffer district with outside source; The high speed serialization makeup is put and is converted each road signal to be fit to carry out the high-speed serial bus transmission high-speed serial signals respectively, comprise steps such as packing, coding, serial conversion, same frame rate conversion device and high speed serialization makeup of dispatching in the pre-treatment branch road put and can be realized by the different hardware module in the same programmable logic device (PLD) fpga chip.Be serially connected with the image segmentation device on every scheduling pre-treatment branch road, be used for a width of cloth complete image is divided into several subimages; This scheduling pre-treatment branch road was one the tunnel before the image segmentation device, was multi-channel parallel afterwards.With the scheduling pre-treatment branch road first of the complete image first being dispatched pre-treatment is example, and three kinds of embodiments are hereinafter described arranged.N hereinafter is the natural number greater than 1.
Scheduling pre-treatment branch road embodiment one
As Fig. 3, the image segmentation device is connected on the format conversion apparatus front end, is used for before format conversion the image segmentation of non-native format is become the N road.Like this then format conversion apparatus, frame rate conversion device and high speed serialization makeup subsequently are put and are the parallel connection of N road.Image segmentation device in the present embodiment can be an external equipment, need before carrying out image segmentation, earlier image transitions be become the signal of this external equipment form, but this conversion does not belong to the category of this paper alleged " format conversion "---alleged " format conversion " of this paper is meant and converts non-native format to local form, is not meant other forms such as converting this external equipment form to.Because the picture signal of using this external equipment to carry out the image segmentation gained is the signal of this external equipment form, so after image segmentation finishes, also need signal to be carried out the alleged format conversion of this paper, each way image transitions of this external equipment form become native format with the format conversion apparatus among Fig. 3.Present embodiment is carried out format conversion after image segmentation, can not guarantee that this each width of cloth subimage that belongs to same width of cloth complete image is provided in each format conversion with the form of frame synchronization, thereby the conversion of conducting frame rate the time causes a part in this each width of cloth subimage that belongs to same width of cloth complete image to be put under mistakenly being positioned at the front/rear picture frame of first picture frame carrying out frame synchronization easily, causes the final multiple image that shows the problem of picture break-up to occur.
Scheduling pre-treatment branch road embodiment two
As Fig. 4, the image segmentation device is connected between format conversion apparatus and the frame rate conversion device, is used for after format conversion becoming the N road to carry out frame rate conversion again the image segmentation of non-native format.So then format conversion apparatus is one the tunnel, and frame rate conversion device and high speed serialization makeup are put and be the parallel connection of N road.Present embodiment is carried out format conversion to complete image earlier, after image segmentation, carry out frame rate conversion at once, guarantee of the form output of this each width of cloth subimage that belongs to same width of cloth complete image, solved the problem of the picture break-up that causes because of format conversion is asynchronous with frame synchronization.
The frame rate conversion of scheduling pre-treatment branch road embodiment one, two
N the frame rate conversion that lays respectively in the frame rate conversion device of N road operated as Fig. 8, at least three frame buffer districts are used in the frame buffer of each frame rate conversion device, three two field pictures are read in turn to realize the continuous broadcast of image in the same frame buffer district, and the frame synchronization of each frame rate conversion reads just correspondingly to read the N width of cloth subimage that belongs to first respectively with other form of dispatching the frame rate conversion frame synchronization of pre-treatment branch road.
Scheduling pre-treatment branch road embodiment three and frame rate conversion thereof
As Fig. 5, the image segmentation device is built in the frame rate conversion device.Particularly as Fig. 9, the frame rate conversion device is used at least three frame buffer districts, the image segmentation that the image segmentation device will be positioned at the frame buffer district becomes N width of cloth subimage, frame synchronization read just correspondingly with the form of the frame rate conversion frame synchronization of second read respectively belong to first N width of cloth subimage to N bar transmission shunt.Like this then input end format conversion apparatus and frame rate conversion is one the tunnel, the output terminal of frame rate conversion and high speed serialization makeup are put and are the parallel connection of N road.Present embodiment because of one road image in the frame buffer district by after cutting apart immediately in the frame synchronization read step form with frame synchronization be read out each along separate routes, just further guaranteed that this image subimage in each road when one road branch multichannel can be divided into other picture frame mistakenly.And it not only can solve the problem of the picture break-up that causes because of format conversion is asynchronous, can also simplied system structure: (1) need not to establish a storage space in addition for image segmentation step, can save the circuit that is used between image segmentation dedicated memory space and the used hardware of frame rate conversion step simultaneously; (2) input at frame rate conversion place has only one the tunnel, many inputs need not be set along separate routes, can save the incoming line at frame rate conversion place simultaneously.
The task of high speed serialization scheduling bus is that the signal dispatching of self scheduling pre-treatment is in the future given respectively and concatenation unit screen a, b, c, four parallel scheduling aftertreatment branch roads that d is corresponding.Suppose only to consider complete image first and complete image second among Fig. 1, scheduling aftertreatment branch road a needs the top of processes complete image first and the upper left quarter of complete image second, scheduling aftertreatment branch road b only needs the upper right quarter of processes complete image second, scheduling aftertreatment branch road c needs the bottom of processes complete image first and the lower left quarter of complete image second, scheduling aftertreatment branch road d only needs the right lower quadrant of processes complete image second, therefore high speed serialization scheduling bus is to scheduling aftertreatment branch road a, c need provide the signal of complete image first and complete image second, and to scheduling aftertreatment branch road b, d only need provide complete image second to get final product at least, is responsible for shearing by each scheduling aftertreatment branch road; High speed serialization scheduling bus also can be dispatched the part that the aftertreatment branch road need handle according to each complete image first and complete image second are sheared the part that the back provides its needs to handle to each scheduling aftertreatment branch road.
Every scheduling aftertreatment is propped up route and is separated high speed serialization device, image zoom circuit, image integration processing unit and show that output unit is connected in series successively and form, and before the image integration processing unit multi-channel parallel is arranged, and is one the tunnel afterwards.A is an example with scheduling aftertreatment branch road, as Fig. 7, suppose that its corresponding concatenation unit screen a need show that in the complete image first several (are assumed to be n, n is the natural number that is not more than above-mentioned N) experimental process image and other image that need show in the subimage, complete image second, the several that then need take is wherein separated high speed serialization device and image zoom circuit, and wherein in order to show the n number of sub images in the complete image first, high speed serialization device and image zoom circuit are separated in the n road that need take wherein; In order to show the experimental process image in the complete image second, just separate the high speed serialization device and the image zoom circuit takies since the n+1 road.The image integration processing unit splices the some width of cloth subimages that belong to first, the some width of cloth subimages that belong to second are spliced, and the like, then each width of cloth spliced image is carried out image overlay, so far the image of multi-channel parallel is returned and is synthesized one the tunnel, just can show through showing that output unit output on the corresponding concatenation unit screen.
Statement is during quantity, and " many " as herein described are meant more than or equal to two, and for example " a plurality of " are meant more than or equal to two, and " several " be meant more than or equal to two width of cloth, or the like.
Claims (4)
1. the multi-screen splicing video-stream processor comprises high speed serialization scheduling bus,
High speed serialization scheduling bus front end is connected to many scheduling pre-treatment branch roads in parallel, and every scheduling pre-treatment is propped up route format conversion apparatus, frame rate conversion device and high speed serialization makeup and put successively that serial connection forms,
High speed serialization scheduling bus rear end is connected to many scheduling aftertreatment branch roads in parallel, every scheduling aftertreatment is propped up route and is separated high speed serialization device, image zoom circuit, image integration processing unit and show that output unit is connected in series successively and form, and before the image integration device, multi-channel parallel is arranged, be one the tunnel afterwards
It is characterized in that,
High speed serialization makeup at least one scheduling pre-treatment branch road is serially connected with the image segmentation device before putting, and is used for a width of cloth complete image is divided into several subimages; This scheduling pre-treatment branch road was one the tunnel before the image segmentation device, was multi-channel parallel afterwards.
2. according to the multi-screen splicing video-stream processor of claim 1, it is characterized in that the image segmentation device is built in the frame rate conversion device.
3. according to the multi-screen splicing video-stream processor of claim 1, it is characterized in that the image segmentation device is connected on the format conversion apparatus front end.
4. according to the multi-screen splicing video-stream processor of claim 1, it is characterized in that the image segmentation device is connected between format conversion apparatus and the frame rate conversion device.
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| CN2009202377435U CN201556196U (en) | 2009-10-23 | 2009-10-23 | Multi-screen splicing display processor |
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| CN2009202377435U CN201556196U (en) | 2009-10-23 | 2009-10-23 | Multi-screen splicing display processor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105652459A (en) * | 2010-12-16 | 2016-06-08 | 索尼公司 | Wireless receiving device |
| CN105897543A (en) * | 2016-05-31 | 2016-08-24 | 陈专 | Network parallel and information overlapping display system |
| CN111050092A (en) * | 2019-12-31 | 2020-04-21 | 南京图格医疗科技有限公司 | Method for demultiplexing ultrahigh resolution image |
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2009
- 2009-10-23 CN CN2009202377435U patent/CN201556196U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105652459A (en) * | 2010-12-16 | 2016-06-08 | 索尼公司 | Wireless receiving device |
| CN105652459B (en) * | 2010-12-16 | 2020-04-24 | 索尼公司 | Image display apparatus and image generation apparatus |
| CN105897543A (en) * | 2016-05-31 | 2016-08-24 | 陈专 | Network parallel and information overlapping display system |
| CN111050092A (en) * | 2019-12-31 | 2020-04-21 | 南京图格医疗科技有限公司 | Method for demultiplexing ultrahigh resolution image |
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Granted publication date: 20100818 Termination date: 20161023 |