CN201550180U - Double-standard switch circuit on ground digital set top box - Google Patents
Double-standard switch circuit on ground digital set top box Download PDFInfo
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- CN201550180U CN201550180U CN2009201812720U CN200920181272U CN201550180U CN 201550180 U CN201550180 U CN 201550180U CN 2009201812720 U CN2009201812720 U CN 2009201812720U CN 200920181272 U CN200920181272 U CN 200920181272U CN 201550180 U CN201550180 U CN 201550180U
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Abstract
A double-standard switch circuit on a ground digital set top box comprises a high frequency head, a main chip STi5105, a first demodulating circuit, a second demodulating circuit and a change-over switch circuit, wherein the high frequency head is respectively connected to the input ends of the first demodulating circuit and the second demodulating circuit; the output ends of the first demodulating circuit and the second demodulating circuit are connected to the change-over switch circuit; the output end of the change-over switch circuit is connected to a CPU in the main chip STi5105; the CPU in the main chip Sti5105 is respectively connected to the first demodulating circuit and the second demodulating circuit; the high frequency head receives the data signal through an antenna; the high frequency head is controlled by the CPU to be tuned to a digital channel; the CPU controls the change-over switch circuit to select a TS stream in the first demodulating circuit or the second demodulating circuit and the TS stream is input into the CPU for decoding. The utility model has the advantage that the subscriber could watch the national standard program and the Euro standard program on a set top box without purchasing two standard set top boxes.
Description
[technical field]
The utility model is about a kind of set-top box internal circuit, is meant a kind of circuit of realizing that on the ground digital set-top box two marks switch especially.
[background technology]
At present, set-top box technique is developed faster, not only is used widely in fixing environment, the terrestrial television set-top box of various various criterions occurred, and Europe superscript terrestrial television set-top box is arranged, and the GB terrestrial TV set-top box is arranged.These set-top box have all adopted single demodulation chip, can watch Europe superscript program or GB program.
Above-mentioned digital TV set-top box can not compatible Europe superscript and GB, if the existing GB signal in area also has the Europe superscript signal, wants to receive these two kinds of signals so and just can separate this two kinds of signals by must need two set-top box by above-mentioned Digital Television.
[utility model content]
Technical problem to be solved in the utility model is to provide a kind of circuit of realizing two mark switchings on the ground digital set-top box that the Europe superscript signal also can be separated the GB signal of realizing both can having separated on a set-top box.
The utility model solves the problems of the technologies described above by the following technical programs: a kind of circuit of realizing that on the ground digital set-top box two marks switch, comprise tuner and master chip STi5105, also comprise first demodulator circuit, second demodulator circuit, and switching switch circuit, described tuner is connected respectively to the input of first demodulator circuit and second demodulator circuit, the output of first demodulator circuit and second demodulator circuit is connected to switching switch circuit, the output of switching switch circuit is connected to the CPU in the master chip STi5105, and the CPU in the master chip STi5105 also links first demodulator circuit and second demodulator circuit respectively.
The utility model can further be specially:
What described tuner adopted is the DTT73000 tuner.
Described first demodulator circuit adopts the demodulation chip MT353 of Europe superscript output, wherein 30 pin of demodulation chip MT353 and 31 pin are connected to two IQ signal pins of tuner respectively by capacitor C 66, C69, capacitor C 67, C68 are connected between 30 pin and 31 pin of demodulation chip MT353, the node ground connection between capacitor C 67, the C68; 41 pin and 42 pin more respectively through a DC component resistance R 39, R35, are exported to the RFAGC and the IFAGC signal pins of tuner respectively by behind the low pass filter that is made of respectively resistance R 41, R40, capacitor C 72 and R36, R37, capacitor C 71 respectively; Offer first group of I2C signal of high frequency by 35 pin and 36 pin; 24 pin and 23 pin are connected to the crystal oscillating circuit of being made up of peripheral oscillator Y2, resistance C79, C80; 9 pin are connected to the resetting pin of CPU by resistance R 48; 4 pin and 5 pin are connected to one group of I2C signal of CPU respectively by resistance R 60 and R59; 11 pin are judged pin as state; 47 pin～53 pin wherein, 56 pin～58 pin, 61 pin are exported 11 TS stream signal to switching switch circuits respectively and are switched selection.
Described second demodulator circuit comprises demodulation chip LGS8913, the phase-locked loop chip AD9203 of GB output and the SDRAM chip K4S641632D of 64M, described demodulation chip LGS8913 is connected to tuner by phase-locked loop chip AD9203, demodulation chip LGS8913 is connected to CPU simultaneously, and SDRAM chip K4S641632D is connected to demodulation chip LGS8913.
3 pin of described demodulation chip LGS8913～7 pin, 10 pin～12 pin, 15 pin～17 pin are exported 11 TS stream signal to switching switch circuits respectively and are switched selection; 66 pin and 71 pin are connected to one group of I2C signal of CPU respectively by resistance R 20 and R17.
Described switching switch circuit is made of three GSB330A chips, wherein the TS of 2 pin of first GSB330A chip and second GSB330A chip, 5 pin, 11 pin, 14 pin difference receiving demodulation chip MT353 output flows signal, and 2 pin of the 3rd GSB330A chip, 5 pin, 11 the pin TS of receiving demodulation chip MT353 output respectively flow signal; Wherein the TS of 3 pin of first GSB330A chip and second GSB330A chip, 6 pin, 10 pin, 13 pin difference receiving demodulation chip LGS8913 output flows signal, and 3 pin of the 3rd GSB330A chip, 6 pin, 10 the pin TS of receiving demodulation chip MT353 output respectively flow signal; 4 pin of first GSB330A chip and second GSB330A chip, 7 pin, 9 pin, 12 pin, and 4 pin of three GSB330A chips, 7 pin, 9 pin are connected respectively to 11 IO ports of CPU.
The utility model is in the advantage that realizes the circuit that two marks switch on the ground digital set-top box: make that the user only needs not only can watch the GB program but also can watch the Europe superscript program on a set-top box, need not to buy the set-top box of two these standards.
[description of drawings]
The utility model will be further described in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the utility model is realized the circuit that two marks switch on the ground digital set-top box a theory diagram.
Fig. 2 is the circuit diagram of tuner of the present utility model.
Fig. 3 is the circuit diagram of first demodulator circuit of the present utility model.
Fig. 4 is the circuit diagram of CPU of the present utility model and switching switch circuit.
Fig. 5, Fig. 6, Fig. 7 are the circuit diagrams of second demodulator circuit of the present utility model.
[embodiment]
See also Fig. 1, the utility model realizes that on the ground digital set-top box circuit that two marks switch comprises tuner (TUNER), first demodulator circuit, second demodulator circuit, switching switch circuit, and master chip STi5105.
Described tuner is connected respectively to the input of first demodulator circuit and second demodulator circuit, the output of first demodulator circuit and second demodulator circuit is connected to switching switch circuit, and the output of switching switch circuit is connected to the CPU in the master chip STi5105.Simultaneously, the CPU in the master chip STi5105 also links first demodulator circuit and second demodulator circuit respectively.
What described tuner adopted is the DTT73000 tuner of Thomson company, receives the program stream from antenna, offers first demodulator circuit and second demodulator circuit and is demodulated to TS stream signal.
First demodulator circuit and second demodulator circuit adopt the demodulation chip MT353 and the LGS8913 of various criterion respectively, demodulation chip MT353 realizes Europe superscript output, demodulation chip LGS8913 realizes GB output, and the TS stream signal of first demodulator circuit and the output of second demodulator circuit offers switching switch circuit.
That described switching switch circuit adopts is diverter switch chip GSB330A, is used to switch the TS stream of selecting two sections of demodulation chips and reaches Europe superscript output or GB output, and the CPU that inputs to master chip STi5105 then encodes.
And two demodulation chip LGS8913 and MT353, they are undertaken the I2C signal of this two chip is switched selection by the CPU among the master chip STi5105.
Described tuner is by connecting the antenna receiving digital signals, front end under the control of master chip STi5105 innernal CPU by the I2C bus tuner be tuned to certain digital channel, control the output of IO mouth voltage height as the IO mouth by the pin of CPU, realize the switching selection demodulation chip MT353 (IO output low level) of switch and the TS stream of demodulation chip LGS8913 (IO exports high level), deliver to demodulation chip and carry out demodulation, become TS stream input master chip STi5105 to decode the digital demodulation signal of ground GB and Europe superscript.
Please consult Fig. 2, Fig. 3, shown in Figure 4 simultaneously, first demodulator circuit adopts the demodulation chip MT353 of Europe superscript output, wherein 30 pin of demodulation chip MT353 and 31 pin are connected to two IQ signal pins of tuner respectively by capacitor C 66, C69, capacitor C 67, C68 are connected between 30 pin and 31 pin of demodulation chip MT353, the node ground connection between capacitor C 67, the C68; 41 pin and 42 pin more respectively through a DC component resistance R 39, R35, are exported to the RFAGC and the IFAGC signal pins of tuner respectively by behind the low pass filter that is made of respectively resistance R 41, R40, capacitor C 72 and R36, R37, capacitor C 71 respectively; Offer first group of I2C signal of high frequency by 35 pin and 36 pin; 24 pin and 23 pin are connected to the 20.48MHz crystal oscillating circuit of being made up of peripheral oscillator Y2, resistance C79, C80; 9 pin are connected to the resetting pin of CPU by resistance R 48; 4 pin and 5 pin are connected to one group of I2C signal of CPU respectively by resistance R 60 and R59; 11 pin are used for judging whether the signal that is received is normal; 47 pin～53 pin wherein, 56 pin～58 pin, 61 pin are exported 11 TS stream signal to switching switch circuits respectively and are switched selection.
Please consult Fig. 5, Fig. 6, shown in Figure 7 simultaneously, be the circuit diagram of second demodulator circuit of the present utility model, described second demodulator circuit comprises demodulation chip LGS8913, the phase-locked loop chip AD9203 of GB output and the SDRAM chip K4S641632D of 64M.Described demodulation chip LGS8913 is connected to tuner by phase-locked loop chip AD9203, and demodulation chip LGS8913 is connected to CPU simultaneously, and SDRAM chip K4S641632D is connected to demodulation chip LGS8913, and the information stores space is provided.3 pin of demodulation chip LGS8913～7 pin wherein, 10 pin～12 pin, 15 pin～17 pin are exported 11 TS stream signal to switching switch circuits respectively and are switched selection; 9 pin are connected to the resetting pin of CPU by resistance R 48; 66 pin and 71 pin are connected to one group of I2C signal of CPU respectively by resistance R 20 and R17.
Please consult Fig. 4 again, it is the circuit diagram of CPU and switching switch circuit, described switching switch circuit is made of three GSB330A chips, wherein the TS of 2 pin of first GSB330A chip and second GSB330A chip, 5 pin, 11 pin, 14 pin difference receiving demodulation chip MT353 output flows signal, and 2 pin of the 3rd GSB330A chip, 5 pin, 11 the pin TS of receiving demodulation chip MT353 output respectively flow signal; Wherein the TS of 3 pin of first GSB330A chip and second GSB330A chip, 6 pin, 10 pin, 13 pin difference receiving demodulation chip LGS8913 output flows signal, and 3 pin of the 3rd GSB330A chip, 6 pin, 10 the pin TS of receiving demodulation chip MT353 output respectively flow signal; 4 pin of first GSB330A chip and second GSB330A chip, 7 pin, 9 pin, 12 pin, and 4 pin of three GSB330A chips, 7 pin, 9 pin are connected respectively to 11 IO ports of CPU.Wherein among Fig. 4,11 groups of network names by the DVB beginning are TS stream signals that output is provided by Europe superscript scheme demodulation chip MT353,11 groups of network names by the DMB beginning are to provide output TS signal by GB scheme demodulation chip LGS8913, they mainly are to control the output just of IO mouth voltage by the pin of CPU as the I/O mouth, realize that the switching of switch selects the TS of demodulation chip MT353 (IO output low level) and demodulation chip LGS8913 (IO exports high level) to flow signal.
Claims (6)
1. on the ground digital set-top box, realize two circuit that switch of marking for one kind, comprise tuner and master chip STi5105, it is characterized in that: also comprise first demodulator circuit, second demodulator circuit, and switching switch circuit, described tuner is connected respectively to the input of first demodulator circuit and second demodulator circuit, the output of first demodulator circuit and second demodulator circuit is connected to switching switch circuit, the output of switching switch circuit is connected to the CPU in the master chip STi5105, and the CPU in the master chip STi5105 also links first demodulator circuit and second demodulator circuit respectively.
2. the circuit of realizing that on the ground digital set-top box two marks switch as claimed in claim 1, it is characterized in that: what described tuner adopted is the DTT73000 tuner.
3. the circuit of realizing that on the ground digital set-top box two marks switch as claimed in claim 1, it is characterized in that: described first demodulator circuit adopts the demodulation chip MT353 of Europe superscript output, wherein 30 pin of demodulation chip MT353 and 31 pin are connected to two IQ signal pins of tuner respectively by capacitor C 66, C69, capacitor C 67, C68 are connected between 30 pin and 31 pin of demodulation chip MT353, the node ground connection between capacitor C 67, the C68; 41 pin and 42 pin more respectively through a DC component resistance R 39, R35, are exported to the RFAGC and the IFAGC signal pins of tuner respectively by behind the low pass filter that is made of respectively resistance R 41, R40, capacitor C 72 and R36, R37, capacitor C 71 respectively; Offer first group of I2C signal of high frequency by 35 pin and 36 pin; 24 pin and 23 pin are connected to the crystal oscillating circuit of being made up of peripheral oscillator Y2, resistance C79, C80; 9 pin are connected to the resetting pin of CPU by resistance R 48; 4 pin and 5 pin are connected to one group of I2C signal of CPU respectively by resistance R 60 and R59; 11 pin are judged pin as state; 47 pin～53 pin wherein, 56 pin～58 pin, 61 pin are exported 11 TS stream signal to switching switch circuits respectively and are switched selection.
4. the circuit of realizing that on the ground digital set-top box two marks switch as claimed in claim 3, it is characterized in that: described second demodulator circuit comprises demodulation chip LGS8913, the phase-locked loop chip AD9203 of GB output and the SDRAM chip K4S641632D of 64M, described demodulation chip LGS8913 is connected to tuner by phase-locked loop chip AD9203, demodulation chip LGS8913 is connected to CPU simultaneously, and SDRAM chip K4S641632D is connected to demodulation chip LGS8913.
5. the circuit of realizing that on the ground digital set-top box two marks switch as claimed in claim 4, it is characterized in that: 3 pin of described demodulation chip LGS8913～7 pin, 10 pin～12 pin, 15 pin～17 pin are exported 11 TS stream signal to switching switch circuits respectively and are switched selection; 66 pin and 71 pin are connected to one group of I2C signal of CPU respectively by resistance R 20 and R17.
6. the circuit of realizing that on the ground digital set-top box two marks switch as claimed in claim 5, it is characterized in that: described switching switch circuit is made of three GSB330A chips, wherein the TS of 2 pin of first GSB330A chip and second GSB330A chip, 5 pin, 11 pin, 14 pin difference receiving demodulation chip MT353 output flows signal, and 2 pin of the 3rd GSB330A chip, 5 pin, 11 the pin TS of receiving demodulation chip MT353 output respectively flow signal; Wherein the TS of 3 pin of first GSB330A chip and second GSB330A chip, 6 pin, 10 pin, 13 pin difference receiving demodulation chip LGS8913 output flows signal, and 3 pin of the 3rd GSB330A chip, 6 pin, 10 the pin TS of receiving demodulation chip MT353 output respectively flow signal; 4 pin of first GSB330A chip and second GSB330A chip, 7 pin, 9 pin, 12 pin, and 4 pin of three GSB330A chips, 7 pin, 9 pin are connected respectively to 11 IO ports of CPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009201812720U CN201550180U (en) | 2009-11-12 | 2009-11-12 | Double-standard switch circuit on ground digital set top box |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009201812720U CN201550180U (en) | 2009-11-12 | 2009-11-12 | Double-standard switch circuit on ground digital set top box |
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| Publication Number | Publication Date |
|---|---|
| CN201550180U true CN201550180U (en) | 2010-08-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009201812720U Expired - Fee Related CN201550180U (en) | 2009-11-12 | 2009-11-12 | Double-standard switch circuit on ground digital set top box |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201550180U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102325268A (en) * | 2011-09-06 | 2012-01-18 | 四川金网通电子科技有限公司 | Method for realizing regional control on live broadcasting satellite and national standard T dual-mode set top box |
| CN105915824A (en) * | 2015-12-13 | 2016-08-31 | 乐视致新电子科技（天津）有限公司 | Module group capable of performing signal demodulation and device thereof |
| WO2018000912A1 (en) * | 2016-06-27 | 2018-01-04 | 深圳市九洲电器有限公司 | Method and system for selecting and processing multiple paths of ts streams |
-
2009
- 2009-11-12 CN CN2009201812720U patent/CN201550180U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102325268A (en) * | 2011-09-06 | 2012-01-18 | 四川金网通电子科技有限公司 | Method for realizing regional control on live broadcasting satellite and national standard T dual-mode set top box |
| CN102325268B (en) * | 2011-09-06 | 2015-07-08 | 四川金网通电子科技有限公司 | Method for realizing regional control on live broadcasting satellite and national standard T dual-mode set top box |
| CN105915824A (en) * | 2015-12-13 | 2016-08-31 | 乐视致新电子科技（天津）有限公司 | Module group capable of performing signal demodulation and device thereof |
| WO2018000912A1 (en) * | 2016-06-27 | 2018-01-04 | 深圳市九洲电器有限公司 | Method and system for selecting and processing multiple paths of ts streams |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100811 Termination date: 20141112 |
|
| EXPY | Termination of patent right or utility model |