CN201527965U - Mcm/d大功率组件 - Google Patents

Mcm/d大功率组件 Download PDF

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CN201527965U
CN201527965U CN 200920109596 CN200920109596U CN201527965U CN 201527965 U CN201527965 U CN 201527965U CN 200920109596 CN200920109596 CN 200920109596 CN 200920109596 U CN200920109596 U CN 200920109596U CN 201527965 U CN201527965 U CN 201527965U
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mcm
power
technology
make
power component
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刘丽辉
姜贵云
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Beijing Feiyu Microelectronics Co., Ltd.
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BEIJING FEIYU MICROELECTRONICS Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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Abstract

一种采用薄膜多层布线技术制作的MCM/D大功率组件，它是MCM/D和厚膜技术相结合的实用化技术，能有效增强大功率组件散热，提高大功率组件的效率，缩小大功率组件体积。采用本实用新型制作了一种功率驱动器，最大输出功率达到了3000瓦。

Description

MCM/D大功率组件
所属技术领域
本实用新型涉及多芯片组件(MCM)技术中一种薄膜多层布线技术(MCM/D)的实用化尤其是能应用在大功率领域中的MCM/D大功率组件。
背景技术
MCM(Multi-Chip Module)多芯片组件是一种高级的混合集成电路，目前MCM主要有三种类型。
MCM/L：采用高密度多层印刷电路板构成
MCM/C：采用高密度多层厚膜和高密度多层布线陶瓷基板制成
MCM/D：它是在Si、陶瓷基板或金属基板上，采用薄膜工艺形成高密度互联布线而构成。
要完成同等功能，这三种MCM中以MCM/D体积为最小，性能为最优，不足之处是不适合制作大功率组件。
表1是三种MCM有关参数的对比
表1三种MCM布线尺寸对比[1]
  MCM/C   MCM/D   MCM/L
  膜厚/μm   150～200   6   40
  最小孔同距/μm   225   15   180
  最小孔径/μm   100   10   102
  内部布线最小孔  径或线间距   450   50   127
  线宽   100   15   51
MCM/L受芯片的安装方式和所采用的基板材料与结构所限，布线密度不高，封装效率和性能较低。
MCM/C具有较高的布线层数、布线密度、封装效率，其性能优于MCM/L而低于MCM/D。
MCM/D布线宽度和线间距最小，具有更高的布线密度，更高的封装效率以及更好的传输特性。
功率型混合集成电路，在航天航空领域得到了广泛应用，功率型混合集成电路多采用厚膜混合集成技术研制，采用薄膜混合集成技术研制大功率组件尚未见报导。
发明内容
本实用新型采用薄膜多层布线制作MCM/D，与厚膜技术相结合，研制大功率组件。
大功率组件的研制首先要考虑的是增强散热和提高效率。
1、散热问题：在大功率组件中，散热是一个突出问题，如散热不好，将影响性能和可靠性。根据有关研究，在混合集成电路中，散热的主要途径是通过金属外壳的底座散发出去，据此，对大功率散热问题本实用新型的作法是将大功率管芯直接焊接在金属外壳的底座上，使大功率芯片产生的热量通过金属底座散发出去。很显然，功率芯片占据封装外壳底板面积越大，其散热能力就越强，由于受到整体封装面积的限制，或者是要进一步缩小功率组件的体积，要使功率芯片占有的面积增加，必须要尽量缩小大功率组件中非功率部分的体积。
2、提高效率问题：要提高功率组件的效率，最直接和最有效的办法是选用导通电阻低的功率器件。根据功率器件的特性，芯片面积越大其导通电阻越低，导通电阻低的功率器件必然要求占有大的有效面积。
综上所述，要研制体积小，性能优良，可靠性高的大功率组件，必须尽量缩小非功率部分的体积，扩大功率器件占有的有效面积。
本实用新型解决其技术问题采用的技术方案是：采用MCM/D薄膜多层布线技术制作非功率部分，以尽量缩小非功率部分占有面积，从而扩大功率部分面积。并且采用厚膜技术制作功率部分。非功率部分MCM/D基片采用Si基板，功率部分厚膜导线制作基片采用氧化铍陶瓷，大功率管芯焊接在氧化铍基板上，氧化铍基板焊接在金属封装外壳的底板上，以便将大功率管芯的热量通过氧化铍基板快速从金属外壳底板散发出去。
本实用新型的有益效果是：
1、非功率部分采用MCM/D制作，能最大限度地缩小非功率部分体积和占有面积，从而最大限度地扩大了功率管芯所能利用的金属封装外壳底板面积，以利于散热。
2、非功率部分采用MCM/D制作，充分发挥MCM/D精度高，稳定性好，温度特性好等优势，从而使非功率部分(如大功率驱动器的控制部分)提高精度，稳定可靠地工作，并以此提高整个功率组件的性能指标。
3、由于功率部分可占有的面积的扩大，为选用面积大，导通电阻小的功率管芯提供了条件，使选用功率管芯的面积能最大化，从而可大大提高功率组件的效率。
附图说明
下面结合附图和实施例对本实用新型进一步说明：
图1为本实用新型整体技术方案示意图
图2为内部结构纵剖面示意图
图1中：1.为大功率部分
2.为MCM/D
3.封装外壳底座底板
图2中：1.大功率管芯
2.为MCM/D
3.金属封装外壳底座
4.MCM/D上外贴管芯
5.内部互联线
具体实施方式
采用平底式金属封装外壳，外壳材料：10#钢
非功率部分：在Si基板上进行薄膜多布线制作MCM/D
功率部分：在氧化铍基板上，制作厚膜导线和焊盘，大功率管芯焊接在氧化铍基板上，非功率部分与外壳之间采用有机聚合物粘接。功率部分与外壳之间，大功率管芯与厚膜之间，采用共晶焊焊接。
内部互联和引出腿互联采用Si-Al丝键合工艺或金丝球焊工艺。
下面就MCM/D制作作进一步说明：
如前所述，薄膜多层布线技术制作的MCM/D是目前三种MCM(多芯片组件)(MCM/L、MCM/C、MCM/D)中组装密度最高，性能最好的，在大功率组件制作中，它能最大限度地缩小非功率部分的体积，因而在限定产品体积情况下，最大限度地增加功率部分的散热面积，所以采用MCM/D制作大功率组件的非功率部分是合理可行的。
本实用新型MCM/D部分，选用Si为基板，选用Ti/w-Cu-Ti/n-Au作导线的优势为：
常用基片和导体材料的有关性能见表2
表2[1]
  电阻率(μΩ/cm)   热胀系数(10-6/℃)   热导率(W/ink)
  Si   4.2   151
  Al2O3   7.3   20
  BeO   7.4   290
  Cu   1.67   16.5   393
  Au   2.2   14.2   297
  Al   4.3   23   240
  Ti-w   5.5   4.5   178
由表2可以看出，选用Si为基板其热导率比Al2O3优良，利于散热同时Si基板与半导体器件其热胀系数相同，非常匹配，这样可增加可靠性。
选用Ti/w-Cu-Ti/w-Au为复合导体，其中导电以Cu为主不但散热性能优良，电阻率也很低，同时Ti/w的热胀系数和Si的热胀系数也十分接近能很好匹配，Au作为复合导体的最上层，是一种理想的抗氧化导体，同时适合金丝球焊和超声键合。
功率部分采用厚膜技术制作：
该部分基板采用氧化铍，因氧化铍的散热系数大大优于氧化铝。利于大功率管芯的散热。
参考文献[1]杨邦朝、张经国多芯片组件(MCM/D)技术及其应用电子科技大学出版社2001.8制作实例：
采用本实用新型技术制作了一种大功率驱动器，驱动器的控制部分采用薄膜多层布线制作的MCM/D。
产品性能指标：
功率部分电源电压+VS  100V
控制部分电源电压+VCC 15V
  时钟输出   TTL电平，频率45KHz
  开关频率   22.5KHz
  三角波中心电压   5V
  三角波峰峰电压   4V
  输出连续电流   不小于30A
  时钟输出   TTL电平，频率45KHz
  输出峰值电流   不小于40A
  功能特性   具有过流和过热保护
  控制方式   PWM
  效率   ≥97％
  外形尺寸   58.65×41.40×6.8mm
MCM/D部分
  基板   Si
  层数   3
  导带   Ti/w-Cu-Ti/w-Au，方阻≤0.01Ω/口，  最小线宽70μm
  介质   P1
  最小通孔   40μm
该产品控制部分Vmax＝15V  Imax＝50mA
总功耗Pmax＝750mw，所以采用MCM/D制作是可行的合理的。
该产品限定体积下可利用的封装外壳底板面积为27.2×34＝924.8mm2。
采用MCM/D制作控制部分占底板面积为14×34＝476mm2，余下部分13.2×34＝488.8mm2即是封装外壳底板面积的一半多作为功率部分4支大功率管芯的直接散热面积，这对大功率管芯的散热是十分有利的。

Claims (1)

1.一种MCM/D大功率组件：其特征是大功率组件中非功率部分采用薄膜多层布线技术MCM/D制作，功率部分采用厚膜技术制作，大功率管芯通过氧化铍基板焊接在金属封装外壳底座底板上。
CN 200920109596 2009-07-03 2009-07-03 Mcm/d大功率组件 Expired - Lifetime CN201527965U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110666269A (zh) * 2019-10-11 2020-01-10 华东光电集成器件研究所 一种组合式共晶焊接装置及其使用方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110666269A (zh) * 2019-10-11 2020-01-10 华东光电集成器件研究所 一种组合式共晶焊接装置及其使用方法
CN110666269B (zh) * 2019-10-11 2021-06-25 华东光电集成器件研究所 一种组合式共晶焊接装置及其使用方法

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