CN201509182U - MOS efficient carrier digital amplifying circuit - Google Patents
MOS efficient carrier digital amplifying circuit Download PDFInfo
- Publication number
- CN201509182U CN201509182U CN200920131931XU CN200920131931U CN201509182U CN 201509182 U CN201509182 U CN 201509182U CN 200920131931X U CN200920131931X U CN 200920131931XU CN 200920131931 U CN200920131931 U CN 200920131931U CN 201509182 U CN201509182 U CN 201509182U
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- oxide
- signals
- output
- base stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The utility model provides an MOS efficient carrier digital amplifying circuit, which aims to amplify digital signals sufficiently, enables the output amplitude to close to the power level, realizes enough signal level output under the overload condition, and transmits carrier signals farther. The circuit includes an LC resonance circuit connected in series with a signal output terminal, and a carrier signal input terminal connected to a processor, wherein the falling edge of the carrier signals are output to a base electrode of a PNP triode, the PNP triode communicates and outputs rising signals, the rising signals triggers a N-channel MOS tube in forward direction through a DC-blocking first crosslink capacitor, and the N-channel MOS tube outputs low level to the LC resonance circuit; and the rising edge of the carrier signals are output to a base electrode of a NPN triode, the NPN triode communicates and outputs falling signals, the falling signals triggers a P-channel MOS tube in forward direction through a DC-blocking second crosslink capacitor, and the P-channel MOS tube outputs high level to the LC resonance circuit.
Description
Technical field
The utility model relates to a kind of digital signal power amplifier, particularly relates to a kind of digital signal power amplifier of power line carrier.
Background technology
ZAP is checked meter general day by day in the application of power industry, but owing to be subjected to the influence of the serious Harmonic Interference of electrical network, the development of ZAP is very limited, improving ZAP is the key subjects of pendulum before scientific and technical personnel, wherein make carrier module export enough signal levels under any loading condition, making carrier signal pass enough also is an important link far.
In existing patent documentation, be called " power amplifier of power line carrier communication ", be the patent on April 22nd, 2009 in open day as Chinese patent ZL 200820095250, name, this patent disclosure a kind of double power amplifier circuit of prime power amplifier and back level power amplifier structure that adopts solve power line carrier underpower problem.And this double power amplifier all adopts is the mode of the combination of a plurality of triodes, can have the problem of power output deficiency under some loading condition, and its anti-overload ability is limited.
Summary of the invention
Problem to be solved in the utility model is: the efficient carrier wave numeral of a kind of MOS power amplifier is provided, the purpose of this power amplifier is that digital signal is enough amplified, make output amplitude as far as possible near power level, be implemented in the enough signal levels of output under the overload condition, make carrier signal pass fartherly.
In order to solve the problems of the technologies described above, the utility model proposes the efficient carrier wave numeral of a kind of MOS power amplifier, comprise LC resonant circuit of connecting and the carrier signal input that is connected on the processor with signal output part, the trailing edge of described carrier signal is input to the base stage of PNP triode, make PNP triode conducting output rising signals, rising signals is through triggering N passage metal-oxide-semiconductor every the first straight crosslinked electric capacity forward, and N passage metal-oxide-semiconductor is to described LC resonant circuit output low level;
The rising edge of described carrier signal is input to the base stage of NPN triode, makes NPN triode conducting output dropping signal, and dropping signal is through triggering P passage metal-oxide-semiconductor every the second straight crosslinked electric capacity negative sense, and P passage metal-oxide-semiconductor is to described LC resonant circuit output high level.
Preferably: be in series with biasing resistor and current-limiting resistance on the base stage of described PNP triode.
Preferably: be in series with biasing resistor and current-limiting resistance on the base stage of described NPN triode.
Preferably: be in series with biasing resistor on the base stage of described N passage metal-oxide-semiconductor.
Preferably: be in series with biasing resistor on the base stage of described P passage metal-oxide-semiconductor.
The beneficial effects of the utility model are as follows:
Compared to existing technology, the performance that the utility model makes full use of the MOS circuit has well solved the problem of the signal level that output is enough under heavy load condition, and the digital signal of its output is enough amplified, and makes output amplitude more near power level.It has the delivery efficiency height, and the characteristics that anti-overload ability is strong can be transmitted carrier signal fartherly.
Figure of description
Fig. 1 is circuit theory diagrams of the present utility model.
Fig. 2 is the partial circuit diagram of the interior A of bold box among Fig. 1.
Embodiment
The utility model provides the efficient carrier wave numeral of a kind of MOS power amplifier.Circuit theory is referring to Fig. 1 and Fig. 2.
This circuit comprises the LC resonant circuit of connecting with signal output part and is connected to carrier signal input J0 on the processor, and the 17th of J0 and processor CY100 is connected with the 18th pin.
Carrier signal input J0 parallel connection is every the first capacitance C15 and the second capacitance C7 of straight usefulness.The first capacitance C15, the first current-limiting resistance R9 that connects is connected on the base stage of PNP triode Q1, and the base stage of PNP triode Q1 is connected on the 12V power supply, and is in series with one first biasing resistor R6.The emitter of PNP triode Q1 is connected with the 12V power supply, its collector electrode is connected with the first crosslinked capacitor C 3, be connected on the input of N passage metal-oxide-semiconductor Q3, the output of N passage metal-oxide-semiconductor Q3 is connected on the LC resonant circuit and resonance capacitor C 1 of all connecting with signal output part.The input of N passage metal-oxide-semiconductor Q3 also is connected with the 3rd biasing resistor R3, and the 3rd biasing resistor R3 is ground connection again, another input end grounding of N passage metal-oxide-semiconductor Q3.N passage metal-oxide-semiconductor Q3 is the metal-oxide-semiconductor that forward triggers.
The second capacitance C7, the second current-limiting resistance R4 that connects, be connected on the base stage of NPN triode Q2, the base stage of the NPN triode Q2 ground connection behind the second biasing resistor R2 of connecting, its grounded emitter, after its collector series connection second crosslinked capacitor C 2, input (collector electrode) with P passage metal-oxide-semiconductor Q4 is connected again, and this input is serially connected with the 4th a biasing resistor R1 who is connected with the 12V power supply simultaneously.Another input of P passage metal-oxide-semiconductor Q4 connects the 12V power supply.The output of P passage metal-oxide-semiconductor Q4 connects the resonant capacitance C1 of the LC resonant circuit of connecting with signal output part.P passage metal-oxide-semiconductor Q4 is the metal-oxide-semiconductor that negative sense triggers.
PNP triode Q1 and NPN triode Q2 are integrated in the IC2.N passage metal-oxide-semiconductor Q3 and P passage metal-oxide-semiconductor Q4 are integrated in the IC1.
Principle of the present utility model is as described below:
Base stage from the next carrier signal trailing edge PNP triode Q1 through the first capacitance C15 and first current-limiting resistance R9 arrival IC2 of processor CY100 the 17th, 18 pin, make its conducting obtain the rising signals of 12V, the forward that triggers two metal-oxide-semiconductor IC1 through the first crosslinked capacitor C 3 triggers the 2nd pin makes 8 pin drop to 0V rapidly.
The base stage of the carrier wave rising edge that processor CY100 the 17th, 18 pin come NPN triode Q2 in the second capacitance C7, second current-limiting resistance R4 arrival IC2, make its conducting obtain dropping signal, the negative sense that triggers metal-oxide-semiconductor IC1 through the second crosslinked capacitor C 2 triggers the 4th pin makes 5 pin obtain 12V voltage rapidly.Thereby make resonant capacitance C1 obtain the power digital level of 0～12V, metal-oxide-semiconductor has extremely strong overcurrent capability, moment can reach 20A, because motional impedance was the milliohm level when metal-oxide-semiconductor road was logical, even pressure drop is also very little under big current conditions, the power consumption of self is very little, so be well suited for using in this occasion.
More than the summary as can be seen, the carrier signal of 0～5V that processor CY100 produces is enlarged into 0～12V to pipe through IC2 signal in order to drive IC 1 MOS to pipe, make its power that produces 0～12V output, the effect of the second crosslinked capacitor C 2 and the first crosslinked capacitor C 3 is every directly, makes MOS be in cut-off state to pipe under quiescent conditions and raises the efficiency.The effect of the 4th biasing resistor R1 and the 3rd biasing resistor R3 provides the bias voltage that IC1 ends.
The resonant circuit of the lc circuit organization center frequency 45KHz that the inductance (not having picture among the figure) of one 60 microhenry of resonant capacitance C1 serial connection is formed is loaded into carrier signal on the coupling transformer, enters electrical network by the coupling transformer carrier signal.The characteristics of the series resonant circuit that LC forms are in the reactance of resonance point approaching zero, reach the effect of frequency-selecting simultaneously, digital waveform is changed into quasi-sine-wave, because the little adaptive capacity to load of internal resistance very strong (its equivalent electric circuit is a constant pressure source), and the capacitive inductive load of circuit can be very not big to the distortion of signal.
Present embodiment is the carrier wave drive circuit of a 45KHz, and the parameter that changes LC can be suitable for the carrier wave of different frequent points.
Claims (5)
1. the efficient carrier wave numeral of MOS power amplifier comprises the LC resonant circuit of connect with signal output part and is connected to carrier signal input on the processor, it is characterized in that:
The trailing edge of described carrier signal is input to the base stage of PNP triode (Q1), make PNP triode (Q1) conducting output rising signals, rising signals is through triggering N passage metal-oxide-semiconductor (Q3) every first straight crosslinked electric capacity (C3) forward, and N passage metal-oxide-semiconductor (Q3) is to described LC resonant circuit output low level;
The rising edge of described carrier signal is input to the base stage of NPN triode (Q2), make NPN triode (Q2) conducting output dropping signal, dropping signal is through triggering P passage metal-oxide-semiconductor (Q4) every second straight crosslinked electric capacity (C2) negative sense, and P passage metal-oxide-semiconductor (Q4) is to described LC resonant circuit output high level.
2. the efficient carrier wave numeral of MOS according to claim 1 power amplifier is characterized in that: be in series with biasing resistor and current-limiting resistance on the base stage of described PNP triode (Q1).
3. the efficient carrier wave numeral of MOS according to claim 1 power amplifier is characterized in that: be in series with biasing resistor and current-limiting resistance on the base stage of described NPN triode (Q2).
4. the efficient carrier wave numeral of MOS according to claim 1 power amplifier is characterized in that: be in series with biasing resistor on the base stage of described N passage metal-oxide-semiconductor (Q3).
5. the efficient carrier wave numeral of MOS according to claim 1 power amplifier is characterized in that: be in series with biasing resistor on the base stage of described P passage metal-oxide-semiconductor (Q4).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200920131931XU CN201509182U (en) | 2009-05-19 | 2009-05-19 | MOS efficient carrier digital amplifying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200920131931XU CN201509182U (en) | 2009-05-19 | 2009-05-19 | MOS efficient carrier digital amplifying circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201509182U true CN201509182U (en) | 2010-06-16 |
Family
ID=42470303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200920131931XU Expired - Fee Related CN201509182U (en) | 2009-05-19 | 2009-05-19 | MOS efficient carrier digital amplifying circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201509182U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158258A (en) * | 2011-04-27 | 2011-08-17 | 钜泉光电科技(上海)股份有限公司 | Circuit and method for sending power line carrier (PLC) signals |
-
2009
- 2009-05-19 CN CN200920131931XU patent/CN201509182U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158258A (en) * | 2011-04-27 | 2011-08-17 | 钜泉光电科技(上海)股份有限公司 | Circuit and method for sending power line carrier (PLC) signals |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101888213A (en) | Push-pull radio-frequency power amplifier with improved linearity and efficiency | |
| CN110212868A (en) | A kind of power amplifier based on comb filtering | |
| CN101752786A (en) | Laser driving method for laser | |
| CN201509182U (en) | MOS efficient carrier digital amplifying circuit | |
| CN109167579A (en) | A kind of efficient power amplifier of high-output power | |
| CN100559706C (en) | Radio-frequency differential-to-single-ended converter | |
| CN201903573U (en) | Current detection and amplification circuit used for two-wire manufactured instrument | |
| CN201726371U (en) | Push-pull type radio-frequency power amplifier with improved linearity and efficiency | |
| CN102347744A (en) | Audio signal generator made of single transistor | |
| CN201726372U (en) | Push-pull type radio-frequency power amplifier with improved linearity | |
| CN205430183U (en) | Intercom audio power amplifier circuit | |
| CN201606059U (en) | Power supply circuit of microsphere focused logging main current | |
| CN208820750U (en) | Broadband low-noise amplifier applied to X wave band | |
| CN201854182U (en) | Voltage source of relay protection test instrument | |
| CN204697017U (en) | A kind of intercom audio amplifier circuit | |
| CN101552594B (en) | High-fidelity power amplifying circuit in power supply regenerator | |
| CN202385067U (en) | Low frequency signal generating device | |
| CN108173588A (en) | A kind of wireless electronic communication signal amplifier | |
| CN203761465U (en) | High frequency video signal compensating circuit | |
| CN204633718U (en) | Power amplifier device | |
| CN221151321U (en) | Radio frequency power amplifying circuit and wireless communication device | |
| CN203206450U (en) | Stereo hi-fi transistor push-pull sound amplifier | |
| CN206135835U (en) | Little signal amplifier module of preceding stage FET input high impedance | |
| CN217849385U (en) | High-temperature-resistant precise hybrid integrated amplification circuit | |
| CN201606057U (en) | Thick film circuit of microsphere focused logging main current circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHENZHEN JIUMAO SANSHUI TECHNOLOGY DEVELOPMENT CO. Free format text: FORMER OWNER: SHENZHEN JIUMAO SANSHUI ELECTRIC CO., LTD. Effective date: 20101027 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 518000 509, COMPLEX BUILDING, CHINA ACADEMY OF SCIENCE AND TECHNOLOGY DEVELOPMENT, GAOXIN SOUTH ROAD 1, SOUTH ZONE OF SCI-TECH. PARK, NANSHAN DISTRICT, SHENZHEN CITY, GUANGDONG PROVINCE TO: 518000 WEST TOWER, 4/F, BUILDING 7, GAOFA SCI-TECH. PARK, LONGJING EAST ROAD, NANSHAN DISTRICT, SHENZHEN CITY, GUANGDONG PROVINCE |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20101027 Address after: 518000, West building, four floor, high tech park, Longjing East Road, Shenzhen, Nanshan District, Guangdong seven, China Patentee after: Shenzhen nine Sanshui Sanshui science and Technology Development Co., Ltd. Address before: 518000 Guangdong city of Shenzhen province Nanshan District science and Technology Park high-tech South Road China Technology Development Institute building 509 Patentee before: Shenzhen Jiumao Sanshui Electric Co., Ltd. |
|
| DD01 | Delivery of document by public notice |
Addressee: Shenzhen nine Sanshui Sanshui science and Technology Development Co., Ltd. Document name: Notification to Pay the Fees |
|
| DD01 | Delivery of document by public notice |
Addressee: Shenzhen nine Sanshui Sanshui science and Technology Development Co., Ltd. Document name: Notification of Termination of Patent Right |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100616 Termination date: 20140519 |
|
| EXPY | Termination of patent right or utility model |