CN201508834U - Double flat pin-free encapsulating part - Google Patents

Double flat pin-free encapsulating part Download PDF

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Publication number
CN201508834U
CN201508834U CN2009201442070U CN200920144207U CN201508834U CN 201508834 U CN201508834 U CN 201508834U CN 2009201442070 U CN2009201442070 U CN 2009201442070U CN 200920144207 U CN200920144207 U CN 200920144207U CN 201508834 U CN201508834 U CN 201508834U
Authority
CN
China
Prior art keywords
carrier
plastic
sealed body
pit
plastic sealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2009201442070U
Other languages
Chinese (zh)
Inventor
郭小伟
慕蔚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xi'an TianSheng Electronics Co., Ltd.
Original Assignee
Tianshui Huatian Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tianshui Huatian Technology Co Ltd filed Critical Tianshui Huatian Technology Co Ltd
Priority to CN2009201442070U priority Critical patent/CN201508834U/en
Application granted granted Critical
Publication of CN201508834U publication Critical patent/CN201508834U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model relates to a double flat pin-free encapsulating part. An encapsulating carrier has two types like single-carrier encapsulation and double-carrier encapsulation. A plastic sealing body comprises an upper plastic sealing body and a lower plastic sealing body; and the upper plastic sealing body and the lower plastic sealing body surround and encapsulate the carrier from the upper surface and the lower surface without exposure. The upper plastic sealing body surrounds the upper surface and the lateral surface of the carrier, bonding materials, an IC chip, a gold bonding wire, the upper surface of an inner pin and a groove between the carrier; and the lower plastic sealing body surrounds a pit on the lower surface of the carrier, a pit at the lower end of the inner pin and the lower lateral surface of the carrier. The double flat pin-free encapsulating part is characterized in that the carrier is reduced, so that not only can the cost of plastic sealing materials be remarkably saved, and but also can the thin and miniature encapsulation of portable products be achieved. Two surfaces of the carrier are encapsulated without exposure, so that hidden troubles of warpage and easy generation of a separation layer are overcome, and the problem that the flash of the carrier can not be cleanly removed is solved. The upper plastic sealing body and the lower plastic sealing body play a role in reducing the warpage.

Description

A kind of packaging part with double flat surfaces and no pins
Technical field
The utility model relates to electronic information Element of automatic control manufacturing technology field, refers more particularly to packaging part with double flat surfaces and no pins.
Background technology
In recent years, the portable e-machine market in mobile communication and mobile computer field is fiery, has directly promoted the development of compact package and high density packaging technique; Simultaneously, also a series of strict demands have been proposed the compact package technology, such as, require the packaging appearance size to dwindle (especially packaging height is less than 1mm) as far as possible.Connection reliability after the encapsulation improves as far as possible, adapted to leadless welding (protection environment) and try hard to reduce cost.
DFN (Dual Flat No Package) type integrated circuit encapsulation technology is a kind of novel small shape encapsulation technology that grew up in recent years, is one of state-of-the-art surface mount encapsulation technology.Because no pin, to mount occupied area little, characteristics such as setting height(from bottom) is low, for satisfying the portable e-machine in mobile communication and mobile computer field, use and a kind of novel encapsulated technology living and that shoot up as the needs of ultrathin electronic product development such as PDA, mobile phone, MP3, MP4.Present packaging part with double flat surfaces and no pins, carrier exposes, plastic packaging material is only sealed the upper surface and the side of IC chip, bonding line, carrier lower surface one circle and the pin of carrier upper surface, belong to the single face encapsulation, be easy to generate warpage, correct by back curing mold pressurization, still exist to produce warpage and absciss layer hidden danger, and have carrier back side flash to remove sordid phenomenon.Simultaneously, existing DFN general thickness is controlled at 0.82mm～1.0mm, does not satisfy the needs of ultrathin encapsulating products.
Summary of the invention
The purpose of this utility model is exactly a warpage when encapsulating plastic packaging at present common double flat non-pin encapsulation (DFN) single face, exist the hidden danger and the carrier back side flash that produce absciss layer to remove phenomenons such as unclean, the packaging part with double flat surfaces and no pins that provides a kind of carrier not expose, and slim DFN of a kind of 0.75mm (TDFN) and ultrathin DFN (UDFN) method for packing of 0.50mm are provided.
The purpose of this utility model is achieved through the following technical solutions:
A kind of packaging part with double flat surfaces and no pins comprises pad, bonding line, frame inner pin and plastic-sealed body on lead frame carrier, bonding die glue, IC chip, the IC chip.Described package carrier is provided with single carrier package, and the carrier lower surface is provided with pit; Described plastic-sealed body comprises plastic-sealed body and following plastic-sealed body; Last plastic-sealed body and following plastic-sealed body from upper and lower two-sided encirclement encapsulation, do not expose carrier.
Described package carrier is provided with two carrier package; Described plastic-sealed body comprises plastic-sealed body and following plastic-sealed body; Last plastic-sealed body and following plastic-sealed body from upper and lower two-sided encirclement encapsulation, do not expose carrier.
Each carrier lower surface of described pair of carrier is provided with pit, establishes a rib between two pits.
The upper surface of described upward plastic-sealed body encirclement lead frame carrier and side, adhesives, IC chip, bonding line, the upper surface of interior pin, the groove between carrier; Described plastic-sealed body down surrounds the pit of carrier lower surface, the pit of interior pin lower end, the downside of carrier; Upper and lower plastic-sealed body is together with the integral body of besieged part forming circuit.
Characteristics of the present utility model are that carrier dwindles, and it is remarkable not only to save the plastic packaging material cost, and can realize portable product slim (1.0mm is following), miniaturization encapsulation.The carrier double-faced packaging does not expose, and has overcome warpage and the easy hidden danger that produces absciss layer, has solved the carrier flash and has removed clean problem.Plastic-sealed body plays the effect that reduces or alleviate angularity up and down.
Description of drawings
Fig. 1 is the utility model list vector product cutaway view;
Fig. 2 is the two vector product cutaway views of the utility model;
Fig. 3 is the two vector product figure back views of the utility model.
Embodiment
Below in conjunction with accompanying drawing this utility model is elaborated:
A kind of packaging part with double flat surfaces and no pins comprises pad, bonding line, frame inner pin and plastic-sealed body on lead frame carrier, bonding die glue, IC chip, the IC chip.Package carrier of the present invention is provided with single carrier package, or two kinds of forms of two carrier package.Carrier 1 lower surface of single carrier package is provided with pit 9; Described plastic-sealed body comprises plastic-sealed body 8 and following plastic-sealed body 15, and carrier from upper and lower two-sided encirclement encapsulation, is not exposed.
By bonding die glue 3 bonding IC chips 4, the pad on the IC chip 4 links to each other the electric current of forming circuit and signalling channel by bonding line 6 with the interior pin 5 of lead frame to single carrier package by lead frame carrier 1.Bonding die glue 3 can be conducting resinl or conductive adhesive film, insulating cement or insulation glued membrane.Last plastic-sealed body 8 surrounds IC chip 4, the side of bonding die glue 3, the upper surface of lead frame carrier 1, the upper surface of lead pin 5 and the bonding line 6 of pad on the IC chip 4 and lead pin 5 upper surfaces; Following plastic-sealed body 13 surrounds the pit 9 of carrier 1 lower surface and the groove 7 of side and lead pin 5 bottom surfaces.Last plastic-sealed body 8 and following plastic-sealed body 15 and encirclement part thereof have constituted the integral body of circuit.
Two carrier package are provided with carrier 1, carrier 2 encapsulation; Carrier 1 lower surface is provided with pit 9, and carrier 2 lower surfaces are provided with pit 13, establishes a rib 14 between the pit 9 and 13, and rib 14 is cut line 16 and cuts when cutting, and carrier 1 and carrier 2 are separated.Plastic-sealed body comprises plastic-sealed body 8 and following plastic-sealed body 15; Last plastic-sealed body 8 and following plastic-sealed body 15 from upper and lower two-sided encirclement encapsulation, do not expose carrier.
Two carrier package are passed through bonding die glue 3 and bonding die glue 10 bonding IC chip 4 and IC chips 11 by lead frame carrier 1 and carrier 2, IC chip 4 links to each other the electric current of forming circuit and signalling channel by bonding line 6 with the interior pin 5 of lead frame with pad on the IC chip 11.Last plastic-sealed body 8 surrounds upper surface, the upper surface of lead pin 5 and the bonding line 6 of pad on IC chip 4 and the IC chip 11 and lead pin 5 upper surfaces of side, lead frame carrier 1 and the carrier 2 of IC chip 4 and IC chip 11, bonding die glue 3 and bonding die glue 10; The lower surface pit 13 and the side thereof of the pit 9 of the lower surface of following plastic-sealed body 13 encirclement carriers and side, carrier 2, and the groove 7 of lead pin 5 bottom surfaces, the groove 12 between carrier 1 and the carrier 2.Last plastic-sealed body 8 and following plastic-sealed body 15 and the integral body of surrounding the part forming circuit thereof.
The effect of plastic-sealed body is that IC chip and bonding line are played the effect of protecting and supporting.And last plastic-sealed body 8 and following plastic-sealed body 13 play and reduce the effect of plastic packaging angularity, the groove 7 of interior pin 5 bottom surfaces and other pit, groove have increased the adhesion of plastic packaging material and framework, play anti-absciss layer effect, avoided common Q FN carrier back side flash to remove sordid problem simultaneously.Connect together before two carriers 1 and 2 cutting and separating, earlier rib 14 cutting and separating of 2 in carrier 1 and carrier are opened during cutting and separating, guarantee not short circuit.

Claims (5)

1. packaging part with double flat surfaces and no pins, comprise pad, bonding line, frame inner pin and plastic-sealed body on lead frame carrier, bonding die glue, IC chip, the IC chip, it is characterized in that: described package carrier is provided with single carrier (1) encapsulation, and carrier (1) lower surface is provided with pit (9); Described plastic-sealed body comprises plastic-sealed body (8) and following plastic-sealed body (15); Last plastic-sealed body (8) and following plastic-sealed body (15) from upper and lower two-sided encirclement encapsulation, do not expose carrier.
2. a kind of packaging part with double flat surfaces and no pins according to claim 1 is characterized in that the described upper surface that plastic-sealed body (8) surrounds the upper surface of lead frame carrier (1) and side, adhesives (3), IC chip (4), bonding line (6), interior pin (5) of going up; Described plastic-sealed body (15) down surrounds the pit (9) of carrier (1) lower surface, the pit (7) of interior pin (5) lower end, the downside of carrier (1); Upper and lower plastic-sealed body is together with the integral body of besieged part forming circuit.
3. a packaging part with double flat surfaces and no pins comprises pad, bonding line, frame inner pin and plastic-sealed body on lead frame carrier, bonding die glue, IC chip, the IC chip, it is characterized in that: described package carrier is provided with two carriers (1), (2) encapsulation; Described plastic-sealed body comprises plastic-sealed body (8) and following plastic-sealed body (15); Last plastic-sealed body (8) and following plastic-sealed body (15) from upper and lower two-sided encirclement encapsulation, do not expose carrier.
4. a kind of packaging part with double flat surfaces and no pins according to claim 3 is characterized in that carrier (1) lower surface of described pair of carrier is provided with pit (9), and carrier (2) lower surface is provided with pit (13), establishes a rib (14) between pit (9) and (13).
5. a kind of packaging part with double flat surfaces and no pins according to claim 3 is characterized in that the described groove of going up between upper surface, carrier (1) and the carrier (2) that plastic-sealed body (8) surrounds the upper surface of lead frame carrier (1) and carrier (2) and side, adhesives (3) and (10), IC chip (4) and (11), bonding line (6), interior pin (5) (12); The pit (9) of the described encirclement of plastic-sealed body (15) down carrier (1) lower surface and the pit (13) of carrier (2) lower surface, the pit (7) of interior pin (5) lower end, the downside of carrier (1) and carrier (2); Upper and lower plastic-sealed body is together with the integral body of besieged part forming circuit.
CN2009201442070U 2009-10-17 2009-10-17 Double flat pin-free encapsulating part Expired - Fee Related CN201508834U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2009201442070U CN201508834U (en) 2009-10-17 2009-10-17 Double flat pin-free encapsulating part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2009201442070U CN201508834U (en) 2009-10-17 2009-10-17 Double flat pin-free encapsulating part

Publications (1)

Publication Number Publication Date
CN201508834U true CN201508834U (en) 2010-06-16

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Application Number Title Priority Date Filing Date
CN2009201442070U Expired - Fee Related CN201508834U (en) 2009-10-17 2009-10-17 Double flat pin-free encapsulating part

Country Status (1)

Country Link
CN (1) CN201508834U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102263077A (en) * 2011-06-13 2011-11-30 西安天胜电子有限公司 Double flat carrier-free pin-free IC chip packaging part

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102263077A (en) * 2011-06-13 2011-11-30 西安天胜电子有限公司 Double flat carrier-free pin-free IC chip packaging part

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C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: XI AN TIANSHENG ELECTRONICS CO., LTD.

Free format text: FORMER OWNER: HUATIAN SCIENCE + TECHNOLOGY CO., LTD., TIANSHUI

Effective date: 20100921

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 741000 TO: 710018

TR01 Transfer of patent right

Effective date of registration: 20100921

Address after: 710018 west section of Fengcheng six road, Xi'an economic and Technological Development Zone, Shaanxi

Patentee after: Xi'an TianSheng Electronics Co., Ltd.

Address before: 741000 Gansu province Tianshui District Shuangqiao Road No. 14

Patentee before: Huatian Science & Technology Co., Ltd., Tianshui

DD01 Delivery of document by public notice

Addressee: Liu Guanghui

Document name: Notification of Passing Examination on Formalities

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100616

Termination date: 20121017