CN201490910U - Parallel-connected clamping reverse excitation circuit - Google Patents
Parallel-connected clamping reverse excitation circuit Download PDFInfo
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- CN201490910U CN201490910U CN2009202048353U CN200920204835U CN201490910U CN 201490910 U CN201490910 U CN 201490910U CN 2009202048353 U CN2009202048353 U CN 2009202048353U CN 200920204835 U CN200920204835 U CN 200920204835U CN 201490910 U CN201490910 U CN 201490910U
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Abstract
The utility model relates to a parallel-connected clamping reverse excitation circuit which comprises two field-effect tubes, a PWM (pulse-width modulation) control chip, two transformers, two diodes and two input capacitors, wherein the two input capacitors are connected in series and divides input voltage into Vin/2; a common terminal of the two transformers is connected to the half position of the input voltage; the two field-effect tubes are connected with the PWM control chip and the two transformers; the negative pole of the first diode is connected with the first field-effect tube and the positive pole thereof is connected with the negative terminal of the input voltage; and the negative pole of the second diode is connected with the positive terminal of the input voltage and the negative pole thereof is connected with the second field-effect tube. During use, when the two field-effect tubes are shut off, energy of leakage inductance on the edges of the transformers are completely fed back to the two input capacitors with no loss, and in addition, clampings on the edges of the transformers are reset in the position of Vin/2 voltage through the two input capacitors, therefore, an RCD reset unit in an original circuit is dispensed with, the power volume is reduced, and furthermore, the loss is reduced and the conversion efficiency is improved.
Description
Technical field
The utility model relates to a kind of circuit of reversed excitation, especially a kind of power supply clamper circuit of reversed excitation in parallel.
Background technology
Please refer to as shown in Figure 1, be the anti-circuit common that swashs in parallel in the prior art.The RCD reset circuit has all been inserted on each limit, transformer source, when the Q1 conducting, and limit, transformer T1 source storage power, T2 transfers energy to secondary, and at this moment, diode D2 positively biased provides energy to load, by RCD transformer is resetted simultaneously; When the Q2 conducting, limit, transformer T2 source storage power, because Q1 turn-offs, the counter-rotating of limit, T1 transformer source winding polarity, the conducting of secondary diode D1 positively biased is discharged into output loading with the energy on limit, source, resets simultaneously to the output capacitance charging, and by RCD.
Because of turn-offing when metal-oxide-semiconductor, when limit, transformer source transfers energy to secondary, the limit, source resets by RCD, the energy of limit, transformer source leakage inductance all consumes on resistance, causes conversion efficiency low, simultaneously, also need an electric capacity that clamper is carried out on limit, transformer source, to avoid leakage inductance energy excessive, produce excessive voltage stress, may cause the damage of metal-oxide-semiconductor.
The utility model content
The technical problems to be solved in the utility model is, may produce the low defective of conversion efficiency at prior art, and a kind of circuit that can improve conversion efficiency is provided.
For achieving the above object, the technical scheme that the utility model adopted is:
Clamper circuit of reversed excitation in parallel, it includes two field effect transistor, pwm chip, two transformers and two diodes, wherein: it also further comprises two input capacitances, described two input capacitances are connected and input voltage are divided into Vin/2, the common port of described two transformers is connected to the input voltage place of half, two field effect transistor link to each other with pwm chip and two transformers, the negative pole of first diode links to each other with first field effect transistor, and positive pole links to each other with the negative terminal of input voltage; The negative pole of second diode links to each other with the anode of input voltage, and positive pole links to each other with second field effect transistor.
Preferably, two above-mentioned field effect transistor are N channel-type metal oxide semiconductor field effect tube, and the grid of described field effect transistor links to each other with described pwm chip.
Preferably, two above-mentioned transformers connected in parallel, when making one of them transformer energy storage, the leakage inductance of another transformer turns back in the power supply goes, and carries out magnetic reset simultaneously.
The other end of the first above-mentioned transformer is connected to the anode of input voltage by first field effect transistor; The other end of described second transformer is connected to the negative terminal of input voltage by second field effect transistor.
The other end of the first above-mentioned transformer links to each other with the source electrode of described first field effect transistor.
The other end of the second above-mentioned transformer links to each other with the drain electrode of described second field effect transistor.
Above-mentioned pwm chip is the voltage-type control chip.
Above-mentioned pwm chip is the current-mode control chip.
Above-mentioned two pulse-width signals of PWM voltage-type control chip output are connected to two field effect transistor by former limit drive circuit, allow limit, transformer source clamper in the input voltage of half.
Above-mentioned two pulse-width signals of PWM current-mode control chip output are connected to two field effect transistor by former limit drive circuit, allow limit, transformer source clamper in the input voltage of half.
After adopting technique scheme, in use, when the field effect pipe turn-offed, energy all fed back in the input capacitance and goes in the leakage inductance on limit, transformer source, does not form loss, by input capacitance limit, transformer source clamper is resetted at the voltage place of Vin/2 in addition, save the RCD reset unit in the original circuit, reduced the volume of power supply, simultaneously, reduce loss, improved conversion efficiency.
Description of drawings
Fig. 1 is a circuit of reversed excitation in parallel in the prior art;
Fig. 2 is a kind of clamper circuit of reversed excitation schematic diagram in parallel of the utility model;
Fig. 3 is a working timing figure of the present utility model.
Embodiment
The utility model is described in further detail below in conjunction with drawings and Examples.
As shown in Figure 2, it is circuit theory diagrams of the present utility model, comprises two field effect transistor Q1, Q2, pwm chip, two transformer T1, T2, two input capacitance C1, C2 and two diode D3, D4, wherein:
Two field effect transistor Q1, Q2 are N channel-type metal oxide semiconductor field effect tube, the grid of described field effect transistor Q1, Q2 is connected to pwm chip, the source electrode of field effect transistor Q1 links to each other with the negative pole of diode D3, and the positive pole of diode D3 links to each other with the negative terminal of input voltage; The drain electrode of field effect transistor Q2 links to each other with the positive pole of diode D4, and the negative pole of diode D4 links to each other with the anode of input voltage.
Pwm chip is voltage-type control chip or current-mode control chip, and in the present embodiment, it is the voltage-type control chip.
Two input capacitance C1, C2 series connection also is divided into Vin/2 with input voltage.
Two transformer T1, T2 parallel connection, common port is connected to the input voltage place of half, and the other end of T1 links to each other with the source electrode of Q1, and the other end of T2 links to each other with the drain electrode of Q2, and the other end of T1 links to each other with the source electrode of field effect transistor Q1, and the drain electrode of field effect transistor Q1 links to each other with the anode of input voltage; The other end of T2 links to each other with the drain electrode of field effect transistor Q2, and the source electrode of field effect transistor Q2 links to each other with the negative terminal of input voltage.
When Q1 is open-minded, when Q2 turn-offed, capacitor C 1 was given limit, the source intake of transformer T1, simultaneously, since the shutoff of Q2, the limit polarity inversion of transformer T2 source, energy delivery is to secondary, the diode D2 of secondary is subjected to forward bias and conducting, powering load, and the energy in the leakage inductance on capacitor C 0 charging limit, T2 source is by diode D4 simultaneously, to capacitor C 1 charging, and the voltage at two ends, limit, T2 source, clamper resets at Vdc/2 voltage place.
When the Q1 shutoff, when Q2 did not also open, the counter-rotating of T1 polarity of transformer was coupled to secondary with energy, and diode D1 is subjected to forward bias and conducting, when load provides energy, also gave output capacitance C0 charging.
When Q1 turn-offs, when Q2 opened, the T1 transformer energy was coupled to secondary, and the energy in the leakage inductance of former limit can't be coupled to secondary, and it gives capacitor C 2 chargings through C2, D3 loop, and with limit, T1 transformer source clamper at Vdc/2 voltage place, reset; Because Q2's is open-minded, limit, transformer T2 source begins storage power, and diode D2 is subjected to reverse bias to ending.
When the Q1 shutoff, when Q2 turn-offed, the counter-rotating of T2 polarity of transformer was coupled to secondary with energy, and diode D2 is subjected to forward bias and conducting, when load provides energy, also gave output capacitance C0 charging.
Cooperate shown in Figure 3, when the field effect pipe turn-offs, energy all feeds back in the input capacitance and goes in the leakage inductance on limit, transformer source, do not form loss, by input capacitance C1, C2 limit, transformer source clamper is resetted at the voltage place of Vin/2 in addition, saved the RCD reset unit in the original circuit, reduced the volume of power supply, simultaneously, reduce loss, improved conversion efficiency.
The above; it only is the preferable embodiment of the utility model; but protection range of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; the variation that can expect easily or replacement all should be encompassed within the protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion with the protection range of claim.
Claims (10)
1. clamper circuit of reversed excitation in parallel, it includes two field effect transistor, pwm chip, two transformers and two diodes, it is characterized in that: it also further comprises two input capacitances, described two input capacitances are connected and input voltage are divided into Vin/2, the common port of described two transformers is connected to the input voltage place of half, two field effect transistor link to each other with pwm chip and two transformers, the negative pole of first diode links to each other with first field effect transistor, and positive pole links to each other with the negative terminal of input voltage; The negative pole of second diode links to each other with the anode of input voltage, and positive pole links to each other with second field effect transistor.
2. clamper circuit of reversed excitation in parallel as claimed in claim 1 is characterized in that: described two field effect transistor are N channel-type metal oxide semiconductor field effect tube, and the grid of described field effect transistor links to each other with described pwm chip.
3. clamper circuit of reversed excitation in parallel as claimed in claim 1 or 2 is characterized in that: described two transformers connected in parallel, when making one of them transformer energy storage, the leakage inductance of another transformer turns back in the power supply goes, and carries out magnetic reset simultaneously.
4. clamper circuit of reversed excitation in parallel as claimed in claim 1 or 2 is characterized in that: the other end of described first transformer is connected to the anode of input voltage by first field effect transistor; The other end of described second transformer is connected to the negative terminal of input voltage by second field effect transistor.
5. clamper circuit of reversed excitation in parallel as claimed in claim 4 is characterized in that: the other end of described first transformer links to each other with the source electrode of described first field effect transistor.
6. clamper circuit of reversed excitation in parallel as claimed in claim 4 is characterized in that: the other end of described second transformer links to each other with the drain electrode of described second field effect transistor.
7. clamper circuit of reversed excitation in parallel as claimed in claim 1 or 2 is characterized in that: described pwm chip is the voltage-type control chip.
8. clamper circuit of reversed excitation in parallel as claimed in claim 1 or 2 is characterized in that: described pwm chip is the current-mode control chip.
9. clamper circuit of reversed excitation in parallel as claimed in claim 1 or 2, it is characterized in that: two pulse-width signals of described PWM voltage-type control chip output, be connected to two field effect transistor by former limit drive circuit, allow limit, transformer source clamper in the input voltage of half.
10. clamper circuit of reversed excitation in parallel as claimed in claim 1 or 2, it is characterized in that: two pulse-width signals of described PWM current-mode control chip output, be connected to two field effect transistor by former limit drive circuit, allow limit, transformer source clamper in the input voltage of half.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202048353U CN201490910U (en) | 2009-09-09 | 2009-09-09 | Parallel-connected clamping reverse excitation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202048353U CN201490910U (en) | 2009-09-09 | 2009-09-09 | Parallel-connected clamping reverse excitation circuit |
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| Publication Number | Publication Date |
|---|---|
| CN201490910U true CN201490910U (en) | 2010-05-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009202048353U Expired - Fee Related CN201490910U (en) | 2009-09-09 | 2009-09-09 | Parallel-connected clamping reverse excitation circuit |
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| CN (1) | CN201490910U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151941A (en) * | 2013-03-26 | 2013-06-12 | 王彤 | Counter excitation type power superposition circuit |
| CN103548249A (en) * | 2011-05-25 | 2014-01-29 | 邦及奥卢夫森公司 | Power supply arrangement for single ended class d amplifier |
| CN103762834A (en) * | 2013-12-31 | 2014-04-30 | 江苏嘉钰新能源技术有限公司 | Auxiliary power supply of three-phase three-level VIENNA rectifier |
-
2009
- 2009-09-09 CN CN2009202048353U patent/CN201490910U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103548249A (en) * | 2011-05-25 | 2014-01-29 | 邦及奥卢夫森公司 | Power supply arrangement for single ended class d amplifier |
| CN103548249B (en) * | 2011-05-25 | 2017-05-10 | 爱思动力公司 | Power supply arrangement for single ended class d amplifier |
| CN103151941A (en) * | 2013-03-26 | 2013-06-12 | 王彤 | Counter excitation type power superposition circuit |
| CN103762834A (en) * | 2013-12-31 | 2014-04-30 | 江苏嘉钰新能源技术有限公司 | Auxiliary power supply of three-phase three-level VIENNA rectifier |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100526 Termination date: 20160909 |
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| CF01 | Termination of patent right due to non-payment of annual fee |