CN201429791Y - High-speed data communication device in high voltage reactive-load compensation equipment - Google Patents

Abstract

The utility model discloses a high-speed data communication device in high voltage reactive-load compensation equipment, which comprises a Digital Signal Processing circuit, a two-port network Random-Access Memory circuit and a Central Processing Unit singlechip circuit, wherein the Digital Signal Processing circuit and the Central Processing Unit singlechip circuit are respectively connected withthe two-port network Random-Access Memory circuit through a data bus, an address bus and a control wire, the Digital Signal Processing circuit is a main processor, and the two-port network Random-Access Memory circuit is a data sharing interface. The high-speed data communication device in high voltage reactive-load compensation equipment can transfer on-site constantly changing data to a controller through the fastest speed, and the control can make corresponding processing within the shortest time, thus the control time is reduced, and the control precision is enhanced.

Description

High-speed data communication device in the high-pressure reactive compensation equipment

(1) technical field

The utility model relates to data communication technology, is specifically related to a kind of high-speed data communication part of high-pressure reactive compensation equipment.

(2) background technology

Control procedure for the high-pressure reactive compensation controller, it is very important carrying out data processing in real time fast, need in the shortest time, send the data that the scene constantly changes to controller, carry out respective handling, finally finish control total system by controller.

General a slice DSP that adopts adds that storer, A/D converter and Peripheral Interface constitute a complete control system in existing high-pressure reactive compensation equipment, is infeasible but this scheme will reach high-speed real-time control.Because a real-time control system generally need be finished tasks such as data acquisition, mould/number conversion, analytical calculation, D/A switch, real-time process control and demonstration, depending merely on a slice DSP finishes these work and will certainly prolong the control cycle of system to controlling object greatly, reduce control accuracy, thereby influenced the performance of total system.

(3) summary of the invention

The purpose of this utility model is to provide a kind of shortcoming that overcomes foregoing circuit, send the data that the scene constantly changes to controller with the fastest speed, in the shortest time, make corresponding processing by controller, shorten the control time, improved the high-speed data communication device in the high-pressure reactive compensation equipment of control accuracy.

The purpose of this utility model is achieved in that its composition comprises: DSP circuit, dual port RAM circuit and CPU single chip circuit, DSP circuit, CPU single chip circuit are connected by data bus, address bus and control line with dual port RAM circuit respectively, the DSP circuit is a primary processor, and dual port RAM is the interface of data sharing.System is a primary processor with DSP (TMS320F2812), and dual port RAM (CY7C133) is as the interface of data sharing.Its major function is to receive control command and the setup parameter that CPU (INTEL80C196) writes dual port RAM, and with these the order and parameter send DSP to, and after DSP receives these instructions or setting data scope or make corresponding control strategies, and control system is made corresponding adjustment, after treating system stability, DSP writes some important real time datas of system in the dual port RAM again, is taken out by CPU.CPU can be sent to the data in the dual port RAM and do monitoring processing in real time in the host computer.In control system, add a CPU, be responsible for tasks such as data acquisition, mould/number conversion, process control and man-machine interface specially, make DSP be absorbed in the realization of systematic control algorithm, make full use of its high-speed data processing power.This CPU adopts 16 INTEL series monolithic.At this moment, just need to adopt dual port RAM to solve data sharing between DSP and the CPU, promptly all data can be by the high-speed bidirectional transmission of dual port RAM freedom realization DSP and CPU.

The utility model also has some technical characterictics like this: described dsp chip is a new generation of TI company chip TMS 320 F 2812, and its data-bus width is 32, and address-bus width is 24, and speed rises to 150M, has abundant peripheral hardware simultaneously.And that the dual port RAM employing is the CY7C133 of CYPRESS company development, this chip is high speed 2K * 16CMOS dual-port static RAM, have two and overlap address bus, data bus and control bus separate, complete symmetry, adopt 68 pin PLCC packing forms, the maximum access time can be 25/35/55ns.CY7C133 allows two CPU to read any storage unit (comprise and read same address location simultaneously) simultaneously, but does not allow to write simultaneously or one read one and write same address location, otherwise will make a mistake.Introduced arbitrated logic (busy logic) circuit in the dual port RAM and solved this problem: when left and right sides two-port writes simultaneously or one reads one when writing same address location, stable address port is is preferentially read and write by arbitraling logic circuit earlier, internal circuit makes the signal of another port effective simultaneously, and in internalized prohibition the other side visit, up to the port EO.Because the data line width of TMS320F2812 is 32, and the data bit width of CY7C133 is 16, therefore adopt low 16 with the TMS320F2812 data bus to link to each other with the data bus of dual port RAM.Described another cpu circuit is INTEL80C196, is a 16 single-chip microcomputers of INTEL Corp., and inside has 10 high-speed a/d converters of one 8 passage, and has PWM output, is a high-performance single-chip microcomputer.

The utility model relates to the high-speed data communication part of various high-pressure reactive compensation equipment; be used for the various real time datas in scene are transmitted fast; so that controller can calculate, handle significant data in the shortest time; and control system makes response fast to realize the purpose of rapid adjustment systematic parameter and protection visual plant, solved in the past long, processing speed of data communication equipment (DCE) transmission time and waited problem slowly.The utility model has solved that the data communication equipment (DCE) data transmission period is long in the past, processing speed is slow, complex structure, influence the difficult problems such as performance of total system.Realize high-speed communication for CPU end and DSP end a kind of practicality, design method efficiently are provided.Compare with the conventional serial communication mode, the novel circuit that is adopted is the data rate height not only, and good in anti-interference performance.This method has not only been simplified the hardware configuration and the software programming of system, and makes system have higher communication speed, has guaranteed the real-time and the reliability of system.In addition, designed CPU/DSP and the interface circuit between the dual port RAM in the system, logic control is simple and practical, other application system is had portable preferably.

(4) description of drawings

Fig. 1 is the electrical block diagram of the utility model high-speed data communication device.

Fig. 2 is the schematic diagram of the utility model high-speed data communication circuit.

(5) embodiment

Below in conjunction with the drawings and specific embodiments the utility model is further described:

The utility model ultimate principle is when operating personnel import some reactive-load compensation equipment required on-site parameters and control strategy by keyboard after, CPU (INTEL80C196) can write these parameters in the dual port RAM (CY7C133), simultaneously the CPU real time data of the system of DSP after handling of can also reading back from dual port RAM.

Fig. 1 is the electrical block diagram of present embodiment high-speed data communication device.At first CPU with data delivery to the interface of dual port RAM, if this moment, DSP did not write data in the same unit in dual port RAM, then the data of CPU can write in the dual port RAM, and this moment DSP if from this unit reads data, just these data can be taken out, handle accordingly, after treating these processing of system responses and adjusting output, DSP obtains the real time data of system and is sent on the interface of dual port RAM, if this moment, CPU did not carry out write operation to dual port RAM, the data of DSP just can write in the dual port RAM, and are same, CPU can read these data immediately, and these data are used for monitoring demonstration in real time.

Fig. 2 is the schematic diagram of present embodiment high-speed data communication circuit.Because the inner structure of dual port RAM (CY7C133) is the dual-port storage array, about two ports can shared this storage array, and have separately control line, when access data separately, identical with common RAM.When reading the data of different storage spaces simultaneously and reading the data in identical data space simultaneously, DSP end and CPU end can carry out simultaneously.Be that CPU is when carrying out read data to dual port RAM, chip selection signal/CER with the CPU end is changed to significant level earlier, the enable signal/OER that reads with dual port RAM becomes low level again, send corresponding address to the A0R-A10R address wire then, 16 bit data that then are stored in this place, address in the dual port RAM are read out simultaneously, and are sent among the 80C196 by the D0R-D15R data bus; When CPU carries out write operation to dual port RAM, also need the chip selection signal/CER of CPU end is changed to significant level, control signal/OER with dual port RAM becomes high level then, by the D0R-D15R data bus data is sent in the pairing address of A0R-A10R address bus at last and goes.When DSP carried out read data to dual port RAM, method was consistent with mode recited above, and only the chip selection signal of DSP end becomes/CEL, and control signal becomes/OEL, and address wire becomes A0-A10, and data line becomes D0-D15.

Yet if simultaneously identical data space is done write operation, or a port makes write operation to this data space in the another port when one data space is done read operation, and cpu port and DSP port will clash.At this moment CY7C133 handles both of these case by the BUSY pin.

When cpu port carries out read-write operation with the DSP port to different storage spaces, access simultaneously.At this moment, the BUSY signal of cpu port and DSP port is put height simultaneously.If when same storage space is carried out storage operation simultaneously, the request signal storage of which end occurs earlier, and then the BUSY signal of this end is put height, allows storage.After the storage signal of which end appears at, then this end BUSY signal put low, forbidden storage.It should be noted that the mistiming that two ends, left and right sides access request signal occurs must be greater than 5ns, before not so arbitrated logic can't judge that the access request signal on which limit appears at.If the mistiming that the two ends access request signal occurs is less than the situation of 5ns, arbitrated logic is put height with BUSY signal on one side, the BUSY signal of another side is put low, thereby guarantee that one of two port carry out data storage, data read is carried out in the another port, has avoided conflict.

Software implement scheme:

Dual port RAM must adopt certain mechanism to coordinate CPU end and the read-write operation of DSP end to it, otherwise the mistake that can occur reading and writing data.Here can be divided into the storage space of dual port RAM very, two spaces of even address.Wherein, the space, odd address is specialized in 80C196 and is write, and the even address space is specialized in 80C196 and read.We only need handle accordingly to the software of TMS320F2812 and get final product so, that is to say that TMS320F2812 is read-only to the space, odd address of dual port RAM, and the antithesis address space is only write.So just avoided TMS320F2812 and 80C196 write operation to the same address location of dual port RAM.

Claims (4)

1, the high-speed data communication device in a kind of high-pressure reactive compensation equipment, the composition that it is characterized in that it comprises: DSP circuit, dual port RAM circuit and CPU single chip circuit, DSP circuit, CPU single chip circuit are connected by data bus, address bus and control line with dual port RAM circuit respectively, the DSP circuit is a primary processor, and dual port RAM is the interface of data sharing.

2, the high-speed data communication device in the high-pressure reactive compensation equipment according to claim 1 is characterized in that described dsp chip is a TI company chip TMS 320 F 2812.

3, the high-speed data communication device in the high-pressure reactive compensation equipment according to claim 1, what it is characterized in that described dual port RAM employing is the CY7C133 chip of CYPRESS company.

4, the high-speed data communication device in the high-pressure reactive compensation equipment according to claim 1 is characterized in that described CPU single chip circuit is INTEL80C196, is 16 single-chip microcomputers.

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