CN201413627Y - Monitor EDID information read and storage circuit - Google Patents
Monitor EDID information read and storage circuit Download PDFInfo
- Publication number
- CN201413627Y CN201413627Y CN2009200972474U CN200920097247U CN201413627Y CN 201413627 Y CN201413627 Y CN 201413627Y CN 2009200972474 U CN2009200972474 U CN 2009200972474U CN 200920097247 U CN200920097247 U CN 200920097247U CN 201413627 Y CN201413627 Y CN 201413627Y
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- flash
- mcu
- edid information
- monitor
- storage circuit
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Abstract
The utility model provides a monitor EDID (extended display identification data) information read and storage circuit. The monitor EDID information read and storage circuit comprises an LDO (low dropout regulator), a decompression diode, a FLASH, a MCU and an analog signal interface, wherein the LDO is connected with the decompression diode, the FLASH and the MCU; meanwhile, the FLASH is also connected with the MCU; the analog signal interface connected with a host computer is connected on the MCU; and the monitor EDID information read and storage circuit directly stores EDID information through the FLASH circuit used for storing programs in the system, and also can normally supply power for the FLASH to achieve the read and the record of the EDID information under the condition of no connection of a control power supply, thereby realizing simplification of the circuit, reducing cost and improving competitiveness of products.
Description
Technical field
The utility model relates to a kind of internal circuit of display, and especially a kind of display EDID information reads memory circuit.
Background technology
EDID information is the normal data information that display is transferred to host computer, comprise and to receive capable field frequency scope, production firm, date of manufacture, product ID, product type, typical display mode and parameter etc. thereof, in the display system EDID information is used independent eeprom circuit storage at present, provide PC to write and read, LDO is connected with FLASH, FLASH is connected with MCU by CSZ/SDO/SDI/SCK Pin, MCU is connected with host computer by D_SUB (VGA) interface, MCU is connected with EEPROM by SDA/SCL Pin simultaneously, EEPROM also is connected with host computer by D_SUB (VGA) interface, as seen when power supply when EEPROM powers, PC_5V is also giving EEPROM direct current supply simultaneously, the circuit complexity, cost is higher.
Above-mentioned LDO is a low pressure difference linear voltage regulator, and FLASH is the multimedia storer, and MCU is the controller part of display chip.
The utility model content
Technical problem to be solved in the utility model is to provide a kind of display EDID information to read memory circuit.
For solving the problems of the technologies described above, the technical solution of the utility model is:
A kind of display EDID information reads memory circuit, comprise LDO, buck diode, FLASH, MCU and analog signal interface, wherein LDO is connected with buck diode, FLASH and MCU respectively, simultaneously FLASH also is connected with MCU, is connected with on the MCU to be used for the analog signal interface that is connected with host computer.
Preferably, described display EDID information reads memory circuit, and wherein analog signal interface is D_SUB interface or VGA interface.
The beneficial effects of the utility model are:
Aforementioned display device EDID information reads memory circuit, directly be used for stored program FLASH circuitry stores EDID information in the using system, even also can give the FLASH normal power supply under the unconnected situation of control power supply, thereby the realization circuit that reads and write of finishing EDID information is oversimplified, reduce cost, improve product competitiveness.
Description of drawings
Fig. 1 is the circuit side connector block diagram that a kind of display EDID information that the utility model provides reads memory circuit.
Among the figure: 1-LDO 2-FLASH 3-MCU 4-D_SUB interface 5-buck diode
Embodiment
For further specifying the utility model, existing conjunction with figs. is described in detail:
As shown in Figure 1, described display EDID information reads memory circuit, comprise the LDO1 (model is NCP1117ST33T3G) that is connected with the control power supply, buck diode 5, FLASH2 (model is MX25L1005MC), MCU3 (model is NT68167) and D_SUB interface 4, wherein LDO1 respectively with buck diode 5, FLASH2 is connected with MCU3, FLASH2 also is connected with MCU3 simultaneously, MCU3 is connected with host computer by D_SUB interface 4 again, wherein be connected by CSZ/SDO/SDI/SCK Pin between FLASH2 and the MCU3, carry out SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) bus communication.
Above-mentioned CSZ/SDO/SDI/SCK Pin is meant the title of several Pin that FLASH2 links to each other with MCU3, CSZ: enable control, SDO: serial data output, SDI: serial data input, SCK: serial data clock.
Principle of work is summarized as follows:
Under the situation that the control power supply is not powered, computing machine (PC) still can read EDID information, described display EDID information reads memory circuit, the 5V voltage of one of them Pin in the analog interface of computing machine is passed through buck diode 5, input to the voltage of LDO1 3.3V in the system, thereby under the unconnected situation of control power supply, also can give the FLASH2 normal power supply, finish reading and writing of EDID information.
The above only is a preferred implementation of the present utility model; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.
Claims (2)
1, a kind of display EDID information reads memory circuit, it is characterized in that: comprise LD0, buck diode, FLASH, MCU and analog signal interface, wherein LD0 is connected with buck diode, FLASH and MCU respectively, simultaneously FLASH also is connected with MCU, is connected with on the MCU to be used for the analog signal interface that is connected with host computer.
2, a kind of display EDID information according to claim 1 reads memory circuit, it is characterized in that: described analog signal interface is D_SUB interface or VGA interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009200972474U CN201413627Y (en) | 2009-06-19 | 2009-06-19 | Monitor EDID information read and storage circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009200972474U CN201413627Y (en) | 2009-06-19 | 2009-06-19 | Monitor EDID information read and storage circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201413627Y true CN201413627Y (en) | 2010-02-24 |
Family
ID=41715508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009200972474U Expired - Fee Related CN201413627Y (en) | 2009-06-19 | 2009-06-19 | Monitor EDID information read and storage circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201413627Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108269550A (en) * | 2016-12-30 | 2018-07-10 | 瑞昱半导体股份有限公司 | Display controller, display control chip and operation method thereof |
-
2009
- 2009-06-19 CN CN2009200972474U patent/CN201413627Y/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108269550A (en) * | 2016-12-30 | 2018-07-10 | 瑞昱半导体股份有限公司 | Display controller, display control chip and operation method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: TIANJIN SANXING ELECTRONIC CO., LTD. Free format text: FORMER OWNER: SANSUNG ELECTRONIC DISPLAY CO., LTD., TIANJIN Effective date: 20111025 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111025 Address after: 300385 Micro Electronics Development Zone, Tianjin economic and Technological Development Zone, four Patentee after: Tianjin Sanxing Electronic Co., Ltd. Address before: 300385 micro industry road, Microelectronics Industrial Zone, Tianjin economic and Technological Development Zone, four Patentee before: Sansung Electronic Display Co., Ltd., Tianjin |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100224 Termination date: 20130619 |