CN201365311Y - High-definition decoder based on digital TV HDTV platform - Google Patents
High-definition decoder based on digital TV HDTV platform Download PDFInfo
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- CN201365311Y CN201365311Y CN 200820183542 CN200820183542U CN201365311Y CN 201365311 Y CN201365311 Y CN 201365311Y CN 200820183542 CN200820183542 CN 200820183542 CN 200820183542 U CN200820183542 U CN 200820183542U CN 201365311 Y CN201365311 Y CN 201365311Y
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Abstract
The utility model relates to a high-definition encoder based on a digital TV HDTV platform, which comprises a multi-circuit main board, a back plate with a plurality of inlaid buses and interfaces, a debugging port and an output interface; an interface FPGA in each circuit of main board transmits the SPTS of the corresponding main board processed by the SPTS of the previous main boards and the encoding FPGA in the main board to an interface FPGA of the next circuit of main board, and the last circuit of main board reuses the SPTS of the previous main boards and the SPTS of the main board into multi-program transmission flow MPTS and outputs same. The high-definition decoder based on digital TV HDTV platform is capable of providing programs with standard definition and high definition under the standard definition network condition, protecting the existing network environment of the operators and increasing the service items of the operators.
Description
Technical field
The utility model relates to a kind of high definition encoder based on digital television HDTV (HDTV (High-Definition Television)) platform, particularly a kind of multi-path high-definition encoder of the TS stream based on standard H.264.
Background technology
China resident family middle high-resolution LCD TV owning rate increases greatly at present, and people are also more and more urgent to the requirement of high-quality digital television program.Along with constantly popularizing of high definition (HD) Digital Television, originally only support the encoder of MPEGII standard, can not re-use under the requirement for the bigger code check bandwidth of high-definition signal coding, vast operator presses for the equipment of the compatible high SD encoding function of supporting coding standard of new generation.
The utility model content
The problem that solves
The high definition encoder based on the HDTV platform in the past can only be encoded simultaneously to 4 tunnel program source, does not have the MPTS packet function.Therefore there is the excessive problem of encoder bit rate under traditional coded system in the existing digital TV in high resolution signal broadcasting.
The means that are used to deal with problems
The related high definition encoder based on digital television HDTV platform in a side of the present utility model is characterised in that to possess: input interface, its input multi-path high-definition video-audio signal; The multichannel mainboard, each road mainboard all possesses two on-site programmable gate array FPGAs, is respectively interface FPGA and coding FPGA, and the multichannel mainboard links to each other with input interface respectively, respectively the HD video coding audio signal of multichannel input is handled, obtained single program transport stream SPTS separately; Each road mainboard in the multichannel mainboard except that last road mainboard with the SPTS of oneself and before the SPTS of each road mainboard be transferred to next road mainboard together, last road mainboard will before the SPTS of each road mainboard and the SPTS of own mainboard be multiplexed with MPTS MPTS; Backboard, it is embedded with a plurality of buses and interface, makes each functional module and port by the backboard mutual communication; Debug port connects computer by this debug port and comes encoder is monitored; And output interface, single program transport stream SPTS or the MPTS MPTS that encoding process obtains carried out in its output in each road mainboard.
The related high definition encoder based on digital television HDTV platform in another side of the present utility model is characterised in that, described multichannel mainboard also can directly link to each other with described output interface respectively, after respectively the HD video coding audio signal of multichannel input being handled, the single program transport stream SPTS separately that processing is obtained exports by described output interface respectively.
The related high definition encoder based on digital television HDTV platform in another side of the present utility model is characterised in that, described multichannel mainboard is carrying out multichannel SPTS separately in the output, and also the MPTS that one tunnel multiplexing multichannel SPTS is obtained is by described output interface output.
The related high definition encoder based on digital television HDTV platform in another side of the present utility model is characterised in that, described high definition encoder also possesses the temperature monitoring module, be used to measure complete machine work internal temperature, when exceeding predefined temperature range, produce overtemperature alarm.
The related high definition encoder based on digital television HDTV platform in another side of the present utility model is characterised in that described multichannel mainboard is 8 road mainboards.The related high definition encoder based on digital television HDTV platform in another side of the present utility model is characterised in that: described input interface is the HDTV level of 8 road HDMI interfaces or HD/SD SDI interface, and its input meets the multi-path high-definition video-audio signal of SMPTE259/292 standard; Described output interface, output meets the H.264 signal of coding standard, MP@HL, HP@HL LEVLE4.1 standard.
The effect of utility model
According to the high definition encoder based on digital television HDTV platform of the present utility model, can encode simultaneously to the multi-path high-definition video and audio program, and carry out the MPTS package, can under the SD network condition, provide the program of single-definition program and high definition.Under the existing network environment of protection operator, increase the service item of operator.Therefore solve the excessive problem of encoder bit rate in the digital TV in high resolution signal broadcasting, can greatly promote the service quality of operator.
Description of drawings
Fig. 1 is the system architecture diagram that expression comprises the digital TV in high resolution broadcast system of the high definition encoder that the utility model is related.
Fig. 2 is the structure chart of the related high definition encoder of expression the utility model.
Fig. 3 is the structure chart of road mainboard in the multichannel mainboard of the related high definition encoder of expression the utility model.
Fig. 4 is the (schematic diagram of the handling process of 1＜M＜N) of M road mainboard under the expression N:N:1 model.
Fig. 5 is the schematic diagram of the handling process of N road mainboard under the expression N:N:1 model.
Embodiment
Fig. 1 shows the system architecture of the related high definition encoder 1 of the utility model.
High definition encoder 1 communicates according to snmp protocol and information platform control terminal 2, and the keeper controls the coding operation of high definition encoder 1 by information platform control terminal 2.High definition encoder 1 is connected to HD video source 3 by the HDMI/SDI/ka interface, and this HD video source 3 can be equipment such as high-definition camera, high definition decoding player.High-definition signal is 3 input high definition encoders 1 from the HD video source, in the ASI mode MPTS is outputed to modulating equipment (QAM) 4 after encoding, be transferred to the receiving terminal 5 of broadcast then, as teaching machine top box (STB), TV (TV), the SPTS that multiplexing multiplex coding obtains in this MPTS wherein.
The structure of the high definition encoder that the utility model is related is described with reference to Fig. 2.
The related high definition encoder 1 of the utility model comprises multichannel mainboard 11, backboard 12, front panel 13, temperature monitoring module 14, debug port 15.Wherein, mainboard 11 is used for HD video coding audio signal and the multiplexing process to input, and its concrete structure and job step illustrate in the back.Backboard 12 comprises a plurality of buses and interface, makes each functional module and port by backboard 12 mutual communication.Front panel 13 comprises button, indicator light, liquid crystal display screen, communicates by letter with master cpu by USB HUB.Temperature monitoring module 14 is measured complete machine work internal temperature.Main control module is set operating temperature range to it, when exceeding the design temperature scope, produces overtemperature alarm, the notice main control module.Debug port 15 is used to connect PC, mainly connects computer by this interface equipment is monitored.
Below, the structure of road mainboard 11 in the multichannel mainboard of the high definition encoder that the utility model is related is described with reference to Fig. 3 (former Fig. 2).
As shown in Figure 3, mainboard 11 possesses interface FPGA 21, coding FPGA 22.The matrixes multiplexing, data that interface FPGA 21 embedded NIOSII master cpus 23, this interface FPGA 21 carry out TS stream switch.Interface FPGA 21 will offer coding FPGA 22 from the original A/V source of outside input by bus, and coding FPGA 22 encodes to it and seals with H.264 the NAL stream SPTS stream as video ES stream, turns back to interface FPGA 21 by bus.
Embedded NIOSII master cpu 23 is used for communicating with long-distance user's control end in interface FPGA 21, each processing unit that control is local.Interface FPGA 21 also possesses system reset module 24, FPGA program debugging interface (JTAG) 25, electrically-alterable ROM (EAROM) (EPCS) 26, synchronous static RAM (SSRAM) 27, flash memory 28,0101 interface 29, network interface 30, HDMI video interface 31, audio interface 32.In addition, interface FPGA 21 also is connected to backboard 8 by the LVDS interface.
Wherein, 24 pairs of mainboards of system reset module provide the machine system unified reset signal that powers on.FPGA program debugging interface (JTAG) 25 is used to carry out the debugging of FPGA program.The program that electrically-alterable ROM (EAROM) (EPCS) 26 is used to preserve FPGA.Synchronously static RAM (SSRAM) 27 is used to preserve data such as the PID that host computer sends and shows, and the buffer memory when being interface FPGA deal with data.Flash memory 28 is used to preserve operating system and other application programs.0101 interface 29 is mainly used in the output of the input of HD/SD SDI high-definition video signal, MPTS.Network interface 30 is connected to host computer by netting twine, and the user operates host computer and sends FPGA Configuration Online file, the work of controlled encoder.HDMI video interface 31 provides interface conversion for the vision signal that meets HDMI 1.3 standards.Audio interface 32 input audio signals.
The following describes the startup flow process of two FPGA.After device power, two FPGA start flow process and carry out synchronously.
About interface FPGA 21, after powering on, electrically-alterable ROM (EAROM) (EPCS) 26 reading of data configuration interface FPGA 21, interface FPGA 21 from flash memory 28 the read operation system to NIOSII master cpu 23, behind the os starting, NIOSII master cpu 23 carries out network communication by network interface 30 and long-distance user's control end, receives user's configuration parameter, be provided with and give corresponding processing module, and be saved among the USBDISK (not shown).While also returns to long-distance user's control end with the operating state of each module.
About coding FPGA 22, after powering on, electrically-alterable ROM (EAROM) (EPCS) 26 reading of data configuration codes FPGA 22, coding FPGA 22 load the FPGA program and start operation from EPC S 26.
After startup is finished, promptly begin Business Processing.
Two kinds of encoding process models that the related encoder of the utility model is supported are respectively N:N:1 model and N:N:N model, describe respectively below.
The specific coding flow process of N:N:1 model is as follows: the N road mainboard among Fig. 1 receives the high definition or the original A/V of the SD source of outside input, encodes respectively afterwards and seals with H.264 the NAL stream SPTS stream package (with reference to " Amendment 3:Transport ofAVC video data over ITU-T Rec.H.222.0|ISO/IEC 13818-1 streams " standard) as video ES stream.Then, first via mainboard is transferred to the second road mainboard with the SPTS stream package SPTS (1) that generates by backboard, the second road mainboard is transferred to the Third Road mainboard together with the SPTS stream package SPTS (1) of the first via and the SPTS stream package SPTS (2) that oneself generates, and the Third Road mainboard is transferred to the four road mainboard with SPTS stream package SPTS (1), the SPTS stream package SPTS (2) that first and second road mainboard generates together with the SPTS stream package SPTS (3) that oneself generates.By that analogy, SPTS stream package SPTS (1), the SPTS (2) on the preceding N-1 road that N road mainboard will receive ... SPTS (N-1), the SPTS that oneself generates flow package SPTS (N) and are multiplexed into MPTS by the program specific information PSI that IP receives, and export in the ASI mode.
The specific coding flow process of N:N:N model is as follows: the N road mainboard among Fig. 1 receives the original A/V source of outside input, encodes respectively afterwards and seals with H.264 the NAL stream SPTS stream package (with reference to " Amendment 3:Transport of AVC videodata over ITU-T Rec.H.222.0|ISO/IEC 13818-1 streams " standard) as video ES stream.Export the TS stream that meets the ASI form afterwards separately.
Handling process (1＜the M＜N) wherein of M road mainboard in the N:N:1 encoding model is described below with reference to the flow chart of Fig. 4.In step STEP 1, interface FPGA 21 is from A/V source input video/audio signal (with 5.).In step STEP 2, interface FPGA 21 is converted into the number format that coding is supported with the signal of input, and is transferred to coding FPGA 22.In step SETP 3, coding FPGA 22 encodes, and generates SPTS stream package, and is transferred to interface FPGA 21.In addition, in step STEP 0, M road mainboard receives from each road SPTS of M-1 mainboard before.Then, in step STEP 4, interface FPGA 21 is with each road SPTS of M-1 road mainboard and the SPTS of oneself are transferred to next M+1 road, road mainboard together before.
The handling process of first via mainboard is similar to the handling process of M road mainboard, but does not have step STEP 0.Specify in this omission.
The handling process of N road mainboard in the N:N:1 encoding model is described below with reference to the flow chart of Fig. 5.In the handling process of N road mainboard, step STEP 0～step STEP 3 is identical with the handling process of the M road mainboard of Fig. 3 record, but there is not step STEP 4, but in step STEP 5 by interface FPGA 21 will before each the road SPTS and the own SPTS of N-1 road mainboard multiplexing, generate MPTS and export.
In addition, the video/audio signal from the input of original A/V source also can be the SD video/audio signal.
Especially, this high definition encoder is preferably 8 tunnel high definition encoders, possesses 8 road mainboards, and two kinds of encoding models are preferably 8:8:1 model and 8:8:8 model.
At this moment, input interface is the HDTV level of 8 road HDMI interfaces or HD/SD SDI interface, and the signal of input meets H.264 coding standard, and output signal meets SMPTE259, SMPTE292, MP@HL, HP@HL LEVLE4.1 standard.Can realize 8 road Dobies, 5.1 channel audios coding, bit rate output 32-384kbps.Can realize 8 tunnel 2 passage AAC audio codings, bit rate output 64kbps, 128kbps, 192kbps.
The above only is the specific embodiment of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. high definition encoder based on digital television HDTV platform is characterized in that possessing:
Input interface, its input multi-path high-definition video-audio signal;
The multichannel mainboard, each road mainboard all possesses two on-site programmable gate array FPGAs, is respectively interface FPGA and coding FPGA, and the multichannel mainboard links to each other with input interface respectively, respectively the HD video coding audio signal of multichannel input is handled, obtained single program transport stream SPTS separately; Each road mainboard in the multichannel mainboard except that last road mainboard with the SPTS of oneself and before the SPTS of each road mainboard be transferred to next road mainboard together, last road mainboard will before the SPTS of each road mainboard and the SPTS of own mainboard be multiplexed with MPTS MPTS;
Backboard, it is embedded with a plurality of buses and interface, makes each functional module and port by the backboard mutual communication;
Debug port connects computer by this debug port and comes described high definition encoder is monitored; And
Output interface, single program transport stream SPTS or the MPTS MPTS that encoding process obtains carried out in its output in each road mainboard.
2. the high definition encoder based on digital television HDTV platform according to claim 1 is characterized in that:
Described multichannel mainboard also can directly link to each other with described output interface respectively, and after respectively the HD video coding audio signal of multichannel input being handled, the single program transport stream SPTS separately that processing is obtained exports by described output interface respectively.
3. the high definition encoder based on digital television HDTV platform according to claim 2 is characterized in that:
Described multichannel mainboard is carrying out multichannel SPTS separately in the output, and also the MPTS that one tunnel multiplexing multichannel SPTS is obtained is by described output interface output.
4. the high definition encoder based on digital television HDTV platform according to claim 1 is characterized in that:
Described high definition encoder also possesses the temperature monitoring module, is used to measure complete machine work internal temperature, when exceeding predefined temperature range, produces overtemperature alarm.
5. according to each the described high definition encoder in the claim 1～3, it is characterized in that based on digital television HDTV platform:
Described multichannel mainboard is 8 road mainboards.
6. according to each the described high definition encoder in the claim 1～3, it is characterized in that based on digital television HDTV platform:
Described input interface is the HDTV level of 8 road HDMI interfaces or HD/SD SDI interface, and its input meets the multi-path high-definition video-audio signal of SMPTE259/292 standard;
Described output interface, output meets the H.264 signal of coding standard, MP@HL, HP@HLLEVLE4.1 standard.
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| CN 200820183542 CN201365311Y (en) | 2008-12-22 | 2008-12-22 | High-definition decoder based on digital TV HDTV platform |
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| CN 200820183542 CN201365311Y (en) | 2008-12-22 | 2008-12-22 | High-definition decoder based on digital TV HDTV platform |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102014264A (en) * | 2010-12-30 | 2011-04-13 | 广州市聚晖电子科技有限公司 | Implementation method for high-definition video design based on high-definition multimedia interface (HDMI) standard |
| CN105141991A (en) * | 2015-09-30 | 2015-12-09 | 深圳市九洲电器有限公司 | Housing of set-top box and set-top box |
| CN105306955A (en) * | 2014-07-04 | 2016-02-03 | 上海广播电视台 | 3d video coding system |
| CN116430202A (en) * | 2023-03-22 | 2023-07-14 | 镇江矽佳测试技术有限公司 | Chip burn-in test system, method, storage medium and electronic device |
-
2008
- 2008-12-22 CN CN 200820183542 patent/CN201365311Y/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102014264A (en) * | 2010-12-30 | 2011-04-13 | 广州市聚晖电子科技有限公司 | Implementation method for high-definition video design based on high-definition multimedia interface (HDMI) standard |
| CN105306955A (en) * | 2014-07-04 | 2016-02-03 | 上海广播电视台 | 3d video coding system |
| CN105306955B (en) * | 2014-07-04 | 2019-12-20 | 上海广播电视台 | 3D video coding system |
| CN105141991A (en) * | 2015-09-30 | 2015-12-09 | 深圳市九洲电器有限公司 | Housing of set-top box and set-top box |
| CN105141991B (en) * | 2015-09-30 | 2018-06-29 | 深圳市九洲电器有限公司 | A kind of STB casing and set-top box |
| CN116430202A (en) * | 2023-03-22 | 2023-07-14 | 镇江矽佳测试技术有限公司 | Chip burn-in test system, method, storage medium and electronic device |
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Effective date of registration: 20140108 Address after: 100080, room 5026, Shen Chang building, No. 51, Zhichun Road, Beijing, Haidian District Patentee after: Beijing BVCOM Technology Co., Ltd. Address before: 100190 room 51, No. 5678, Haidian District, Beijing, Zhichun Road Patentee before: Beijing BVCOM Technology Co., Ltd. |
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Address after: 100085 C, block 9, 3rd Street, Beijing, Haidian District, C612 Patentee after: Beijing horizon Technology Co., Ltd. Address before: 100080, room 5026, Shen Chang building, No. 51, Zhichun Road, Beijing, Haidian District Patentee before: Beijing BVCOM Technology Co., Ltd. |
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