CN102421005A - Embedded type based code stream analysis system - Google Patents
Embedded type based code stream analysis system Download PDFInfo
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- CN102421005A CN102421005A CN2011103764812A CN201110376481A CN102421005A CN 102421005 A CN102421005 A CN 102421005A CN 2011103764812 A CN2011103764812 A CN 2011103764812A CN 201110376481 A CN201110376481 A CN 201110376481A CN 102421005 A CN102421005 A CN 102421005A
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Abstract
The invention discloses an embedded type based code stream analysis system, comprising a hardware part and a software part. The hardware part is mainly composed of a FPGA (Field Programmable Gate Array) and an ARM (Advanced Risc Machine) and is further provided with peripheral chips, such as an ASI (Asynchronous Serial Interface) chip, an Ethernet interface chip, an SDRAM (Synchronous Dynamic random access memory), FLASH and the like, to constitute a complete embedded system. The software part comprises four modules, namely, an FPGA interface module, a TS (Transport Stream) code stream analysis module, a network server module and a web server module. According to the invention, TS code stream data can be subjected to synchronous byte extraction and packet sequence error check, a data stream can be monitored in real time, and error time and error conditions can be recorded in time.
Description
Technical field
The present invention relates to the digital television techniques field, be specifically related to a kind of based on Embedded code stream analysis system.
Background technology
Along with the maturation day by day of digital television techniques, the digitlization of China's TV network is also in the middle of the carrying out of anxiety.The cable digital TV system has formed the TS code stream transmission system of a complicacy from signal reception, coding, the links such as STB multiplexing, that be modulated to user side of front end; Critical data field in its transmission code stream must can be able to receive at receiving terminal like clockwork, otherwise can directly have influence on the transmission quality of cable digital TV system.In the cable digital TV system, use code stream analysis appearance test transmission code stream at present, with its detected transmission code stream whether meet whether MPEG-2/DVB standard, transmission code stream wrong, mistake aspect what, whether be received rectify really decoding and analyze information such as PSI/SI in the transmission code stream, debugging acid that the code stream analysis appearance also can be used as digital television devices such as digital satellite receiver, encoder, multiplexer, modulator, the TS code stream that detects input and output conformance with standard whether.
Therefore; For normal operation and the transmission quality that guarantees digital TV network; It is requisite test in DTV development and application center and debugging acid that research and development corresponding detecting system, checkout equipment etc. have become a very important job, these checkout equipments.The code stream analysis system also is action and the target that under such background, becomes vast R&D work person.
At present external relevant unit and research department have developed corresponding apparatus; But the difficult national conditions that meet China of external digital television code stream analytical system and equipment; And cost an arm and a leg, therefore be an important and urgent thing to code stream analysis system and development of equipments and research.
ASCII stream file ASCII refers to information such as the most original digital picture, audio frequency and video and handles and the data flow that forms through coding or packing, usually the analysis of ASCII stream file ASCII is comprised its pack arrangement, bag size, PSI/SI table information or the like are extracted and shown.The present invention is according to the DVB examination criteria, and hardware, software and the display interface etc. of associated code flow analysis are concentrated in the embedded system, adopts the B/S framework of server and browser to realize the demonstration of code stream analysis and analysis result.
Summary of the invention
The present invention provides a kind of design and implementation method of the code stream analysis software and hardware system based on FPGA+ARM platform, (SuSE) Linux OS, and the embedded system that will possess characteristics such as powerful, that cost is low, reliability is high, volume is little is widely used in digital TV field.
A kind of based on Embedded code stream analysis system, comprise hardware components and software section; Hardware components mainly is made up of FPGA and ARM, is equipped with ASI interface chip and Ethernet interface chip again, SDRAM, and peripheral chips such as FLASH are formed a complete embedded system; Software section is divided into FPGA interface, TS code stream analysis, the webserver, four modules of web server.
Select for use ARM and FPGA jointly the composition system be in order to realize the real-time of code stream analysis; Said ARM reads and writes data from FPGA as main equipment, accomplishes the analysis of TS code flow structure and to the control of FPGA, and with the parsing of the communication protocol of host computer; Said FPGA is mainly with the packet filtering of doing TS stream.
TS stream is through being divided into two-way after interface TUNE or the ASI entering system: the one tunnel passes to decoder decode and the extraction of making basic SI/PSI information; FPGA is passed to as code stream analysis in another road, communicates through the HOST bus between FPGA and the ARM.
Job step between each module of software section is following:
Step 1:FPGA interface module reads the data in the IO internal memory, is forwarded to each module after the classification;
Step 2:TS code stream analysis module receives the TS bag, splices complete PSI/SI packets of information according to PID; Decoded information bag and obtain code table if hardware resource is enough, can be considered parallel parsing TS packets then, the speed of like this can expedited data analyzing; Pass to the webserver to code table information at last; Simultaneously, detected PSI/SI code table mistake passes to the webserver after also will be added up in the decode procedure;
Step 3: the webserver is collected PSI/SI code table information, the error message of TS code stream, and PCR/PID information is according to sending to the client that connects the web server behind the host-host protocol coding; Simultaneously, the webserver receives the passback instruction of client, sends to code stream analysis module and FPGA interface;
Step 4:web server, webpage that is provided for showing and Java Applet give client downloads; When client connects the web server, just pass to web server module to the network information of client, so that setting up network with client, it is connected; What adopt is to support multi-platform GoAhead WebServer, also can use Boa, thttpd etc.;
Step 5:Java Applet is used for receiving and showing the code stream analysis result, and sends order to ARM, has simple interactive function.
Technique scheme can be found out, because the present invention has following beneficial effect:
1. the present invention can carry out sync byte extraction and the error checking of bag preface to the TS bit stream data, and data stream is monitored in real time, in time writes down the time and the wrong situation of makeing mistakes;
2. the current bandwidth of each road PID of statistics that the present invention can be real-time takies situation, the total quantity and the transmission code rate of current TS bag;
The present invention can be open-and-shut the essential information, programme information, bandwidth information etc. of demonstration TS stream file.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is system global structure figure of the present invention;
Fig. 2 is system hardware structure figure of the present invention;
Fig. 3 is system software structure figure of the present invention.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making all other embodiment that obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
The embodiment of the invention provides a kind of can provide reliable foundation for measurement and the detection that DTV transmits based on Embedded code stream analysis system, below is elaborated respectively.
Be illustrated in figure 1 as system global structure figure of the present invention, native system is a hardware platform with FPGA+ARM, is operating system with Linux.Input code flow is handled generation specific packet in back through FPGA with the code stream analysis software analysis that operates on the operating system, connects the code stream analysis appearance in client with browser, and downloading Java Applet operation automatically can the display analysis result.Java Applet can also accomplish simple making and settlement and controlled function except the display analysis result.
Be illustrated in figure 2 as system hardware structure figure of the present invention.According to the analysis of application demand, hardware of the present invention mainly is made up of FPGA and ARM, is equipped with ASI interface chip and Ethernet interface chip again, SDRAM, and peripheral chips such as FLASH are formed a complete embedded system.Select for use ARM and FPGA jointly the composition system be in order to realize the real-time of code stream analysis.TS stream is through being divided into two-way after interface (TUNE or ASI) the entering system: the one tunnel passes to decoder decode and the extraction of making basic SI/PSI information; FPGA is passed to as code stream analysis in another road.Communicate through the HOST bus between FPGA and the ARM.
Said FPGA is mainly with the packet filtering of doing TS stream, and some require very high to real-time and the better simply wrong detection of implementation procedure (for example continuous counter mistake) is also accomplished by FPGA in the TR101-290 standard;
Said ARM reads and writes data from FPGA as main equipment, mainly accomplishes the analysis of TS code flow structure and to the control of FPGA, and with the parsing of the communication protocol of host computer.
TS code stream analysis software of the present invention is mainly accomplished following three tasks:
1. read the TS packet after FPGA filters, PCR numerical value, information such as PID speed.
2. decoding PSI/SI code table is analyzed the mistake in the TS stream according to TR290.
3. send data and the instruction that receives client through network, transmit instruction and give analysis software.
According to above three tasks, this software can be divided into FPGA interface, TS code stream analysis, the webserver, four modules of web server, and its module declaration is seen shown in the table 1.
Be illustrated in figure 3 as system software structure figure of the present invention, the job step between the four module is following:
Step 1:FPGA interface module reads the data in the IO internal memory, is forwarded to each module after the classification.
Step 2:TS code stream analysis module receives the TS bag, splices complete PSI/SI packets of information according to PID.Decoded information bag and obtain code table if hardware resource is enough, can be considered parallel parsing TS packets then, the speed of like this can expedited data analyzing.Pass to the webserver to code table information at last.Simultaneously, detected PSI/SI code table mistake passes to the webserver after also will be added up in the decode procedure.
Step 3: the webserver is collected PSI/SI code table information, the error message of TS code stream, and PCR/PID information is according to sending to the client that connects the web server behind the host-host protocol coding.Simultaneously, the webserver receives the passback instruction of client, sends to code stream analysis module and FPGA interface.
Step 4:web server, webpage that is provided for showing and Java Applet give client downloads.When client connects the web server, just pass to web server module to the network information of client, so that setting up network with client, it is connected.What we adopted is to support multi-platform GoAhead WebServer, also can use Boa, thttpd etc.
Step 5:Java Applet is used for receiving and showing the code stream analysis result, and sends order to ARM, has simple interactive function.
Need to prove, contents such as the information interaction between said apparatus and intrasystem each unit, implementation since with the inventive method embodiment based on same design, particular content can repeat no more referring to the narration among the inventive method embodiment here.
One of ordinary skill in the art will appreciate that all or part of step in the whole bag of tricks of the foregoing description is to instruct relevant hardware to accomplish through program; This program can be stored in the computer-readable recording medium; Storage medium can comprise: read-only memory (ROM; Read Only Memory), random access memory (RAM, Random Access Memory), disk or CD etc.
More than to the method for a kind of built-in Linux network acceleration that the embodiment of the invention provided; Carried out detailed introduction; Used concrete example among this paper principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that on embodiment and range of application, all can change, in sum, this description should not be construed as limitation of the present invention.
Claims (4)
1. one kind based on Embedded code stream analysis system, it is characterized in that this system comprises hardware components and software section; Hardware components mainly is made up of FPGA and ARM, is equipped with ASI interface chip and Ethernet interface chip again, SDRAM, and peripheral chips such as FLASH are formed a complete embedded system; Software section is divided into FPGA interface, TS code stream analysis, the webserver, four modules of web server.
2. system according to claim 1 is characterized in that, select for use ARM and FPGA jointly the composition system be in order to realize the real-time of code stream analysis; Said ARM reads and writes data from FPGA as main equipment, accomplishes the analysis of TS code flow structure and to the control of FPGA, and with the parsing of the communication protocol of host computer; Said FPGA is mainly with the packet filtering of doing TS stream.
3. system according to claim 1 is characterized in that, TS flows through being divided into two-way after interface TUNE or the ASI entering system: the one tunnel passes to decoder decode and the extraction of making basic SI/PSI information; FPGA is passed to as code stream analysis in another road, communicates through the HOST bus between FPGA and the ARM.
4. system according to claim 1 is characterized in that, the job step between each module of software section is following:
Step 1:FPGA interface module reads the data in the IO internal memory, is forwarded to each module after the classification;
Step 2:TS code stream analysis module receives the TS bag, splices complete PSI/SI packets of information according to PID; Decoded information bag and obtain code table if hardware resource is enough, can be considered parallel parsing TS packets then, the speed of like this can expedited data analyzing; Pass to the webserver to code table information at last; Simultaneously, detected PSI/SI code table mistake passes to the webserver after also will be added up in the decode procedure;
Step 3: the webserver is collected PSI/SI code table information, the error message of TS code stream, and PCR/PID information is according to sending to the client that connects the web server behind the host-host protocol coding; Simultaneously, the webserver receives the passback instruction of client, sends to code stream analysis module and FPGA interface;
Step 4:web server, webpage that is provided for showing and Java Applet give client downloads; When client connects the web server, just pass to web server module to the network information of client, so that setting up network with client, it is connected; What adopt is to support multi-platform GoAhead WebServer, also can use Boa, thttpd etc.;
Step 5:Java Applet is used for receiving and showing the code stream analysis result, and sends order to ARM, has simple interactive function.
Priority Applications (1)
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| CN2011103764812A CN102421005A (en) | 2011-11-22 | 2011-11-22 | Embedded type based code stream analysis system |
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| CN2011103764812A CN102421005A (en) | 2011-11-22 | 2011-11-22 | Embedded type based code stream analysis system |
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| CN102710984A (en) * | 2012-05-11 | 2012-10-03 | 深圳Tcl新技术有限公司 | Method and device for processing program information |
| CN102779093A (en) * | 2012-07-04 | 2012-11-14 | 复旦大学 | Java invariance detection system of collection of object granularity |
| CN110536154A (en) * | 2019-08-16 | 2019-12-03 | 北京达佳互联信息技术有限公司 | Video code flow analysis method, device, electronic equipment and storage medium |
| CN113037532A (en) * | 2019-12-25 | 2021-06-25 | 中兴通讯股份有限公司 | Stream media code stream detection method, device, server and readable storage medium |
| CN115842934A (en) * | 2022-10-27 | 2023-03-24 | 北京华建云鼎科技股份公司 | Video signal processing system |
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| CN110536154A (en) * | 2019-08-16 | 2019-12-03 | 北京达佳互联信息技术有限公司 | Video code flow analysis method, device, electronic equipment and storage medium |
| CN113037532A (en) * | 2019-12-25 | 2021-06-25 | 中兴通讯股份有限公司 | Stream media code stream detection method, device, server and readable storage medium |
| CN115842934A (en) * | 2022-10-27 | 2023-03-24 | 北京华建云鼎科技股份公司 | Video signal processing system |
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Application publication date: 20120418 |