CN201359723Y - Self-starting serial bootstrap program loading and reading system - Google Patents
Self-starting serial bootstrap program loading and reading system Download PDFInfo
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- CN201359723Y CN201359723Y CNU200820206679XU CN200820206679U CN201359723Y CN 201359723 Y CN201359723 Y CN 201359723Y CN U200820206679X U CNU200820206679X U CN U200820206679XU CN 200820206679 U CN200820206679 U CN 200820206679U CN 201359723 Y CN201359723 Y CN 201359723Y
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Abstract
The utility model relates to a self-starting serial bootstrap program loading and reading system, which comprises a system level chip and an external SPI interface memory, wherein the system level chip comprises a CPU, an internal program memory, a self-starting serial bootstrap program loading module, a two-path double-direction multiplexer and a standard SPI protocol interface; the self-starting serial bootstrap program loading module is respectively connected with the input end I of the two-path double-direction multiplexer and the CPU, and is connected with the external SPI interface memory through the standard SPI protocol interface; the input end II of the two-path double-direction multiplexer is connected with the CPU; the output end is connected with an RAM; and the self-starting serial bootstrap program loading module consists of a self-starting loading circuit, a working mode switching circuit and an SPI main mode circuit. After the power is turned on, the self-starting serial bootstrap program loading module directly reads the algorithm program in the external memory, and fast loads the algorithm program into the internal program memory. The utility model has the advantages of simple program loading method and short system starting time, and can be used for a plurality of times of loading and reading operations.
Description
Technical field
The utility model relates to program loading system field, is meant that specifically the self-starting serial boot program based on system level chip loads and reading system.
Background technology
At present, program based on system level chip (SOC chip or dsp chip etc.) loads and reading system, structure as shown in Figure 1, comprise SOC chip or dsp chip and be used for the external memory storage of storage algorithm program, as SPI-EEPROM (high-speed synchronous serial port-EEPROM (Electrically Erasable Programmable Read Only Memo)) etc.Wherein, SOC or dsp chip comprise CPU, program load-on module and chip internal program storage (RAM), this program load-on module is made up of external interface and a ROM who carries the initialization boot, described RAM, external interface, the ROM that carries the initialization boot are connected the also external external memory storage of external interface respectively with cpu signal.The program loading method of this SOC or dsp chip system is a kind of boot program loads method of complexity, it is specific as follows: after system powers on, CPU reads the initialization boot in the ROM and it is carried out processing such as decoding, the external interface that will carry out the loading algorithm program is carried out initialization operations such as read-write mode configuration, then by the algorithm routine in the external interface reading external memory, at last, algorithm routine is loaded in the chip internal program storage (RAM) under the control of CPU and carries out.
The problem that the program loading method of said procedure loading system exists is: after each system powered on, CPU will spend a period of time and start complicated initial configuration such as initialization boot.At first to spend a period of time to the initialization boot that carries in the ROM read, processing such as decoding, then the external interface that will carry out the loading algorithm program is carried out initialization operations such as read-write mode configuration, just really begin download algorithm program and execution at last.The time that startup initialization boot is spent has been dragged slowly the start-up time of SOC or dsp chip system.
The utility model content
The utility model purpose is to overcome above-mentioned the deficiencies in the prior art, provide a kind of self-starting serial boot program to load and reading system, after native system powers on, self-starting serial boot program load-on module (the SSBL that it is built-in, Self Serial Boot Loader) need not initial configuration through CPU, and directly read algorithm routine in the outside SPI interface memory fast by standard SPI protocol interface, by two-way bidirectional multiplexer (Multiplexer) algorithm routine is loaded in the internal program memory (RAM) fast then, program loading method is simple, the system start-up time is short, and realizes easily.
The purpose of this utility model is achieved through the following technical solutions: self-starting serial boot program loads and reading system, comprise system level chip and the outside SPI interface memory that is used for the storage algorithm program, wherein, system level chip comprises CPU, internal program memory (RAM), self-starting serial boot program load-on module (SSBL, Self Serial Boot Loader), two-way bidirectional multiplexer (Multiplexer) and standard SPI protocol interface, described self-starting serial boot program load-on module respectively with the input end I of two-way bidirectional multiplexer, cpu signal connects, the self-starting serial boot program load-on module also is connected with the external memory storage signal by standard SPI protocol interface, simultaneously, the input end II of two-way bidirectional multiplexer is connected with cpu signal, and the output terminal of two-way bidirectional multiplexer is connected with the RAM signal.Described self-starting serial boot program load-on module is made up of self-starting loaded circuit (SBL), mode of operation commutation circuit (SMC), SPI holotype circuit (SPIM), and the mode of operation commutation circuit is connected with self-starting loaded circuit, SPI holotype circuit signal respectively.
In order to realize the utility model purpose better, described system level chip is SOC chip or dsp chip, and the described outside SPI interface memory that is used for the storage algorithm program is SPI-EEPROM.
Above-mentioned self-starting serial boot program loads the method that loads and read with reading system implementation algorithm program, comprises algorithm routine loading method and read method, and wherein, loading method specifically comprises the steps:
(1) after system powers on, mode of operation commutation circuit (SMC) the forbidding SPI holotype circuit (SPIM) in the self-starting serial boot program load-on module, and gating self-starting loaded circuit (SBL);
(2) self-starting loaded circuit (SBL) sends (RESET) signal that resets CPU is resetted (RESET), simultaneously, sends the input end I of gating control signal gating two-way bidirectional multiplexer (Multiplexer);
(3) self-starting loaded circuit (SBL) Control work mode switch circuit (SMC) reads algorithm routine in the outside SPI interface memory by standard SPI protocol interface, and the algorithm routine that is read is loaded in the internal program memory (RAM) through two-way bidirectional multiplexer (Multiplexer);
Read method specifically may further comprise the steps:
In A, the above-mentioned loading method step (3), when algorithm routine is loaded into after internal program memory (RAM) finishes, mode of operation commutation circuit (SMC) forbidding self-starting loaded circuit (SBL) in the self-starting serial boot program load-on module, and gating SPI holotype circuit (SPIM), make outside SPI interface memory in SPI holotype circuit (SPIM) connection;
B, self-starting loaded circuit (SBL) send the gating control signal makes CPU enter normal operating condition, and simultaneously, self-starting loaded circuit (SBL) sends the input end II of gating control signal gating two-way bidirectional multiplexer (Multiplexer); Then, CPU reads algorithm routine in the internal program memory (RAM) by two-way bidirectional multiplexer (Multiplexer).
Among the said method step B, when CPU reads algorithm routine in the internal program memory (RAM) by two-way bidirectional multiplexer (Multiplexer) after, if CPU finds the code in the algorithm routine and comprises the visit again of the external SPI of portion interface memory, then control the algorithm routine that SPI holotype circuit (SPIM) secondary reads in the outside SPI interface memory the interior code of corresponding and algorithm routine that CPU reads, and the algorithm routine that secondary reads is loaded in the internal program memory (RAM) through two-way bidirectional multiplexer (Multiplexer) secondary, then, the CPU algorithm routine that secondary is loaded into internal program memory (RAM) by two-way bidirectional multiplexer (Multiplexer) carries out secondary and reads.
If the code in the algorithm routine that CPU discovery secondary reads comprises the visit again of the external SPI of portion interface memory, can circulate according to above-mentioned secondary loading and read method repeatedly loads and read operation.
The utility model has following advantage and effect with respect to prior art:
(1) the utility model self-starting serial boot program loads and reading system, carrying out outside algorithm routine when loading, the built-in self-starting serial boot program load-on module of system directly reads algorithm routine in the outside SPI interface memory fast by standard SPI protocol interface, be loaded into algorithm routine among the RAM fast by the two-way bidirectional multiplexer then, and the initial configuration that need not to pass through CPU, thereby the program loading system of having saved existing system level chip is used in the time that starts the initialization boot when starting, program loading method is simple, it is short that program loads required time, so the system start-up time is short with respect to existing program loading system, and realize easily;
(2) the utility model self-starting serial boot program load with reading system externally algorithm routine load finish after, built-in self-starting serial boot program load-on module is the input end II that is connected of gating two-way bidirectional multiplexer and CPU at once, thereby CPU can read the algorithm routine among the RAM fast and carry out;
(3) in the utility model, when CPU reads algorithm routine in the internal program memory (RAM) by two-way bidirectional multiplexer (Multiplexer) after, if CPU finds the code in the algorithm routine and comprises the visit again of external portion storer, then CPU can read the algorithm routine of outside SPI interface memory corresponding to described code according to the control SPI holotype circuit of the code in the algorithm routine (SPIM), to realize that secondary loads or read-write operation, circulation repeatedly loads and read operation even, and repeatedly load and the read operation logic simple, fast, realize easily.
Description of drawings
Fig. 1 is for having now based on the program loading of system level chip and the structural representation of reading system;
Fig. 2 is the structural representation of the utility model self-starting serial boot program loading with reading system;
Fig. 3 is the structural representation of self-starting serial boot program load-on module in the utility model system;
Fig. 4 is the workflow block diagram of the utility model self-starting serial boot program loading with reading system.
Embodiment
Below in conjunction with embodiment and accompanying drawing the utility model is described in further detail, but embodiment of the present utility model is not limited thereto.
As shown in Figure 2, the utility model self-starting serial boot program loads and reading system, comprise SOC chip or dsp chip and the SPI-EEPROM that is used for the storage algorithm program, wherein, SOC chip or dsp chip comprise CPU, internal program memory (RAM), self-starting serial boot program load-on module (SSBL, Self Serial Boot Loader), two-way bidirectional multiplexer (Multiplexer) and standard SPI protocol interface, described self-starting serial boot program load-on module respectively with the input end I of two-way bidirectional multiplexer, cpu signal connects, the self-starting serial boot program load-on module also is connected with the external memory storage signal by standard SPI protocol interface, simultaneously, the input end II of two-way bidirectional multiplexer is connected with cpu signal, and the output terminal of two-way bidirectional multiplexer is connected with the RAM signal.
As shown in Figure 3, the self-starting serial boot program load-on module is made up of self-starting loaded circuit (SBL), mode of operation commutation circuit (SMC), SPI holotype circuit (SPIM), the mode of operation commutation circuit is connected with self-starting loaded circuit, SPI holotype circuit signal respectively, the mode of operation commutation circuit is communicated with self-starting loaded circuit or SPI holotype circuit as the case may be, to realize the working mode change of self-starting serial boot program load-on module.
Above-mentioned self-starting serial boot program loads the method that loads and read with reading system implementation algorithm program, comprises algorithm routine loading method and read method, and wherein, loading method specifically comprises the steps:
(1) after system powers on, mode of operation commutation circuit (SMC) the forbidding SPI holotype circuit (SPIM) in the self-starting serial boot program load-on module, and gating self-starting loaded circuit (SBL);
(2) self-starting loaded circuit (SBL) sends (RESET) signal that resets CPU is resetted (RESET), simultaneously, sends the input end I of gating control signal gating two-way bidirectional multiplexer (Multiplexer);
(3) self-starting loaded circuit (SBL) Control work mode switch circuit (SMC) reads algorithm routine in the outside SPI interface memory by standard SPI protocol interface, and the algorithm routine that is read is loaded in the internal program memory (RAM) through two-way bidirectional multiplexer (Multiplexer);
Read method specifically may further comprise the steps:
In A, the above-mentioned loading method step (3), when algorithm routine is loaded into after internal program memory (RAM) finishes, mode of operation commutation circuit (SMC) forbidding self-starting loaded circuit (SBL) in the self-starting serial boot program load-on module, and gating SPI holotype circuit (SPIM), make outside SPI interface memory in SPI holotype circuit (SPIM) connection;
B, self-starting loaded circuit (SBL) send the gating control signal and discharge CPU, make CPU enter normal operating condition, and simultaneously, self-starting loaded circuit (SBL) sends the input end II of gating control signal gating two-way bidirectional multiplexer (Multiplexer); Then, CPU reads algorithm routine in the internal program memory (RAM) by two-way bidirectional multiplexer (Multiplexer).
Among the said method step B, when CPU reads algorithm routine in the internal program memory (RAM) by two-way bidirectional multiplexer (Multiplexer) after, if CPU finds the code in the algorithm routine and comprises the visit again of the external SPI of portion interface memory, then control the algorithm routine that SPI holotype circuit (SPIM) secondary reads in the outside SPI interface memory the interior code of corresponding and algorithm routine that CPU reads, and the algorithm routine that secondary reads is loaded in the internal program memory (RAM) through two-way bidirectional multiplexer (Multiplexer) secondary, then, the CPU algorithm routine that secondary is loaded into internal program memory (RAM) by two-way bidirectional multiplexer (Multiplexer) carries out secondary and reads.
If the code in the algorithm routine that CPU discovery secondary reads comprises the visit again of the external SPI of portion interface memory, can circulate according to above-mentioned secondary loading and read method repeatedly loads and read operation.
As mentioned above, just can realize the utility model preferably.
Claims (3)
1, self-starting serial boot program loads and reading system, comprise system level chip and the external memory storage that is used for the storage algorithm program, system level chip comprises CPU, internal program memory, it is characterized in that: described external memory storage is outside SPI interface memory, described system level chip also comprises the self-starting serial boot program load-on module, two-way bidirectional multiplexer and standard SPI protocol interface, described self-starting serial boot program load-on module respectively with the input end I of two-way bidirectional multiplexer, cpu signal connects, the self-starting serial boot program load-on module also is connected with the external memory storage signal by standard SPI protocol interface, simultaneously, the input end II of two-way bidirectional multiplexer is connected with cpu signal, and the output terminal of two-way bidirectional multiplexer is connected with the RAM signal; Described self-starting serial boot program load-on module is made up of self-starting loaded circuit, mode of operation commutation circuit, SPI holotype circuit, and the mode of operation commutation circuit is connected with self-starting loaded circuit, SPI holotype circuit signal respectively.
2, load and reading system according to the described self-starting serial boot program of claim 1, it is characterized in that: described system level chip is SOC chip or dsp chip.
3, load and reading system according to the described self-starting serial boot program of claim 1, it is characterized in that: described outside SPI interface memory is SPI-EEPROM.
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| Application Number | Priority Date | Filing Date | Title |
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| CNU200820206679XU CN201359723Y (en) | 2008-12-31 | 2008-12-31 | Self-starting serial bootstrap program loading and reading system |
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| CNU200820206679XU CN201359723Y (en) | 2008-12-31 | 2008-12-31 | Self-starting serial bootstrap program loading and reading system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103336700A (en) * | 2013-06-09 | 2013-10-02 | 深圳市汇川技术股份有限公司 | Serial port burning circuit and system of digital signal processor (DSP) |
| CN109725941A (en) * | 2018-12-18 | 2019-05-07 | 深圳吉迪思电子科技有限公司 | A kind of programmable initial method and system for display driver chip |
| CN111459572A (en) * | 2020-03-31 | 2020-07-28 | 深圳市汇顶科技股份有限公司 | Program loading method, controller, chip and electronic equipment |
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2008
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103336700A (en) * | 2013-06-09 | 2013-10-02 | 深圳市汇川技术股份有限公司 | Serial port burning circuit and system of digital signal processor (DSP) |
| CN103336700B (en) * | 2013-06-09 | 2016-08-10 | 深圳市汇川技术股份有限公司 | The serial ports programming circuitry of a kind of digital signal processor and system |
| CN109725941A (en) * | 2018-12-18 | 2019-05-07 | 深圳吉迪思电子科技有限公司 | A kind of programmable initial method and system for display driver chip |
| CN111459572A (en) * | 2020-03-31 | 2020-07-28 | 深圳市汇顶科技股份有限公司 | Program loading method, controller, chip and electronic equipment |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091209 Termination date: 20131231 |