CN201355244Y - Data acquisition circuit of ultrasonic ice melting sensor - Google Patents

Abstract

The utility model discloses a data acquisition circuit of an ultrasonic ice melting sensor, which belongs to the field of ultrasonic measurement technology, and relates to an improved ultrasonic ice melting sensor which is used to detect the surface ice thickness of an airplane. The data acquisition circuit of an ultrasonic ice melting sensor comprises a DSP[1] and a clock circuit [5], and is characterized in that the data acquisition circuit consists of the DSP [1], the clock circuit [5], a differential amplifier circuit [2], a first A/D drive circuit [3], a second A/D drive circuit [4], a first A/D conversion circuit [6], a second A/D conversion circuit [7] and four cache memory circuits. The data acquisition circuit of an ultrasonic ice melting sensor adopts the parallel sampling and cache memory circuits, thereby reducing the sampling and cache memory working efficiency, and greatly reducing the cost of the whole ultrasonic ice melting sensor.

Description

Ultrasound wave ice-melt sensor data acquisition circuit

Technical field

The utility model belongs to supersonic technique, relates to the improvement to the ultrasound wave ice-melt sensor that is used for the icing thickness in hunter surface.

Background technology

Ultrasound wave ice-melt sensor is the sniffer that is used for detecting the icing thickness of aviation aircraft (fixed-wing, rotor and special device).In aircraft was executed the task process, ultrasound wave ice-melt sensor may run into gas velocity 180m/s, temperature-30 ℃, liquid water content 1.25g/m ³Icing environment, when ultrasonic probe surface froze, ultrasound wave can be returned in two surface reflections of ice sheet, as long as obtain the time interval of twice ultrasonic echo signal, just ultrasound wave travel-time in ice, just can calculate icing thickness.Use high-speed a/d converter to carry out the A/D conversion in the present ultrasound wave ice-melt sensor, because costing an arm and a leg of high-speed a/d converter and buffer improved the cost of whole ultrasonic ripple ice-melt sensor.

Summary of the invention

The purpose of this utility model is: provide a kind of ice-melt of ultrasound wave cheaply sensor data acquisition circuit, to reduce the cost of whole ultrasonic ripple ice-melt sensor.

The technical solution of the utility model is: ultrasound wave ice-melt sensor data acquisition circuit, comprise a DSP and a clock circuit, it is characterized in that data acquisition circuit is made up of DSP, clock circuit, differential amplifier circuit, an A/D driving circuit, the 2nd A/D driving circuit, an A/D change-over circuit, the 2nd A/D change-over circuit and four buffer circuits; Four buffer circuits are first buffer circuit, second buffer circuit, the 3rd buffer circuit and the 4th buffer circuit; The signal input part of ultrasonic echo signal input difference amplifying circuit, the signal output part of differential amplifier circuit is connected with the signal input part of an A/D driving circuit and the 2nd A/D driving circuit respectively, the signal output part of the one A/D driving circuit is connected with the signal input part of an A/D change-over circuit, the signal output part of the one A/D change-over circuit is connected with the digital signal input end of first buffer circuit with second buffer circuit respectively, the signal output part of the 2nd A/D driving circuit is connected with the signal input part of the 2nd A/D change-over circuit, the signal output part of the 2nd A/D change-over circuit is connected with the digital signal input end of the 3rd buffer circuit with the 4th buffer circuit respectively, first buffer circuit, second buffer circuit, the digital signal output end of the 3rd buffer circuit and the 4th buffer circuit is connected with the data bus of DSP by bus respectively, the cache control signal output terminal of DSP is connected with the cache control signal input end of first buffer circuit, the cache control signal output terminal of first buffer circuit is connected with the cache control signal input end of second buffer circuit, the cache control signal output terminal of second buffer circuit is connected with the cache control signal input end of the 3rd buffer circuit, and the cache control signal output terminal of the 3rd buffer circuit is connected with the cache control signal input end of the 4th buffer circuit; 0 degree clock signal output terminal of clock circuit is connected with the clock signal input terminal of an A/D change-over circuit, and 180 degree clock signal output terminals of clock circuit are connected with the clock signal input terminal of the 2nd A/D change-over circuit.

The utility model has the advantages that: adopt parallel sampling and buffer circuit, reduced the frequency of operation of sampling and buffer memory, thereby greatly reduced the cost of whole ultrasonic ripple ice-melt sensor.

Description of drawings

Fig. 1 is a structural principle block diagram of the present utility model.

Embodiment

Below the utility model is described in further details.Referring to Fig. 1, ultrasound wave ice-melt sensor data acquisition circuit, comprise a DSP1 and a clock circuit 5, it is characterized in that data acquisition circuit is made up of DSP1, clock circuit 5, differential amplifier circuit 2, an A/D driving circuit 3, the 2nd A/D driving circuit 4, an A/D change-over circuit 6, the 2nd A/D change-over circuit 7 and four buffer circuits; Four buffer circuits are that FIFO is first buffer circuit 8, second buffer circuit 9, the 3rd buffer circuit 10 and the 4th buffer circuit 11; The signal input part of ultrasonic echo signal input difference amplifying circuit 2, the signal output part of differential amplifier circuit 2 is connected with the signal input part of an A/D driving circuit 3 and the 2nd A/D driving circuit 4 respectively, the signal output part of the one A/D driving circuit 3 is connected with the signal input part of an A/D change-over circuit 6, the signal output part of the one A/D change-over circuit 6 is connected with the digital signal input end of first buffer circuit 8 and second buffer circuit 9 respectively, the signal output part of the 2nd A/D driving circuit 4 is connected with the signal input part of the 2nd A/D change-over circuit 7, the signal output part of the 2nd A/D change-over circuit 7 is connected with the digital signal input end of the 3rd buffer circuit 10 and the 4th buffer circuit 11 respectively, first buffer circuit 8, second buffer circuit 9, the digital signal output end of the 3rd buffer circuit 10 and the 4th buffer circuit 11 is connected with the data bus of DSP1 by bus respectively, the cache control signal output terminal of DSP1 is connected with the cache control signal input end of first buffer circuit 8, the cache control signal output terminal of first buffer circuit 8 is connected with the cache control signal input end of second buffer circuit 9, the cache control signal output terminal of second buffer circuit 9 is connected with the cache control signal input end of the 3rd buffer circuit 10, and the cache control signal output terminal of the 3rd buffer circuit 10 is connected with the cache control signal input end of the 4th buffer circuit 11; 0 degree clock signal output terminal of clock circuit 5 is connected with the clock signal input terminal of an A/D change-over circuit 6, and 180 degree clock signal output terminals of clock circuit 5 are connected with the clock signal input terminal of the 2nd A/D change-over circuit 7.

Principle of work of the present utility model is: the ultrasonic echo signal carries out difference by differential amplifier circuit 2 earlier and amplifies, amplifying signal is become differential signal, import the output signal of two A/D driving circuits 3 and 4, two A/D driving circuits 3 and 4 then and import 2 A/D change-over circuits 6 and 7 more respectively.The differential signal of importing in the circuit arrives the input end of every A/D change-over circuit simultaneously, 2 A/D change-over circuit alternating samplings, and the sample frequency of each A/D change-over circuit drops to 1/2 of sum frequency.The clock signal that clock circuit produces is divided into two-way, one the tunnel directly enters first A/D convertor circuit 6, another road clock signal enters second A/D convertor circuit 7 after spending through reverse 180 again, make the phase difference of half cycle in sampling time of two A/D convertor circuits, promptly to make the frequency of whole sample circuit be 2 times of single A/D convertor circuit in two A/D change-over circuits last lower edge of being operated in clock respectively.Each A/D convertor circuit adopts the structure of two-way output simultaneously, and 2 clocks inverting each other are provided simultaneously, and two A/D convertor circuits divide 4 passage output datas, and the frequency of each passage is 1/4 of a sum frequency.DSP controls writing and reading of 4 buffer circuits by the cache control signal of output, and reading clock is provided by DSP.DSP reads 4 data in the buffer circuit piecewise successively, and all data that read all deposit the storer of DSP inside in.

Among the embodiment of the present utility model, differential amplifier circuit adopts AD620, and the A/D driving circuit adopts AD8138, and the A/D change-over circuit adopts AD9481, and clock circuit adopts SY89429A, and 4 buffer circuits adopt the CY7C4245 chip.

Claims (1)

1, ultrasound wave ice-melt sensor data acquisition circuit, comprise a DSP[1] and a clock circuit [5], it is characterized in that data acquisition circuit is by DSP[1], clock circuit [5], differential amplifier circuit [2], an A/D driving circuit [3], the 2nd A/D driving circuit [4], an A/D change-over circuit [6], the 2nd A/D change-over circuit [7] and four buffer circuits form; Four buffer circuits are first buffer circuit [8], second buffer circuit [9], the 3rd buffer circuit [10] and the 4th buffer circuit [11]; The signal input part of ultrasonic echo signal input difference amplifying circuit [2], the signal output part of differential amplifier circuit [2] is connected with the signal input part of an A/D driving circuit [3] and the 2nd A/D driving circuit [4] respectively, the signal output part of the one A/D driving circuit [3] is connected with the signal input part of an A/D change-over circuit [6], the signal output part of the one A/D change-over circuit [6] is connected with the digital signal input end of first buffer circuit [8] with second buffer circuit [9] respectively, the signal output part of the 2nd A/D driving circuit [4] is connected with the signal input part of the 2nd A/D change-over circuit [7], the signal output part of the 2nd A/D change-over circuit [7] is connected with the digital signal input end of the 3rd buffer circuit [10] with the 4th buffer circuit [11] respectively, first buffer circuit [8], second buffer circuit [9], the digital signal output end of the 3rd buffer circuit [10] and the 4th buffer circuit [11] is respectively by bus and DSP[1] data bus be connected, DSP[1] the cache control signal output terminal be connected with the cache control signal input end of first buffer circuit [8], the cache control signal output terminal of first buffer circuit [8] is connected with the cache control signal input end of second buffer circuit [9], the cache control signal output terminal of second buffer circuit [9] is connected with the cache control signal input end of the 3rd buffer circuit [10], and the cache control signal output terminal of the 3rd buffer circuit [10] is connected with the cache control signal input end of the 4th buffer circuit [11]; 0 degree clock signal output terminal of clock circuit [5] is connected with the clock signal input terminal of an A/D change-over circuit [6], and 180 degree clock signal output terminals of clock circuit [5] are connected with the clock signal input terminal of the 2nd A/D change-over circuit [7].