CN201327637Y - Embedded system starter and embedded equipment equipped with same - Google Patents
Embedded system starter and embedded equipment equipped with same Download PDFInfo
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- CN201327637Y CN201327637Y CNU200820235843XU CN200820235843U CN201327637Y CN 201327637 Y CN201327637 Y CN 201327637Y CN U200820235843X U CNU200820235843X U CN U200820235843XU CN 200820235843 U CN200820235843 U CN 200820235843U CN 201327637 Y CN201327637 Y CN 201327637Y
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- flash memory
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- main system
- memory
- starter gear
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Abstract
The utility model relates to an embedded system starter used for the startup of a main system. The main system comprises a main processor and a memory. The main system also comprises a first flash memory for the storage of a bootstrap program, an operating system nucleus and a basic file system, and a second flash memory for the storage of system program; the first flash memory and the second flash memory are respectively connected with the main processor. The first flash memory is a negater flash memory. The utility model can achieve the quick start for the embedded system with huge data size with less increased cost through the two flash memories.
Description
Technical field
The utility model relates to starter gear, more particularly, relates to a kind of starter gear that uses flash memory.
Background technology
Rejection gate flash memory (being NOR FLASH) belongs to the non-volatility memory of linear addressing, microprocessor can directly be carried out the program in the flash memory, and do not need earlier program to be read in the systematic memory body, use relatively easily, therefore most of in the market embedded OSs are all with the media of rejection gate flash memory as the guidance system start.Yet the storage density of rejection gate flash memory is lower and cost an arm and a leg, so can't use the rejection gate flash memory to store the bigger file of data volume.
Along with the progressively raising of embedded system function, the data volume of startup file increases gradually, uses the rejection gate flash memory no longer can satisfy the system start-up demand merely.
The equipment that data-handling capacities such as existing computing machine are stronger generally adopts hard disk startup.When adopting hard disk startup because the data reading speed of hard disk is slower, so equipment to finish time of startup long, correspondingly, the time that the user waits for is also longer relatively.In addition, reading hard disk is also to be accompanied by bigger noise.And in the time of for frequent switching on and shutting down or unexpected switching on and shutting down, be easy to damage hard disk, obliterated data.
The utility model content
The technical problems to be solved in the utility model is, can't satisfy the startup file of big data quantity and hard disk startup speed is slow and defective that damage easily at above-mentioned rejection gate flash memory, provide that a kind of toggle speed is fast, the embedded system starter gear of stable performance and have the embedded device of this device.
The technical scheme that its technical matters that solves the utility model adopts is: construct a kind of embedded system starter gear, be used to realize the startup of main system, described main system comprises primary processor and internal memory, also comprise first flash memory that stores boot, operating system nucleus and basic file system and second flash memory that stores system program, described first flash memory and second flash memory are connected respectively to primary processor, and wherein said first flash memory is the rejection gate flash memory.
In embedded system starter gear described in the utility model, the data reading speed of described first flash memory is greater than the data reading speed of described second flash memory.
In embedded system starter gear described in the utility model, described second flash memory is the Sheffer stroke gate flash memory.
Be connected to the address signal line of main system at first flash memory described in the embedded system starter gear described in the utility model by 24 bit address lines, and be connected to the data signal line of main system by 16 position datawires.
In embedded system starter gear described in the utility model, described first flash memory connects the chip selection signal line of chip selection signal to main system.
In embedded system starter gear described in the utility model, described second flash memory is connected to primary processor by usb bus.
The utility model also provides a kind of embedded device with above-mentioned embedded system starter gear, comprise main system with primary processor and internal memory, also comprise first flash memory that stores boot, operating system nucleus and basic file system and second flash memory that stores system program, described first flash memory and second flash memory are connected respectively to primary processor, and the memory capacity of wherein said second flash memory is greater than the memory capacity of described first flash memory.
In embedded device described in the utility model, described first flash memory is the rejection gate flash memory, and described second flash memory is the Sheffer stroke gate flash memory.
In embedded device described in the utility model, described main system also comprises the hard disk that is connected to primary processor.
In embedded device described in the utility model, described first flash memory is connected to the address signal line of main system by 24 bit address lines, and being connected to the data signal line of main system by 16 position datawires, described second flash memory is connected to primary processor by usb bus.
Implement embedded system starter gear of the present utility model and embedded device, have following beneficial effect:, increase the quick startup that less cost can realize the embedded system that data volume is bigger by two flash memories with this device.Because the utility model adopts flash memory to start, in the time of for frequent switching on and shutting down or unexpected switching on and shutting down, it is stable that its performance also keeps.
Description of drawings
The utility model is described in further detail below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the structural representation of the utility model embedded system starter gear embodiment;
Fig. 2 is the structural representation of first flash memory among Fig. 1;
Fig. 3 is the circuit diagram of first flash memory among Fig. 1;
Fig. 4 is the circuit diagram of second flash memory among Fig. 1.
Embodiment
This embedded system starter gear is used to realize the startup of main system, wherein this main system is an embedded system, the more common DVD of its data-handling capacity, VCD player etc. are powerful, therefore the log-on data amount of its system is also relatively large, and the common DVD or the Starting mode of VCD player are no longer suitable.Certainly, starter gear of the present utility model also can be applicable to complicated more data handling system (for example non-embedded system).
As shown in Figure 1, embedded system starter gear of the present utility model.Include main system 10, first flash memory 13 and second flash memory 14 in this device, wherein main system 10 includes primary processor 11, internal memory 12 and hard disk (not shown) etc.First flash memory 13 and second flash memory 14 are connected respectively to primary processor 11 (for example by expansion bus etc.).
In the present embodiment, the memory capacity of second flash memory 14 is greater than the memory capacity of first flash memory 13.And the data reading speed of first flash memory 13 is greater than the data reading speed of second flash memory 14.Especially, above-mentioned first flash memory 13 is rejection gate flash memory (NORFLASH), and second flash memory 14 is Sheffer stroke gate flash memory (NAND FLASH).By these two flash memories 13,14, not only realized the quick startup of the main system that the log-on data amount is bigger, and can adapt to frequent switching on and shutting down operation, improper outage etc.Certain second flash memory also can be the flash memory of other types.
As shown in Figure 2, in an embodiment of first flash memory 13, its memory capacity is 8M (in actual applications, being not limited to 8M).Store boot, operating system nucleus and basic file system etc. in this first flash memory 13.When this first flash memory 13 was the rejection gate flash memory, data wherein need not to be written into main system memory when system start-up, used relatively easy.
Especially, data can be solidificated in above-mentioned first flash memory 13, promptly the data in first flash memory 13 can not be revised, thereby reduce the fault probability of the main system of knowing clearly.
The capacity of second flash memory 14 relatively large (for example can be 2G) wherein stores system program.Under the situation that memory capacity is had more than needed, also can store upgrade file in second flash memory 14, be used for data etc.
Main system is when starting, flow process is as follows: main system 10 is written into the boot in first flash memory 13 behind the power-up initializing, the loading start-up picture also outputs on the terminal presentation facility, be written into embedded operating system kernel then, and the master routine in the loading basic file system and second flash memory 14, finish start-up course.
As shown in Figure 3, be the electrical block diagram of first flash memory 13 among Fig. 1.U9 among the figure is first flash memory (NOR FLASH), it is connected to main system address signal line [Exp ADDR1-24] by 24 bit address lines [A1～A24], and is connected to main system data signal wire [Exp DATA0-15] by 16 position datawires [DQ0～DQ16].The output of U9 (OE#) and write control (WE#) and be connected respectively to reading (RD#) and writing (WR#) signal wire of main system in addition.This U9 connects chip selection signal (CE#) and arrives the main system reseting signal line to main system chip selection signal line, connection reset signal (RST#).
As shown in Figure 4, be the electrical block diagram of second flash memory 14 among Fig. 1.U50 is the USB control chip among the figure, and itself and storage chip U51 have constituted second flash memory (NANDFLASH) jointly.This second flash memory is connected to primary processor by usb bus.The chip selection signal of storage chip U51 is connected to the chip selection signal line of USB control chip U50.
Above-mentioned embedded system starter gear may be used in the multiclass embedded device.The embedded device that has above-mentioned embedded system starter gear comprises main system with primary processor and internal memory, store first flash memory of boot, operating system nucleus and basic file system and store second flash memory of system program, first flash memory and second flash memory are connected respectively to primary processor, wherein first flash memory is the rejection gate flash memory, and second flash memory is the Sheffer stroke gate flash memory.
The above; it only is the preferable embodiment of the utility model; but protection domain of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; the variation that can expect easily or replacement all should be encompassed within the protection domain of the present utility model.Therefore, protection domain of the present utility model should be as the criterion with the protection domain of claim.
Claims (10)
1, a kind of embedded system starter gear, be used to realize the startup of main system, described main system comprises primary processor and internal memory, it is characterized in that, also comprise first flash memory that stores boot, operating system nucleus and basic file system and second flash memory that stores system program, described first flash memory and second flash memory are connected respectively to primary processor, and wherein said first flash memory is the rejection gate flash memory.
2, embedded system starter gear according to claim 1 is characterized in that, the data reading speed of described first flash memory is greater than the data reading speed of described second flash memory.
3, according to any one described embedded system starter gear in claim 1 or 2, it is characterized in that described second flash memory is the Sheffer stroke gate flash memory.
4, embedded system starter gear according to claim 3 is characterized in that, described first flash memory is connected to the address signal line of main system by 24 bit address lines, and is connected to the data signal line of main system by 16 position datawires.
5, embedded system starter gear according to claim 3 is characterized in that, the described first flash memory chip selection signal is connected to the chip selection signal line of main system.
6, embedded system starter gear according to claim 3 is characterized in that, described second flash memory is connected to primary processor by usb bus.
7, a kind of embedded device with embedded system starter gear according to claim 1, comprise main system with primary processor and internal memory, it is characterized in that, also comprise first flash memory that stores boot, operating system nucleus and basic file system and second flash memory that stores system program, described first flash memory and second flash memory are connected respectively to primary processor, and the memory capacity of wherein said second flash memory is greater than the memory capacity of described first flash memory.
8, embedded device according to claim 7 is characterized in that, described first flash memory is the rejection gate flash memory, and described second flash memory is the Sheffer stroke gate flash memory.
9, according to claim 7 or 8 described embedded devices, it is characterized in that described main system also comprises the hard disk that is connected to primary processor.
10, embedded device according to claim 9, it is characterized in that, described first flash memory is connected to the address signal line of main system by 24 bit address lines, and being connected to the data signal line of main system by 16 position datawires, described second flash memory is connected to primary processor by usb bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200820235843XU CN201327637Y (en) | 2008-12-26 | 2008-12-26 | Embedded system starter and embedded equipment equipped with same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200820235843XU CN201327637Y (en) | 2008-12-26 | 2008-12-26 | Embedded system starter and embedded equipment equipped with same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201327637Y true CN201327637Y (en) | 2009-10-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU200820235843XU Expired - Fee Related CN201327637Y (en) | 2008-12-26 | 2008-12-26 | Embedded system starter and embedded equipment equipped with same |
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| CN (1) | CN201327637Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102141945A (en) * | 2010-02-02 | 2011-08-03 | 余俊德 | Computer system with built-in flash memory standby operating units and method thereof |
| CN102117245B (en) * | 2010-01-06 | 2014-07-02 | 浙江德景电子科技有限公司 | Embedded device and method for loading and starting operation of cutting system executable file thereof |
-
2008
- 2008-12-26 CN CNU200820235843XU patent/CN201327637Y/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102117245B (en) * | 2010-01-06 | 2014-07-02 | 浙江德景电子科技有限公司 | Embedded device and method for loading and starting operation of cutting system executable file thereof |
| CN102141945A (en) * | 2010-02-02 | 2011-08-03 | 余俊德 | Computer system with built-in flash memory standby operating units and method thereof |
| CN102141945B (en) * | 2010-02-02 | 2013-04-17 | 余俊德 | Computer system with built-in flash memory standby operating units and method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091014 Termination date: 20141226 |
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| EXPY | Termination of patent right or utility model |