CN201311933Y

CN201311933Y - Capacitor

Info

Publication number: CN201311933Y
Application number: CNU2008201551209U
Authority: CN
Inventors: 黄威森; 钱蔚宏; 程仁豪; 包自意
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Beijing Corp
Priority date: 2008-11-10
Filing date: 2008-11-10
Publication date: 2009-09-16
Anticipated expiration: 2018-11-10

Abstract

Disclosed is a capacitor, which comprises a first electrode and a second electrode, wherein the first electrode further includes an E-shaped structure and a linear structure connected with a middle transverse line of the E-shaped structure. The linear structure is connected with the middle transverse line of the E-shaped structure in a T shape and the second electrode is mutually intersected with the E-shaped structure and enwraps the E-shaped structure of the first electrode. The capacitor can be formed into an array type capacitor or a stack type capacitor, thereby a comparatively large capacitance can be achieved and an arrangement area can be saved by applying the capacitor, the array type capacitor or the stack type capacitor.

Description

Capacitor

Technical field

The utility model relates to semiconductor technology, particularly relates to a kind of capacitor.

Background technology

Capacitor is to be made of two very near metal electrodes of being separated by again insulated from each other, and it is widely used in the integrated circuits such as analog circuit, hybrid circuit.In semiconductor integrated circuit, common capacitor has metal-insulator-metal type (MIM, Metal-Insulator-Metal) capacitor, metal-oxide-metal (MOM, Metal-Oxide-Metal) capacitor.

Along with the integrated circuit microminiaturization, capacitor is also microminiaturized thereupon, so just produced problem how to guarantee enough capacitances, at present in semiconductor integrated circuit technique, stacked (stacked) capacitor can increase capacitance under the situation of saving layout area, for example, application number is that stacked MIM capacitor and stacked MOM capacitor have been introduced in 200310109110.3 and 200710145334.8 Chinese invention patent application respectively.

Figure 1A is the floor map of the layout structure of existing a kind of capacitor, shown in capacitor 10 comprise first electrode 11 and second electrode 12, wherein, the layout figure of first electrode 11 is the combination of pectinate texture and T type structure, the layout figure of second electrode is the combination of T type structure, and the T type structure of the pectinate texture of first electrode 11, T type structure and second electrode 12 is interlaced.

Metal-layer structure by inter-level interconnects can be formed stacked capacitor with the capacitor shown in Figure 1A 10, to obtain bigger capacitance.Fig. 2 A is a kind of side schematic view of stacked capacitor, with the capacitor that is formed by seven layers of metal level M1～M7 is example, shown in stacked capacitor comprise: be connected through hole (Via) V11～V16, the V21～V26 of two metal layers up and down among the metal level M1～M7, interlayer dielectric layer D1～D6 and interlayer dielectric layer D1～D6.Wherein, every layer of metal level comprises the capacitor 10 shown in Figure 1A, first electrode 11 of capacitor 10, second electrode 12 are represented with

symbol

1,2 respectively in Fig. 2 A, first electrode 1 of the capacitor 10 of each layer metal level electrically connects by the metal that is filled among through hole V11～V16, second electrode 2 electrically connects by the metal that is filled among through hole V21～V26, and the capacitor 10 with each layer metal level is connected in parallel thus.

Fig. 2 B is the side schematic view of another kind of stacked capacitor, same is example with the capacitor that is formed by seven layers of metal level M1～M7, shown in stacked capacitor comprise: through hole (Via) V11 '～V16 ', the V21 '～V26 ' of two metal layers about being connected among the metal level M1 '～M7 ', interlayer dielectric layer D1 '～D6 ' and interlayer dielectric layer D1 '～D6 '.Wherein, metal level M1 ', M3 ', M5 ', M7 ' comprise the capacitor 10 shown in Figure 1A respectively, and first electrode 11 of capacitor 10, second electrode 12 are represented with

symbol

1,2 respectively in Fig. 2 A; Metal level M2 ', M4 ', M6 ' comprise the capacitor 10 ' shown in Figure 1B respectively, the layout structure of capacitor 10 ' is that the layout structure of capacitor 10 obtains through flip horizontal, first electrode 11 ' of capacitor 10 ', second electrode 12 ' are represented with symbol 1 ', 2 ' respectively in Fig. 2 B, that is to say that the capacitor 10 ' shown in the capacitor 10 shown in Figure 1A and Figure 1B is staggeredly stacked.Second electrode 2 ' of the capacitor 10 ' of first electrode 1 of the capacitor 10 of metal level M1 ', M3 ', M5 ', M7 ' by being filled in metal among through hole V11 '～V16 ' and metal level M2 ', M4 ', M6 ' electrically connects, first electrode 1 ' of the capacitor 10 ' of second electrode 2 of the capacitor 10 of metal level M1 ', M3 ', M5 ', M7 ' by being filled in metal among through hole V21 '～V26 ' and metal level M2 ', M4 ', M6 ' electrically connects, and the capacitor 10,10 ' with each layer metal level is connected in parallel thus.

For plane-parallel capacitor, the capacitance of capacitor is directly proportional with the dielectric constant over against area, medium between two electrodes, is inversely proportional to two distance between electrodes.Therefore, under the situation of identical topology area, between two electrodes of increase capacitor is a kind of capacitance that improves unit are over against area, thereby improves the effective ways of the capacitance of capacitor.

The utility model content

The problem that the utility model solves is, a kind of capacitor is provided, with between two electrodes that increase capacitor over against area, thereby improve the capacitance of capacitor.

For addressing the above problem, the utility model execution mode provides a kind of capacitor, comprise first electrode and second electrode, described first electrode comprises the linear structure of E shape structure and the middle horizontal line that is connected described E shape structure, and the middle horizontal line of described linear structure and described E shape structure constitutes T shape; The E shape structure of described second electrode and first electrode is interlaced, and surrounds the E shape structure of described first electrode.

For addressing the above problem, the utility model execution mode also provides a kind of capacitor, comprise first electrode and second electrode, described first electrode comprises an E shape structure and the 2nd E shape structure that vertical line overlaps, and the linear structure that connects the middle horizontal line of a described E shape structure, the 2nd E shape structure, the middle horizontal line of a described linear structure and a described E shape structure, the 2nd E shape structure constitutes T shape; The one E shape structure, the 2nd E shape structure of described second electrode and first electrode are interlaced, and the E shape structure of surrounding described first electrode.

For addressing the above problem, the utility model execution mode also provides a kind of array type capacitor, comprises M*N above-mentioned capacitor, and a described M*N capacitor arrangement becomes the matrix of the capable N row of M, and wherein, the adjacent electrode of neighboring capacitors links together.

For addressing the above problem, the utility model execution mode also provides a kind of multilayer capacitor, comprises two metal layers at least, and wherein, each metal level comprises above-mentioned capacitor respectively.

Compared with prior art, technique scheme has changed the layout structure of two electrodes of capacitor, and wherein, an electrode is a primary structure with E shape, another electrode is around the E shape structure of described first electrode, with this increased between two electrodes over against area.Under the situation that layout area is determined, technique scheme can obtain the capacitance of higher unit are; Under the situation that capacitance is determined, technique scheme is saved layout area.

Description of drawings

Figure 1A and 1B are the floor map of the layout structure example of existing capacitor;

Fig. 2 A and 2B are the side schematic views of stacked capacitor example;

Fig. 3 A to 3C is the floor map of layout structure example of the capacitor of the utility model execution mode 1;

Fig. 4 A and 4B are the floor map of layout structure example of the capacitor of the utility model execution mode 2;

Fig. 5 is the floor map of layout structure example of the array type capacitor of the utility model execution mode 3.

Embodiment

The utility model execution mode is by first electrode that changes capacitor, the layout structure of second electrode, so that increasing over against area between two electrodes, thereby reaches the purpose of the capacitance that improves capacitor.Below in conjunction with drawings and Examples the utility model execution mode is elaborated.

Execution mode 1

The capacitor of present embodiment comprises: first electrode and second electrode, and wherein, described first electrode comprises the linear structure of E shape structure and the middle horizontal line that is connected described E shape structure, the middle horizontal line of described linear structure and described E shape structure constitutes T shape; The E shape structure of described second electrode and first electrode is interlaced, and surrounds the E shape structure of described first electrode.

Fig. 3 A is the floor map of a layout structure example of the capacitor of present embodiment, shown in capacitor 30 comprise: first electrode 31, second electrode 32 and be filled in first electrode 31 and second electrode 32 between dielectric.Shown in first electrode 31, second electrode 32 of capacitor 30 be formed on the layer of metal layer.

First electrode 31 comprises E shape structure 31a and linear structure 31b.E shape structure 31a comprises vertical line, goes up horizontal line, middle horizontal line and following horizontal line.Linear structure 31b is connected with the middle horizontal line of E shape structure 31a, and constitutes T shape with the middle horizontal line of E shape structure 31a.Linear structure 31b is relative with the opening of E shape structure 31a, linear structure 31b comprises vertical curve 311b and connecting line 312b, wherein, connecting line 312b connects the middle horizontal line of vertical curve 311b and E shape structure 31a, be the middle horizontal line that linear structure 31b only connects E shape structure 31a, and do not connect the vertical line of E shape structure 31a.

Second electrode 32 is inserted in the space of first electrode 31, and around the E shape structure 31a of first electrode 31; Formation is interlaced with the E shape structure 31a of first electrode 31 thus, and the structure of surrounding the E shape structure 31a of described first electrode 31.

As shown in Figure 3A, the live width w1 of first electrode 31 can equal the live width w2 of second electrode 32, also can be not equal to the live width w2 of second electrode 32, and the value of live width w1, w2 should be more than or equal to the minimum feature of design rule definition.Distance (being distance between centers of tracks) d between first electrode 31 and second electrode 32 equates that throughout its value is generally the minimum line distance of design rule definition.Distance (being distance between centers of tracks) between first electrode 31 and second electrode 32 also can be unequal throughout, but can increase the complexity of calculating capacitance like this.

First electrode 31 and second electrode 32 are insulated medium and separate, and have promptly filled dielectric in the gap of first electrode 31 and second electrode 32, first electrode 31, second electrode 32 and be filled in two dielectrics between the electrode and constitute capacitors 30.Capacitor 30 can be a MIM capacitor, it also can be the MOM capacitor, first electrode 31, second electrode 32 can be copper (Cu), aluminium electric conducting materials such as (Al), for MIM capacitor, the dielectric that is filled between first electrode 31 and second electrode 32 can be silicon nitride (SiN), silica (SiO ₂) wait the insulator dielectric material; For the MOM capacitor, the dielectric that is filled between first electrode 31 and second electrode 32 can be SiO ₂, aluminium oxide (Al ₂O ₃) wait the medium of oxides material.

Capacitor 30 is a plane-parallel capacitor, and its capacitance is directly proportional with the dielectric constant over against area, medium between two electrodes, is inversely proportional to two distance between electrodes.First electrode 31 of capacitor 30 shown in Fig. 3 A is based on E shape structure, and second electrode 32 is around the E shape structure of first electrode 31, thereby bigger over against area between first electrode 31 and second electrode 32, can obtain bigger capacitance.Two of capacitor 30 electrodes shown in Fig. 3 A be called coupling area again over against area, therefore, the capacitor 30 of formation is a coupling capacitance.

Fig. 3 B is the floor map of another layout structure example of the capacitor of present embodiment, shown in capacitor 30 ' comprising: first electrode 31 ', second electrode 32 ' and be filled in first electrode 31 ' and second electrode 32 ' between dielectric.With reference to Fig. 3 A and 3B, the layout structure of capacitor 30 ' shown in Fig. 3 B is that the layout structure of capacitor 30 shown in Fig. 3 A obtains through the first direction upset, described first direction is vertical with the vertical line direction of the E shape structure 31a of first electrode 31, is horizontal direction in the diagram.The structure of first electrode 31 ' of capacitor 30 ' is identical with the structure of first electrode 31 of capacitor 30, and the structure of second electrode 32 ' of capacitor 30 ' is identical with the structure of second electrode 32 of capacitor 30, in this no longer repeat specification.

Fig. 3 C is the floor map of another layout structure example of the capacitor of present embodiment, shown in capacitor 30 " comprising: first electrode 31 ", second electrode 32 " and be filled in first electrode 31 " and second electrode 32 " between dielectric.

First electrode 31 " comprise E shape structure 31a " and linear structure 31b ".E shape structure 31a " comprise vertical line, go up horizontal line, middle horizontal line and following horizontal line.Linear structure 31b " with E shape structure 31a " middle horizontal line constitute T shape, different with first electrode 31 shown in Fig. 3 A is: first electrode 31 " linear structure 31b " connect E shape structure 31a " and middle horizontal line and vertical line; and the linear structure 31b of first electrode 31 only connects the middle horizontal line of E shape structure 31a, and does not connect the vertical line of E shape structure 31a.Specifically, linear structure 31b " comprise vertical curve 311b " and connecting line 312b ", wherein, connecting line 312b " connect vertical curve 311b " and E shape structure 31a " vertical line and middle horizontal line.

Second electrode 32 " with first electrode 31 " E shape structure 31a " interlaced, and surround first electrode 31 " E shape structure 31a ".Because first electrode 31 " structure different with the structure of first electrode 31 shown in Fig. 3 A, therefore, second electrode 32 " structure be different from the structure of second electrode 32 shown in Fig. 3 A.

Capacitor 30 shown in Fig. 3 C " layout structure also can obtain the layout structure of symmetry with it through first direction upset, described first direction is vertical with the vertical line direction of the E shape structure of first electrode, the horizontal direction in promptly illustrating.

Execution mode 2

The capacitor of present embodiment comprises: first electrode and second electrode, wherein, described first electrode comprises an E shape structure and the 2nd E shape structure that vertical line overlaps, and the linear structure that connects the middle horizontal line of a described E shape structure, the 2nd E shape structure, the middle horizontal line of a described linear structure and a described E shape structure, the 2nd E shape structure constitutes T shape; The one E shape structure, the 2nd E shape structure of described second electrode and first electrode are interlaced, and the E shape structure of surrounding described first electrode.

The difference of present embodiment and execution mode 1 is: first electrode of present embodiment comprises two E shape structures, and first electrode of execution mode 1 comprises an E shape structure.

Fig. 4 A is the floor map of a layout structure example of the capacitor of present embodiment, shown in capacitor 40 comprise: first electrode 41, second electrode 42 and be filled in first electrode 41 and second electrode 42 between dielectric.Shown in first electrode 41, second electrode 42 of capacitor 40 be formed on the layer of metal layer.

First electrode 41 comprises an E shape structure 41a, the 2nd E shape structure 41b and linear structure 41c.The one E shape structure 41a comprises vertical line, goes up horizontal line, middle horizontal line and following horizontal line, and the 2nd E shape structure 41b also comprises vertical line, goes up horizontal line, middle horizontal line and following horizontal line; The vertical line of the one E shape structure 41a overlaps with the vertical line of the 2nd E shape structure 41b, thus the last horizontal line of an E shape structure 41a and the last horizontal line of the 2nd E shape structure 41b are connected in line, the middle horizontal line of the one E shape structure 41a and the middle horizontal line of the 2nd E shape structure 41b are connected in line, and the following horizontal line of an E shape structure 41a and the following horizontal line of the 2nd E shape structure 41b are connected in line.Linear structure 41c connects the middle horizontal line of an E shape structure 41a, the 2nd E shape structure 41b, and constitutes T shape with the middle horizontal line of an E shape structure 41a, the 2nd E shape structure 41b.

Second electrode 42 is inserted in the space of first electrode 41, and around an E shape structure 41a, the 2nd E shape structure 41b of first electrode 41; Formation is interlaced with an E shape structure 41a, the 2nd E shape structure 41b of first electrode 41 thus, and surrounds an E shape structure 41a of first electrode 41, the structure of the 2nd E shape structure 41b.Because the structure of first electrode 41 is different with the structure of first electrode 31 shown in Fig. 3 A, therefore, the structure of second electrode 42 is different from the structure of second electrode 32 shown in Fig. 3 A.

The layout structure of capacitor 40 shown in Fig. 4 A also can obtain the layout structure of symmetry with it through the first direction upset, i.e. capacitor 40 ' shown in Fig. 4 B, described first direction is vertical with the vertical line direction of the E shape structure of first electrode 41, i.e. horizontal direction in the diagram.The structure of first electrode 41 ' of capacitor 40 ' is identical with the structure of first electrode 41 of capacitor 40, and the structure of second electrode 42 ' of capacitor 40 ' is identical with the structure of first electrode 42 of capacitor 40.

Execution mode 3

The array type capacitor of present embodiment comprises M*

N execution mode

1 or 2 described capacitors, and a described M*N capacitor arrangement becomes the matrix of the capable N row of M, and wherein, the adjacent electrode of neighboring capacitors links together.M, N are natural number.

Execution mode

1 or 2 described capacitor arrangement are become matrix array, and link together, can obtain having the more array type capacitor of high capacitance by certain way.The array type capacitor that constitutes with capacitor shown in Fig. 3 A 30 is an example, please refer to Fig. 5, shown in the array type capacitor comprise 36 (M=6, N=6) capacitor shown in Fig. 3 A 30, the adjacent electrode of neighboring capacitors links together, for example, first electrode of the capacitor of first row first row is adjacent with second electrode of the capacitor of the first capable secondary series, so these two electrodes link together (partially overlapping); First electrode of the capacitor of first electrode of the capacitor of first row, first row and second row, first row is adjacent, so these two electrodes link together; Second electrode of the capacitor of first row first row is adjacent with second electrode of the capacitor that second row first is listed as, so these two electrodes link together (partially overlapping).For array type capacitor shown in Figure 5, the identical electrodes of same column capacitance device links together, and second electrode of first electrode of previous column capacitor and back one column capacitance device links together.Two electrodes of array type capacitor shown in Figure 5 are respectively second electrode of the first column capacitance device and first electrode of last column capacitance device.

On same metal level, if enough layout areas are arranged, can adopt the array type capacitor of present embodiment, in the capacitor that obtains high capacitance, can also simplify processing step.

Execution mode 4

The stacked capacitor of present embodiment comprises two metal layers at least, and wherein, each metal level comprises

execution mode

1 or 2 described capacitors.Metal-layer structure by inter-level interconnects can be formed stacked capacitor with

execution mode

1 or 2 described capacitors, to obtain bigger capacitance.

Fig. 2 A is the side schematic view of an example of stacked capacitor, described stacked capacitor comprises two metal layers at least, in this example be seven layers, shown in stacked capacitor comprise: be connected through hole (Via) V11～V16, the V21～V26 of two metal layers up and down among the metal level M1～M7, interlayer dielectric layer D1～D6 and interlayer dielectric layer D1～D6.Wherein, every layer of metal level can comprise capacitor 30 as shown in Figure 3A, first electrode 31 of capacitor 30, second electrode 32 are represented with

symbol

1,2 respectively in Fig. 2 A, first electrode 1 of the capacitor 30 of each layer metal level electrically connects by the metal that is filled among through hole V11～V16, second electrode 2 electrically connects by the metal that is filled among through hole V21～V26, capacitor 30 with each layer metal level is connected in parallel thus, and two of the array type capacitor electrodes are respectively first electrode 1 and second electrode 2 shown in Fig. 2 A.

In other embodiments, the included capacitor of each layer metal level shown in Fig. 2 A can be a capacitor 30 shown in Fig. 3 C " obtain through flip horizontal, perhaps, also can be the capacitor 40 ' shown in Fig. 4 B.

Fig. 2 B is the side schematic view of another example of stacked capacitor, shown in stacked capacitor comprise: through hole (Via) V11 '～V16 ', the V21 '～V26 ' of two metal layers about being connected among the metal level M1 '～M7 ', interlayer dielectric layer D1 '～D6 ' and interlayer dielectric layer D1 '～D6 '.Wherein, metal level M1 ', M3 ', M5 ', M7 ' comprise capacitor 30 as shown in Figure 3A respectively, and first electrode 31 of capacitor 30, second electrode 32 are represented with

symbol

1,2 respectively in Fig. 2 A; Metal level M2 ', M4 ', M6 ' comprise the capacitor 30 ' shown in Fig. 3 B respectively, the layout structure of capacitor 30 ' is that the layout structure of capacitor 30 obtains through flip horizontal, first electrode 31 ' of capacitor 30 ', second electrode 32 ' are represented with symbol 1 ', 2 ' respectively in Fig. 2 B, that is to say that the capacitor 30 ' shown in the capacitor 30 shown in Fig. 3 A and Fig. 3 B is staggeredly stacked.Metal level M1 ', M3 ', M5 ', first electrode 1 of the capacitor 30 of M7 ' is by being filled in metal and the metal level M2 ' among through hole V11 '～V16 ', M4 ', second electrode 2 ' of the capacitor 30 ' of M6 ' electrically connects, metal level M1 ', M3 ', M5 ', second electrode 2 of the capacitor 30 of M7 ' is by being filled in metal and the metal level M2 ' among through hole V21 '～V26 ', M4 ', first electrode 1 ' of the capacitor 30 ' of M6 ' electrically connects, thus with the capacitor 30 of each layer metal level, 30 ' is connected in parallel, and two of stacked capacitor electrodes are respectively first electrode 1 (perhaps second electrode 2 ') and second electrode 2 (perhaps first electrode 1 ') shown in Fig. 2 B.

In other embodiments, the included capacitor of metal level M1 '～M7 ' also can be other possible structure, for example: metal level M1 ', M3 ', M5 ', M7 ' comprise capacitor 30 as shown in Figure 3A respectively, metal level M2 ', M4 ', M6 ' comprise the capacitor 30 shown in Fig. 3 C respectively ", i.e. capacitor 30 shown in capacitor shown in Fig. 3 A 30 and Fig. 3 C " be staggeredly stacked; Perhaps, metal level M1 ', M3 ', M5 ', M7 ' comprise the capacitor 40 ' shown in Fig. 4 B respectively, metal level M2 ', M4 ', M6 ' comprise the capacitor 40 shown in Fig. 4 A respectively, and promptly the capacitor 40 shown in the capacitor shown in Fig. 4 B 40 ' and Fig. 4 A is staggeredly stacked.

The metal material of metal level can be Cu, Al etc., and metal layer thickness is generally several thousand dusts (Angstrom).The dielectric material of interlayer dielectric layer can be SiO ₂, SiN etc., the thickness range of interlayer dielectric layer is generally several thousand to several ten thousand dusts.

The electrode of the two metal layers up and down of stacked capacitor shown in Fig. 2 A and the 2B links together by the metal that is filled in the through hole, and the capacitance of the stacked capacitor that obtains thus is the summation of the capacitance of the capacitor of each metal level.In other embodiments, the electrode of two metal layers can be according to the needs of actual capacitance up and down, select to connect or do not connect, like this, the coupling capacitance that forms between the metal level (coupling capacitance), area capacitance (area capacitance), peripheral electric capacity (peripherycapacitance) can be employed.

Table 1 shows the comparison of capacitance of the unit are of above-mentioned each capacitor, wherein, the capacitance of each capacitor is the result that the Star-rcxt simulation software with Synopsys company records under the same process condition, and described process conditions comprise the material (dielectric constant) of metal layer thickness and resistivity, dielectric layer and thickness etc.In the table 1, capacitor C1 is the capacitor 30 shown in Fig. 3 A, and it is formed on the layer of metal layer; Capacitor C2 is an array type capacitor shown in Figure 5, and it is formed on the layer of metal layer; Capacitor C3 piles up the stacked capacitor shown in Fig. 2 A of formation for the capacitor 30 shown in Fig. 3 A; Stacked capacitor shown in Fig. 2 B that capacitor C4 is staggeredly stacked to form for capacitor shown in Fig. 3 A 30 and the capacitor 30 ' shown in Fig. 3 B; Capacitor C5 is the capacitor 30 shown in Fig. 3 A and the capacitor 30 shown in Fig. 3 C " stacked capacitor shown in Fig. 2 B of being staggeredly stacked to form; Stacked capacitor shown in Fig. 2 B that capacitor C6 is staggeredly stacked to form for the capacitor 40 shown in the capacitor shown in Fig. 4 B 40 ' and Fig. 4 A; Stacked capacitor shown in Fig. 2 B that capacitor C7 (prior art) is staggeredly stacked to form for capacitor shown in Figure 1A 10 and the capacitor 10 ' shown in Figure 1B.

Table 1

	Layout area (μ m^2)	Capacitance (fF)	The capacitance of unit are (fF/ μ m^2)
	Layout area (μ m^2)	Capacitance (fF)	The capacitance of unit are (fF/ μ m^2)	Capacitor C1	6.76	0.815	0.121
Capacitor C2	213.16	28.3	0.133	Capacitor C1	6.76	0.815	0.121
Capacitor C2	213.16	28.3	0.133	Capacitor C3	6.76	4.78	0.707
Capacitor C4	6.76	7.09	1.049	Capacitor C3	6.76	4.78	0.707
Capacitor C4	6.76	7.09	1.049	Capacitor C5	6.76	7.37	1.090
Capacitor C6	6.76	7.30	1.080	Capacitor C5	6.76	7.37	1.090
Capacitor C6	6.76	7.30	1.080	Capacitor C7	6.76	7.29	1.078

Can see that from table 1 under the situation of identical topology area, the capacitance of capacitor C5, C6 is greater than the capacitance of capacitor C7, promptly the capacitance of the unit are of capacitor C5, C6 is greater than the capacitance of the unit are of capacitor C7.That is to say that if obtain identical capacitance, the required layout area of capacitor C5, C6 can be less than the required layout area of capacitor C7.

In sum, the layout structure of first electrode of technique scheme by changing capacitor, second electrode increase between two electrodes over against area, wherein, first electrode is a primary structure with E shape, second electrode is around the E shape structure of described first electrode.Use the capacitor of technique scheme, under the situation that layout area is determined, can obtain the capacitance of higher unit are; Perhaps, under the situation that capacitance is determined, can save layout area.

Though the utility model with preferred embodiment openly as above; but it is not to be used for limiting the utility model; any those skilled in the art are not in breaking away from spirit and scope of the present utility model; can make possible change and modification, therefore protection range of the present utility model should be as the criterion with the scope that the utility model claim is defined.

Claims

1. a capacitor comprises first electrode and second electrode, it is characterized in that,

Described first electrode comprises the linear structure of E shape structure and the middle horizontal line that is connected described E shape structure, and the middle horizontal line of described linear structure and described E shape structure constitutes T shape;

The E shape structure of described second electrode and first electrode is interlaced, and surrounds the E shape structure of described first electrode.

2. capacitor as claimed in claim 1 is characterized in that, described linear structure comprises the connecting line of vertical curve and the middle horizontal line that is connected described vertical curve and E shape structure.

3. capacitor as claimed in claim 1 is characterized in that, described linear structure comprises vertical curve and is connected the described vertical curve and the middle horizontal line of E shape structure, the connecting line of vertical line.

4. capacitor as claimed in claim 1 is characterized in that, described first electrode equates with the distance between centers of tracks of second electrode.

5. capacitor as claimed in claim 1 is characterized in that, described capacitor is MIM capacitor or MOM capacitor.

6. a capacitor comprises first electrode and second electrode, it is characterized in that,

Described first electrode comprises an E shape structure and the 2nd E shape structure that vertical line overlaps, and the linear structure that connects the middle horizontal line of a described E shape structure, the 2nd E shape structure, the middle horizontal line of a described linear structure and a described E shape structure, the 2nd E shape structure constitutes T shape;

The one E shape structure, the 2nd E shape structure of described second electrode and first electrode are interlaced, and the E shape structure of surrounding described first electrode.

7. capacitor as claimed in claim 6 is characterized in that, described first electrode equates with the distance between centers of tracks of second electrode.

8. capacitor as claimed in claim 6 is characterized in that, described capacitor is MIM capacitor or MOM capacitor.

9. an array type capacitor is characterized in that, comprises M*N as claim 1 or 6 described capacitors, and a described M*N capacitor arrangement becomes the matrix of the capable N row of M, and wherein, the adjacent electrode of neighboring capacitors links together.

10. array type capacitor as claimed in claim 9 is characterized in that, described array type capacitor is MIM capacitor or MOM capacitor.

11. a stacked capacitor is characterized in that, comprises two metal layers at least, wherein, each metal level comprises respectively as claim 1 or 6 described capacitors.

12. stacked capacitor as claimed in claim 11 is characterized in that, the described electrode of two metal layers up and down links together.

13. stacked capacitor as claimed in claim 11 is characterized in that, described stacked capacitor is MIM capacitor or MOM capacitor.