CN201194013Y - SPI sampling circuit for full-automatic tripartite group blood cell analyser - Google Patents
SPI sampling circuit for full-automatic tripartite group blood cell analyser Download PDFInfo
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- CN201194013Y CN201194013Y CNU2008201129170U CN200820112917U CN201194013Y CN 201194013 Y CN201194013 Y CN 201194013Y CN U2008201129170 U CNU2008201129170 U CN U2008201129170U CN 200820112917 U CN200820112917 U CN 200820112917U CN 201194013 Y CN201194013 Y CN 201194013Y
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Abstract
The utility model relates to a full automatic three cent blood cell analyzer SPI sampling circuit, which comprises an A/D communication sampling circuit and an ARM mainboard. The A/D communication sampling circuit comprises three analog switch chips (U17, U18,U19) and an analogue converter chip (U20); WBC and HGB signals are accessed to the signal input end of U17 respectively; the control signal input end of the U17 is connected to one I/O end of the ARM mainboard; PLT and RBC signals are accessed to the signal input end of U18 respectively; the control signal input end of the U18 is connected to one I/O end of the ARM mainboard; the output end of the U17 and U18 are connected to the two signal input ends of the U19 respectively; the control signal input end of the U19 is connected to one I/O end o the ARM mainboard; the output of the U19 is connected to the signal input end of the analogue converter chip (U20); the CONV, DATA and CLK end of the U20 are connected to the GPA12, SPIMISO0 and SPLCLK0 end of the ARM mainboard respectively. The utility model achieves the advantages of simple structure, economical and practical, improves the sampling speed of the ARM serial mainboard greatly.
Description
Affiliated technical field
The utility model belongs to the sample circuit of Medical Devices, relates to full-automatic tripartite group blood cell analyser (claiming blood counting instrument again, down together) driving circuit.
Background technology
The counting principle of haemocyte is based on the impedance variation that produces in the process of haemocyte by the jewel microsensor.When the haemocyte that is mixed with dilution passes through the jewel micropore, electric current is continuously by being placed on two electrodes on micropore both sides, pass through the processing of instrument amplifying circuit then, voltage signal amplified and remove background noise, obtain the signal that can analyze, the signal after will amplifying at last samples mainboard inside through A/D and handles.Therefore Sampling techniques are one of gordian techniquies of full-automatic tripartite group blood cell analyser fast and accurately.
At present, the circuit of the full-automatic tripartite group blood cell analyser of the overwhelming majority adopts the common board structure, also has few blood cell analysis instrument circuit to apply to ARM mainboard series.But at present the sample circuit of cellanalyzer mainboard also still uses the A/D sampling of mainboard CPU inside, and promptly Cai Yang simulating signal is directly delivered to the A/D sampling channel of mainboard CPU, by the A/D module of mainboard inside to analog signal sampling.But,, can cause the inaccuracy of pair cell counting like this so when cell sample is counted, can not collect enough features to each cell and count because the A/D slewing rate that mainboard carries can not reach the requirement of defined.
Summary of the invention
The utility model provides a kind of frame mode by the outside A/D communication sampling of ARM9SPI+, does not reach the deficiency of requirement to overcome the A/D slewing rate that mainboard carries in the prior art.
The utility model is made up of A/D communication sample circuit and ARM mainboard, and wherein A/D communication sample circuit comprises three analog switch chips (U17, U18, U19), and an analog to digital converter chip (U20).The analog switch chip constitutes the selector channel of signal sampling, and WBC, HGB signal insert two signal input parts of analog switch chip U17 respectively, and the signal input end of U17 is connected to an I/O end of ARM mainboard; PLT, RBC signal insert two signal input parts of analog switch chip U18 respectively, and the signal input end of U18 is connected to an I/O end of ARM mainboard; The output terminal of U17, U18 is connected with two signal input parts of analog switch chip U19 respectively again, and the signal input end of U19 is connected to an I/O end of ARM mainboard, and the output terminal of U19 is connected to the signal input part of analog to digital converter chip U20; The CONV of U20, DATA, CLK end are connected with GPA12, SPIMISO0, the SPLCLK0 end of ARM mainboard respectively.
More particularly, connected mode of the present utility model is:
WBC, HGB signal insert two signal input parts (S1, S2) of analog switch chip U17 respectively, its signal input end (IN) is connected with the I/O end (GPB4) of mainboard by resistance, and output terminal (D) is connected with the signal input port (S1) of analog switch chip U19; PLT, RBC signal insert two signal input parts (S1, S2) of analog switch chip U18 respectively, its signal input end (IN) is connected with the I/O end (GPA16) of mainboard by resistance, and output terminal (D) is connected with another signal input part of analog switch chip U19 (S2); The signal input end (IN) of analog switch chip U19 is connected with the I/O end (GPD9) of mainboard by resistance, the V+ end of U19 is connected with power supply by capacitor filter, the V-end of U19 is connected with power supply by capacitor filter, and U19 output terminal (D) is connected with the IN+ end of analog to digital converter chip U20 through resistance; The Vref end of analog to digital converter chip U20 is connected to ground by capacitor filter, the IN+ end of U20 is by stabilivolt ground connection, the IN-end of U20 is connected and ground connection with the GND end, U20+Vcc end is connected with power supply by capacitor filter, and the CONV of U20, DATA, CLK hold to hold with GPA12, SPIMISO0, the SPLCLK0 of ARM mainboard respectively by resistance and are connected.
The course of work of the present utility model is:
The signal input part of analog switch chip U17 receives WBC, HGB signal, and its signal input end receives the control signal U17IO that ARM mainboard GPB4 end sends; The signal input part of analog switch chip U18 receives PLT, RBC signal, and its signal input end receives the control signal U18IO that ARM mainboard GPA16 end sends; The signal input part of analog switch chip U19 receives the signal that receives respectively from U17, U18 output terminal, and its signal input end receives the control signal U19IO that ARM mainboard GPD9 end sends; From control signal U17IO, U18IO, the U19IO of ARM mainboard, the on/off of control U17, U18, U19 signal input part.
Work as U17IO, when U19IO was low level, the S1 end of the S1 of U17 end, U19 was logical, and WBC signal to be amplified enters into the U20 chip by U17, U19, takes the WBC signal and delivers to the ARM mainboard by U20; When U17IO be high level, when U19IO is low level, the S1 of the S2 of U17 end, U19 end is logical, HGB signal to be amplified enters into the U20 chip by U17, U19, takes the HGB signal and delivers to the ARM mainboard by U20; When U18IO be low level, when U19IO is high level, the S2 of the S1 of U18 end, U19 end is logical, PLT signal to be amplified enters into the U20 chip by U18, U19, takes the PLT signal and delivers to the ARM mainboard by U20; When U18IO, U19IO were high level, RBC signal to be amplified entered into the U20 chip by U18, U19, takes the RBC signal and delivers to the ARM mainboard by U20.
When sampling A U20 and ARM mainboard did not carry out data transmission, the transmission control signal CS0 that the ARM mainboard sends was a high level, and CS0 becomes low level by high level when both sides need transmit data.Simultaneously, when clock output signal CLK negative edge, the beginning data transmission, after one group of data has transmitted, the ARM mainboard will transmit control signal CS0 and become high level by low level, an end of transmission (EOT).When the ARM mainboard will transmit control signal CS0 and be changed to low level by high level by the time, data began transmission once more.The transfer rate of this SPI can be provided with by ARM mainboard corresponding registers, as long as outside sampling A can reach requirement, according to this A/D sample mode, the sampling rate of ARM can reach 25M/s, and this just makes that the cell sample bottleneck of cellanalyzer can be solved well.
The utility model is a description object with the ARM mainboard, but is not limited to the ARM mainboard, and the cpu motherboard with SPI (high-speed synchronous serial port) all is applicable to the utility model.
The utility model is a description object with the ADS7818 sampling A, but is not limited to the ADS7818 chip.
The beneficial effects of the utility model are, utilization ARM series is during as the mainboard of cellanalyzer, provides a kind of brand-new A/D sample mode to the A/D sampling of haemocyte, and this mode has improved the sampling rate of ARM series of plates greatly, and it is simple in structure, economical and practical.This frame mode has not only solved the ARM plate well and has carried A/D sampling module low excessively problem on the A/D sample rate, as long as select the external chip of the A/D sampling that has SPI that matches with it for use, just can meet the demands, can select friction speed neatly for use like this, the outside A/D sampling A of different accuracy satisfies the needs of self.This mode provides a kind of fine choice for the sampling process of cellanalyzer.
Description of drawings
Fig. 1 is a circuit structure block diagram of the present utility model.Wherein A is pending simulation signal generator, and B is an A/D communication sample circuit, and C is the ARM mainboard.
Fig. 2 is the way circuit schematic diagram of an embodiment of the present utility model.Wherein left side figure is an A/D communication sample circuit, U17, U18, U19 are the analog switch chip, U20 is the analog to digital converter chip, right figure JP4 is the ARM9 mainboard, and corresponding U17IO, U18IO, U19IO, CS0, DATA, CLK are connected among the JP4 of U17IO, the U18IO in the wherein left figure A/D communication sample circuit, U19IO, CS0, DATA, CLK and right figure.
Fig. 3 is the left figure A/D communication sample circuit schematic diagram of embodiment shown in Figure 2.WBC, HGB, RBC, PLT are four simulating signals to be sampled, and U17IO, U18IO, U19IO are used for the Route Selection control signal of U17, U18, U19.
Fig. 4 is the port connection diagram of the right figure JP4 of embodiment shown in Figure 2.
Embodiment
The utility model will be in conjunction with the accompanying drawings, is described further by following examples.
Embodiment.
The ARM mainboard of present embodiment adopts the ARM9 mainboard, and analog to digital converter chip U20 (A/D sampling A) adopts the ADS7818 chip, and analog switch chip U17, U18, U19 adopt the DG419 chip.
Fig. 3 is the schematic diagram that the A/D communication sample circuit of present embodiment amplifies.WBC, HGB, RBC, PLT are four simulating signals to be sampled, and U17IO, U18IO, U19IO are used for the Route Selection control signal of U17, U18, U19.
Fig. 4 is the port connection diagram of the ARM9 mainboard of present embodiment.
The concrete connected mode of present embodiment is:
WBC, HGB signal insert two signal input part S1, S2 ends of analog switch chip U17 respectively, its signal input end IN is connected with the I/O end GPB4 end of mainboard by resistance R 128, output terminal D is connected with the signal input port S1 of analog switch chip U19, V+, V-the end connect respectively+12 ,-the 12V power supply, VL connects+the 5V power supply, GND ground connection; PLT, RBC signal insert two signal input part S1, S2 ends of analog switch chip U18 respectively, its signal input end IN is connected with the I/O end GPA16 end of mainboard by resistance R 126, another signal input part of output terminal D and U19 S2 is connected, V+, V-the end connect respectively+12 ,-the 12V power supply, VL connects+the 5V power supply, GND ground connection; The signal input end IN of U19 is connected with the I/O end GPD9 end of mainboard by resistance R 125, the capacitor filter that the V+ of U19 end is formed by C43, C44 is connected with+12V power supply, the capacitor filter that the V-of U19 end is formed by C47, C48 is connected with-12V power supply, VL termination+5V power supply, GND ground connection, U19 output terminal D is connected with the IN+ end of analog to digital converter chip U20 through resistance R 57; The Vref end of U20 passes through C45, the capacitor filter that C46 forms is connected to ground, the IN+ end of U20 is by stabilivolt D1 ground connection, the IN-end of U20 is connected and ground connection with the GND end, U20+Vcc end passes through C49, the capacitor filter that C50 forms is connected with+5V power supply, the CONV end of U20 is connected with the GPA12 end of ARM9 mainboard by resistance R 124, the DATA end of U20 is connected with the SPIMISO0 end of ARM9 mainboard by resistance R 102, the CLK end of U20 is connected 5 of ARM9 mainboard with the SPLCLK0 end of ARM9 mainboard respectively by resistance R 103,7,8,13,14,20, the equal ground connection of 28 (GND port) pins.
The parameter of each element is respectively in the circuit: C43 is a 100nF electric capacity, C44 is the 10uF electrochemical capacitor, C47 is a 100nF electric capacity, and C48 is the 10uF electrochemical capacitor, and C45 is the electrochemical capacitor of 2.2uF, C46 is a 100nF electric capacity, C49 is a 100nF electric capacity, and C50 is the electrochemical capacitor of 10uF, and R57 is 100 Ω, D1 is the 5V stabilivolt, and R102, R103, R124 are 100 Ω.
The course of work of present embodiment is:
The signal input part of analog switch chip U17 receives WBC, HGB signal, and its signal input end receives the control signal U17IO that ARM9 mainboard GPB4 end sends; The signal input part of analog switch chip U18 receives PLT, RBC signal, and its signal input end receives the control signal U18IO that ARM9 mainboard GPA16 end sends; The signal input part of analog switch chip U19 receives the signal that receives respectively from U17, U18 output terminal, and its signal input end receives the control signal U19IO that ARM9 mainboard GPD9 end sends; From control signal U17IO, U18IO, the U19IO of ARM9 mainboard, the on/off of control U17, U18, U19 signal input part.
Work as U17IO, when U19IO was 0V, the S1 end of the S1 of U17 end, U19 was logical, and WBC signal to be amplified enters into the U20 chip by U17, U19, takes the WBC signal and delivers to the ARM9 mainboard by U20; When U17IO is 3.3V, U19IO when being 0V, the S1 end of the S2 of U17 end, U19 is logical, and HGB signal to be amplified enters into the U20 chip by U17, U19, takes the HGB signal and delivers to the ARM9 mainboard by U20; When U18IO is 0V, U19IO when being 3.3V, the S2 end of the S1 of U18 end, U19 is logical, and PLT signal to be amplified enters into the U20 chip by U18, U19, takes the PLT signal and delivers to the ARM9 mainboard by U20; When U18IO, U19IO were 3.3V, RBC signal to be amplified entered into the U20 chip by U18, U19, takes the RBC signal and delivers to the ARM9 mainboard by U20.
At the A/D chip in ARM9 mainboard transmission course, ARM9 is by the CLK path, to ADS7818 chip transmission clock signal, the transmission control signal CS0 that while ARM9 mainboard sends becomes low level by high level, and at next clock output signal CLK during by high step-down, begin from the ADS7818 chip by the DATA path with data transmission to the ARM9 mainboard, after one group of data has transmitted, the ARM9 mainboard will transmit control signal CS0 and become high level by low level, this end of transmission (EOT), by the time the ARM9 mainboard will transmit control signal CS0 and be changed to low level and at next clock output signal CLK by high step-down constantly by high level, and data begin transmission once more.Because when transmitting data, the transmission position of data is consistent with the CLK clock bit, thereby reaches very high transfer rate.
Claims (4)
1. full-automatic tripartite group blood cell analyser SPI sample circuit, comprise the signal sampling selection path, the ARM mainboard, it is characterized in that taking outside A/D communication sampling structure, outside A/D communication sample circuit comprises three analog switch chip (U17, U18, U19), an and analog converter chip (U20), WBC, the HGB signal inserts two signal input part (S1 of analog switch chip U17 respectively, S2), its signal input end (IN) is connected with the I/O end (GPB4) of mainboard by resistance, and output terminal (D) is connected with the signal input port (S1) of analog switch chip U19; PLT, RBC signal insert two signal input parts (S1, S2) of analog switch chip U18 respectively, its signal input end (IN) is connected with the I/O end (GPA16) of mainboard by resistance, and output terminal (D) is connected with another signal input part of analog switch chip U19 (S2); The signal input end (IN) of analog switch chip U19 is connected with the I/O end (GPD9) of mainboard by resistance, the V+ end of U19 is connected with power supply by capacitor filter, the V-end of U19 is connected with power supply by capacitor filter, and U19 output terminal (D) is connected with the IN+ end of analog converter chip U20 through resistance; The Vref end of analog converter chip U20 is connected to ground by capacitor filter, the IN+ end of U20 is by stabilivolt ground connection, the IN-end of U20 is connected and ground connection with the GND end, U20+Vcc end is connected with power supply by capacitor filter, and the CONV of U20, DATA, CLK hold to hold with GPA12, SPIMISO0, the SPLCLK0 of ARM mainboard respectively by resistance and are connected.
2. SPI sample circuit according to claim 1 is characterized in that the ARM mainboard is ARM9.
3. SPI sample circuit according to claim 1 is characterized in that the analog converter chip is ADS7818.
4. SPI sample circuit according to claim 1 is characterized in that the analog switch chip is DG419.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201129170U CN201194013Y (en) | 2008-05-16 | 2008-05-16 | SPI sampling circuit for full-automatic tripartite group blood cell analyser |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201129170U CN201194013Y (en) | 2008-05-16 | 2008-05-16 | SPI sampling circuit for full-automatic tripartite group blood cell analyser |
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| Publication Number | Publication Date |
|---|---|
| CN201194013Y true CN201194013Y (en) | 2009-02-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2008201129170U Expired - Lifetime CN201194013Y (en) | 2008-05-16 | 2008-05-16 | SPI sampling circuit for full-automatic tripartite group blood cell analyser |
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| CN (1) | CN201194013Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103048441A (en) * | 2012-12-21 | 2013-04-17 | 深圳市锦瑞电子有限公司 | Circuit arrangement method for hematology analyzer and circuit |
| CN103364452A (en) * | 2013-06-03 | 2013-10-23 | 南昌大学 | Blood cell classification and identification circuit and method |
-
2008
- 2008-05-16 CN CNU2008201129170U patent/CN201194013Y/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103048441A (en) * | 2012-12-21 | 2013-04-17 | 深圳市锦瑞电子有限公司 | Circuit arrangement method for hematology analyzer and circuit |
| CN103048441B (en) * | 2012-12-21 | 2014-08-20 | 深圳市锦瑞电子有限公司 | Circuit arrangement method for hematology analyzer and circuit |
| CN103364452A (en) * | 2013-06-03 | 2013-10-23 | 南昌大学 | Blood cell classification and identification circuit and method |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20091211 Address after: No. 699 Dongsheng Road, Chang Dong Industrial Zone, Jiangxi, Nanchang, China: 330012 Patentee after: Nanchang Biotech A & C Biotechnical Industry Incorporated Company Address before: Chang Dong two road Baxter Industrial Park, Jiangxi Province, Nanchang Liberation Road middle zip code: 330012 Patentee before: Nanchang Bt Biology High & New Technology Co., Ltd. |
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| CX01 | Expiry of patent term |
Granted publication date: 20090211 |
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| CX01 | Expiry of patent term |