CN201174385Y

CN201174385Y - Array substrate of thin-film transistor

Info

Publication number: CN201174385Y
Application number: CNU2008200558696U
Authority: CN
Inventors: 田广彦
Original assignee: SVA Group Co Ltd
Current assignee: SVA Group Co Ltd
Priority date: 2008-03-03
Filing date: 2008-03-03
Publication date: 2008-12-31
Anticipated expiration: 2018-03-03

Abstract

The utility model relates to a thin film transistor array substrate. The array substrate comprises a substrate, on which a plurality of grid lines and data wires are arranged crossed to form a plurality of pixel areas, and a plurality of pixel structures which are arranged in the pixel areas of the substrate, wherein each pixel structure comprises a thin film transistor and a pixel electrode; a source electrode of the thin film transistor is electrically connected with the pixel electrode through a contact hole; and a drain electrode o thin film transistor are arranged at an intersection of the grid lines and the data wires. In the thin film transistor array substrate, the drain electrodes of the thin film transistor and the intersections of the grid lines and the data wires are used together, which can decrease the coupling capacitance of the grid lines and the date wires, so the signal delay of the grid lines and the date wires is lessened.

Description

Thin-film transistor array base-plate

Technical field

The utility model relates to a kind of liquid crystal indicator, particularly relates to a kind of thin-film transistor array base-plate that reduces distribution signal delay.

Background technology

LCD (LCD) is a kind of flat-panel screens that is widely used at present, compares with other display modes, has advantages such as low-power consumption, external form be thin, in light weight, radiationless.Generally speaking, LCD includes thin-film transistor (TFT) array infrabasal plate, color film (CF) upper substrate and is filled in liquid crystal layer between the upper and lower base plate.Viewing area on the array infrabasal plate comprises a plurality of subpixel area, each subpixel area is generally two gate line (gate line, claim scan line again) intersect formed rectangle or other shape area with two data wires (data line), be provided with thin-film transistor and pixel electrode in it, thin-film transistor serves as switch element; The yawing moment that common electrode on the color film upper substrate and the electric field strength between the pixel electrode on the array infrabasal plate are being modulated liquid crystal molecule.

Because the resistance that distribution itself exists, and the electric capacity that forms between the common electrode on the electric capacity between this layer distribution and other conductive layer of array infrabasal plate, this layer distribution and the color film upper substrate make distribution exist RC to postpone.Along with the increase of display panels size and the raising of resolution, the distribution of LCD comprises that the RC of data wire, gate line, reparation line etc. postpones also can increase thereupon.And excessive RC postpones influence the brightness, contrast of LCD etc., thus the reduction display quality.As opening at gate line in TFT switch and the data wire process to the pixel charging, the RC on the gate line postpones to influence the switching characteristic of TFT, and the RC on the data wire postpones then can influence the signal voltage that is added on the liquid crystal layer, thereby influences display characteristic.

Fig. 1 illustrates the sub-pixel schematic diagram of a kind of TFT-LCD.Conductive layer on the array base palte 100 haves three layers, be respectively Gate layer, D layer and ITO layer, wherein the Gate layer forms grid 106 and the common electrode line 102 of grid line 101, TFT, D layer (part of black oblique line among the figure) forms the source electrode 104 of data wire 103, TFT and drains 105, and the ITO layer forms pixel electrode 107.Insulating barrier (not drawing among the figure) is arranged between each conductive layer.Gate signal is added on the grid 106, is used for opening or closing TFT; When TFT opened, data-signal was transferred to source electrode 104 by the drain electrode 105 of data wire.Source electrode 104 is connected with pixel electrode 107 by contact hole 108.Between array base palte 100 and the color membrane substrates (not drawing among the figure) is liquid crystal layer, forms liquid crystal capacitance Clc between the ITO layer on pixel electrode and the color membrane substrates, and the voltage on the liquid crystal capacitance is used for controlling the direction of rotation of liquid crystal molecule; Form storage capacitance Cst between pixel electrode and the common electrode line, be used for assisting the voltage that keeps on the liquid crystal capacitance.The shared grid line 101 of left and right sides neighbor, the shared data lines 103 of neighbouring pixel.

Fig. 2 illustrates another kind of sub-pixel structure, and wherein the structure of the source electrode 204 of TFT, drain electrode 205 is slightly different with Fig. 1, and is with the grid of grid line 101 as TFT.

In above-mentioned two sub pixel structures, when calculating the electric capacity between grid line and the data wire except to consider grid/and the electric capacity that forms of data wire cross section, also to consider the drain electrode of TFT and the electric capacity between the grid line.

Usually adopting following several method to reduce distribution RC at present postpones:

First method is to adopt the wiring material of low-resistivity.Apply for a patent among the CN200380103627.X in China, disclose a kind of use more the copper alloy of low-resistivity as the method for wiring material.Though adopt copper or copper alloy can reduce wiring resistance R, thereby reduce the signal delay on the distribution as wiring material, can't carry out volume production at present, practicality is relatively poor.

Second method is to increase the width of distribution and thickness to reduce the resistance of distribution, thereby reduce the signal delay of distribution, but increase the distribution width aperture opening ratio of array infrabasal plate is reduced, the electric capacity between while and other layer also can increase, and is limited to the effect that reduces the RC delay; In addition, increase the use amount that distribution thickness also can increase target, influence productive rate (throughput), also can increase the incidence of product point defective, line defect.

The third method is the overlapping area that reduces between wiring layer and other conductive layer of array infrabasal plate.Adopt self-registered technology (Self-Alignment Process) can reduce the electric capacity between each layer distribution on the array infrabasal plate, thereby the RC that reduces distribution postpone.But consider present technological ability, the ability that this method reduction distribution RC postpones is also limited.

The utility model content

Technical problem to be solved in the utility model provides a kind of thin-film transistor array base-plate that can reduce grid line and data line signal delay.

The utility model is to solve the problems of the technologies described above the technical scheme that adopts to provide a kind of thin-film transistor array base-plate, comprises a substrate, many grid lines and data wire and a plurality of dot structure.These grid lines and data wire are disposed on the substrate, and grid line and data wire intersect to define a plurality of pixel regions.A plurality of dot structures are disposed in each pixel region on the substrate, wherein each dot structure comprises a thin-film transistor and a pixel electrode, the source electrode of this thin-film transistor electrically connects described pixel electrode by contact hole, and the drain electrode of this thin-film transistor is positioned at the cross part of grid line and data wire.

Because the drain electrode of the TFT in the thin-film transistor array base-plate of the present utility model and the cross part of grid line and data wire are shared, this structure can reduce the coupling capacitance of grid line and data wire, and the resistance of grid line and data wire remains unchanged substantially, be proportional to the total capacitance on the common electrode and the product of all-in resistance based on the time coefficient τ of signal delay, thin-film transistor array base-plate of the present utility model can reduce the signal delay of grid line and data wire.

Description of drawings

For above-mentioned purpose of the present utility model, feature and advantage can be become apparent, below in conjunction with accompanying drawing embodiment of the present utility model is elaborated, wherein:

Fig. 1 is the sub-pixel structure schematic diagram of existing a kind of tft array substrate.

Fig. 2 is the sub-pixel structure schematic diagram of existing another kind of tft array substrate.

Fig. 3 is the sub-pixel structure schematic diagram of the tft array substrate of an embodiment of the utility model.

Fig. 4 A～Fig. 4 C is the making flow chart of tft array substrate of the present utility model.

Embodiment

Fig. 3 is the structural representation of the tft array substrate of an embodiment of the utility model.On a thin-film transistor array base-plate, dispose many grid lines 301 and data wire 303 (respectively illustrating 2 among the figure) and common electrode line 302, these grid lines and data wire intersect to define a plurality of pixel regions (shown in the figure one), in the pixel region shown in the figure, disposed a dot structure, it comprises a thin-film transistor and a pixel electrode 307, this thin-film transistor has source electrode 304, drain electrode 305 and grid, wherein pixel electrode 307 is connected with the source electrode 304 of thin-film transistor by contact hole 308, drain electrode 305 is the cross parts that are positioned at grid line 301 and data wire 303, and grid then is to be positioned on the grid line 301.In addition, pixel electrode 307 parts connect with electrode wires 302 together.

The making flow process of thin-film transistor array base-plate of the present utility model is described below with reference to Fig. 4 A～Fig. 4 C.Fig. 4 A～Fig. 4 C is the substrate sectional view of Fig. 3 section line A-A position.

At first,, provide an insulated substrate 300, and on substrate, form the grid wiring layer 310 that comprises above-mentioned grid line 301 and grid with reference to Fig. 4 A.Then, with reference to Fig. 4 B, cover gate insulating barrier 320 on grid wiring layer 310 afterwards, forms the semiconductor layer 330 that comprises amorphous silicon layer 331 and n+ amorphous silicon layer 332 on insulating barrier 320 earlier.Moreover, on semiconductor layer 330 and gate insulator 320, form data arrange layer 340.Afterwards, shown in Fig. 4 C, making the data arrange layer form drain electrode 305, the source electrode 304 of above-mentioned data wire 303 and thin-film transistor, wherein is that cross part with grid line 301 and data wire 303 is as drain electrode 305.Afterwards, cover one deck passivation layer 350, form pixel electrode 307 (with reference to Fig. 3) then and also electrically connect by the source electrode 304 of contact hole 308 and thin-film transistor.Shown in Fig. 4 C, semiconductor layer 330 is positioned at source electrode 304 with the below of drain electrode 305 and on gate insulator 320.

In the thin-film transistor array base-plate of the present utility model, the cross part of the drain electrode of its TFT and grid line and data wire is shared, this structure can reduce the coupling capacitance of grid line and data wire, and the resistance of grid line and data wire remains unchanged substantially, be proportional to the total capacitance on the common electrode and the product of all-in resistance based on the timeconstant of signal delay, that is:

τ∝R*C

This sub-pixel structure can reduce the signal delay on grid line and the data wire.Sub-pixel with 32 inches TV is that example describes, and its resolution is 1366 * 3 * 768, and its sub-pixel size is 170.25 μ m * 510.75 μ m.As shown in table 1 below based on the time constant of the signal delay of LCD grid line of the present utility model and data wire with the time constant of the signal delay of grid line that does not adopt common LCD of the present utility model and data wire:

	The utility model	Reference value	Reduce effect
	The utility model	Reference value	Reduce effect	Grid line	2.07μs	2.27μs	-9％
Data wire	2.02μs	2.17μs	-7％	Grid line	2.07μs	2.27μs	-9％

Table 1

As seen, thin-film transistor array base-plate of the present utility model can reduce the grid line of LCD and the signal delay on the data wire.

Though the utility model discloses as above with preferred embodiment; right its is not in order to limit the utility model; any those skilled in the art; in not breaking away from spirit and scope of the present utility model; when doing a little modification and perfect, therefore protection range of the present utility model is worked as with being as the criterion that claims were defined.

Claims

1. thin-film transistor array base-plate is characterized in that comprising:

One substrate;

Many grid lines and many data wires are disposed on the described substrate, and wherein said grid line and data wire intersect to define a plurality of pixel regions;

A plurality of dot structures, be disposed in each pixel region on the described substrate, wherein each dot structure comprises a thin-film transistor and a pixel electrode, the source electrode of described thin-film transistor electrically connects described pixel electrode by contact hole, and the drain electrode of described thin-film transistor is positioned at the cross part of described grid line and data wire.

2. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, also comprises the common electrode line, and described pixel electrode part is connected with described common electrode line.

3. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, the grid of described thin-film transistor is to be positioned on the described grid line.

4. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, also comprises a gate insulator, is arranged on the described grid line.

5. thin-film transistor array base-plate as claimed in claim 4 is characterized in that, also comprises semi-conductor layer, and it is positioned at the below of the source electrode of described thin-film transistor and drain electrode and on described gate insulator.