CN201134234Y - Display controlling circuit - Google Patents
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- CN201134234Y CN201134234Y CNU2007201909553U CN200720190955U CN201134234Y CN 201134234 Y CN201134234 Y CN 201134234Y CN U2007201909553 U CNU2007201909553 U CN U2007201909553U CN 200720190955 U CN200720190955 U CN 200720190955U CN 201134234 Y CN201134234 Y CN 201134234Y
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Abstract
The utility model discloses a display control circuit, which is used to control an approximate crystalline liquid crystal display screen to display. The display control circuit comprises a control module, M R wave generation modules and N D wave generation modules, the control module and all R wave generation modules are connected with the D wave generation modules, and R wave generation modules and the D wave generation modules are connected with the approximate crystalline liquid crystal display screen. The display control circuit of the utility model is capable of producing bipolar high voltage pulse, the bipolar high voltage pulse is used to drive the arrangement status of liquid crystal to change, thereby various patterns are displayed by the display screen.
Description
Technical field
The utility model relates to a kind of display control circuit, specifically, relates to a kind of circuit that smectic liquid crystal display screen shows that is used to control.
Background technology
The smectic phase liquid crystal is spent between 60 degree subzero 20 and is the starchiness of thickness, if its ordered state is changed, needs to use the positive negative bipolar high-voltage signal to drive.At present, what the TN screen of STN screen and TFT liquid crystal used is that the bipolarity ac voltage signal drives, but this voltage magnitude is very low, between the 5V, can't satisfy the driving needs of smectic phase liquid crystal at 3V.And plasma chip driving voltage is than higher, and peak value is generally greater than more than the 60V, but this signal all is the unipolar pulse mode, is not to drive the needed double polarity pulse signal of smectic phase liquid crystal.This shows that because the singularity of the display screen that the smectic phase liquid crystal material is made, its display driver needs a kind of bipolarity high-voltage pulse signal.Therefore, designing a kind of circuit that produces the bipolarity high-voltage pulse signal is urgent problem.
The utility model content
The purpose of this utility model is to provide a kind of display control circuit, and this circuit can produce the bipolarity high-voltage pulse signal, to drive the demonstration of smectic liquid crystal display screen.
To achieve these goals, the utility model has adopted following technical scheme:
A kind of display control circuit, this display control circuit is used to control the demonstration of smectic liquid crystal display screen, this smectic liquid crystal display screen comprises first base layer and second base layer, between first base layer and second base layer, be provided with a mixolimnion that forms by smectic phase liquid crystal and additives mixed, this smectic phase liquid crystal is a category-A smectic phase liquid crystal organic compound, this additive is the compound of band conductive characteristic, be provided with first conductive electrode layer at first base layer towards a side of mixolimnion, be provided with second conductive electrode layer at second base layer towards a side of mixolimnion, first conductive electrode layer is made up of M strip shaped electric poles that is arranged in parallel, second conductive electrode layer is made up of N strip shaped electric poles that is arranged in parallel, N strip shaped electric poles of the M of first conductive electrode layer strip shaped electric poles and second conductive electrode layer is perpendicular, this first and second conductive electrode layer forms the pixel array of one M * N, it is characterized in that: this display control circuit comprises control module, M R ripple generation module and N D ripple generation module, control module is connected with D ripple generation module with all R ripple generation modules, R ripple generation module is connected with smectic liquid crystal display screen with D ripple generation module, wherein:
R ripple generation module comprises the first positive level converter unit, the first negative level converter unit, the first forward signal generation unit, the first negative-going signal generation unit and first signal synthesis unit, this first forward signal generation unit is connected with control module through the first positive level converter unit, this first negative-going signal generation unit is connected with control module through the first negative level converter unit, this first forward signal generation unit is connected with first signal synthesis unit with the first negative-going signal generation unit, and this first signal synthesis unit is connected with a strip shaped electric poles of described first conductive electrode layer;
D ripple generation module comprises the second positive level converter unit, the second negative level converter unit, the second forward signal generation unit, the second negative-going signal generation unit, the true amplitude control module, negative amplitude control module and secondary signal synthesis unit, this second forward signal generation unit is connected with control module through the second positive level converter unit, this second negative-going signal generation unit is connected with control module through the second negative level converter unit, just, negative amplitude control module respectively with the second forward signal generation unit, the second negative-going signal generation unit connects, this second forward signal generation unit is connected with the secondary signal synthesis unit with the second negative-going signal generation unit, and this secondary signal synthesis unit is connected with a strip shaped electric poles of described second conductive electrode layer.
When showing, display control circuit is according to the displaying scheme of setting, carry out R ripple and the output of D ripple in the mode that drives line by line, R ripple and D ripple are applied on the strip shaped electric poles of two conductive electrode layers, make two conductive electrode interlayers form a certain size, the voltage signal of frequency, change the arrangement form of smectic phase liquid crystal in the mixolimnion, make pixel present the bright or vaporific state of full impregnated, thereby make display screen demonstrate required literal or pattern.
The utility model has the advantages that: because the smectic phase liquid crystal needs the high-voltage bipolar driven, so the utility model display control circuit boosts to action of low-voltage pulse positive and negative, and positive and negative unipolar pulse synthesized the bipolarity high-voltage pulse, change to utilize this bipolarity high-tension pulse to bring the ordered state that drives the smectic phase liquid crystal, thereby make display screen show various patterns.In addition, the R ripple and the D ripple of control output all are that bipolarity makes zero in the utility model display control circuit, use such drive waveform smectic phase liquid crystal, can prolong the life-span of liquid crystal effectively, avoid the electrochemical reaction on surface.
Description of drawings
Fig. 1 is the composition synoptic diagram of smectic liquid crystal display screen;
Fig. 2 is arranged in the first and second conductive electrode layer synoptic diagram of lattice array shape anyhow;
Fig. 3 is the utility model display control circuit composition frame chart;
Fig. 4 is the circuit theory diagrams of R ripple generation module;
Fig. 5 is the circuit theory diagrams of D ripple generation module;
Fig. 6 is the waveform stack synoptic diagram of R ripple and D ripple;
Fig. 7 is the smectic phase liquid crystal arrangement form synoptic diagram of low-frequency voltage when acting on first, second conductive electrode layer;
Fig. 8 is the smectic phase liquid crystal arrangement form synoptic diagram of HF voltage when acting on first, second conductive electrode layer;
Fig. 9 is an instance graph of the type of drive of explanation smectic liquid crystal display screen.
Embodiment
Below in conjunction with accompanying drawing the utility model is described in further detail.
To shown in Figure 2, the utility model display control circuit is used to control smectic liquid crystal display screen and shows as Fig. 1.This smectic liquid crystal display screen 1 comprises that the material of first base layer 11 and second base layer, 12, the first base layers 11 and second base layer 12 is chosen as glass or plastics.Between first base layer 11 and second base layer 12, be provided with a mixolimnion 13 that forms by smectic phase liquid crystal and additives mixed, promptly mix with additive molecule 1 32 by the smectic phase liquid crystal molecule 131 shown in Fig. 7.This smectic phase liquid crystal is category-A smectic phase liquid crystal (Smectic-A) organic compound, as with silica-based compound, four cyano four octyl group biphenyl, tetraacethyl ester in last of the ten Heavenly stems four cyano biphenyl etc.Additive is the compound of band conductive characteristic, contains the compound of conductive ion as cetyltriethylammonium bromide etc.Be coated with first conductive electrode layer 14 at first base layer 11 towards a side of mixolimnion 13, be coated with second conductive electrode layer 15 at second base layer 12 towards a side of mixolimnion 13, as shown in Figure 2, first conductive electrode layer 14 is made up of M strip shaped electric poles 141 that is arranged in parallel, second conductive electrode layer 15 is made up of N strip shaped electric poles 151 that is arranged in parallel, N strip shaped electric poles 151 of the M of first conductive electrode layer 14 strip shaped electric poles 141 and second conductive electrode layer 15 is perpendicular, this first conductive electrode layer 14 and second conductive electrode layer 15 form the pixel-matrix array structure of one M * N, a strip shaped electric poles 141 and a strip shaped electric poles 151 form a pixel, pixel 3 for example shown in Figure 2.These two conductive electrode layers 14 and 15 and middle mixolimnion 13 formed a capacitance structure that area is very big.First conductive electrode layer 14 and second conductive electrode layer 15 are transparent, and it can be ITO (tin indium oxide) etc., and can use auxiliary metal electrode as required, as aluminium, copper, silver etc.
As shown in Figure 3, the utility model display control circuit 2 comprises control module 21, a M R ripple generation module 22 and N D ripple generation module 23, control module 21 is connected with D ripple generation module 23 with all R ripple generation modules 22, and R ripple generation module 22 is connected with smectic liquid crystal display screen 1 with D ripple generation module 23.
R ripple generation module 22 comprises the first positive level converter unit 221, the first negative level converter unit 222, the first forward signal generation unit 223, the first negative-going signal generation unit 224 and first signal synthesis unit 225.This first forward signal generation unit 223 is connected with control module 21 through the first positive level converter unit 221, this first negative-going signal generation unit 224 is connected with control module 21 through the first negative level converter unit 222, this first forward signal generation unit 223 is connected with first signal synthesis unit 225 with the first negative-going signal generation unit 224, and this first signal synthesis unit 225 is connected with a strip shaped electric poles 141 of first conductive electrode layer 14.
D ripple generation module 23 comprises the second positive level converter unit 231, the second negative level converter unit 232, the second forward signal generation unit 233, the second negative-going signal generation unit 234, true amplitude control module 235, negative amplitude control module 236 and secondary signal synthesis unit 237.This second forward signal generation unit 233 is connected with control module 21 through the second positive level converter unit 231, this second negative-going signal generation unit 234 is connected with control module 21 through the second negative level converter unit 232, true amplitude control module 235 is connected with the second forward signal generation unit 233, negative amplitude control module 236 is connected with the second negative-going signal generation unit 234, this second forward signal generation unit 233 is connected with secondary signal synthesis unit 237 with the second negative-going signal generation unit 234, and this secondary signal synthesis unit 237 is connected with a strip shaped electric poles 151 of second conductive electrode layer 15.
Fig. 4 and Fig. 5 are respectively the physical circuit figure of R ripple generation module, D ripple generation module.As shown in Figure 4 and Figure 5, all CMOS phase inverters are by enhancement mode PMOS pipe and the complementary formation of enhancement mode NMOS pipe, the PMOS pipe links to each other as the input end of CMOS phase inverter with the grid of NMOS pipe, and the PMOS pipe links to each other as the output terminal of CMOS phase inverter with the drain electrode of NMOS pipe.
As shown in Figure 4, the first positive level converter unit 221 comprises a CMOS phase inverter CMOS1, PMOS pipe VT1 links to each other as the input end InR+ of phase inverter CMOS1 with the grid of NMOS pipe VT2, PMOS pipe VT1 links to each other as the output terminal OutR+ (formation of following phase inverter is similar to phase inverter CMOS1, repeats no more) of phase inverter CMOS1 with the drain electrode of NMOS pipe VT2.The input end InR+ of this phase inverter CMOS1 links to each other with its corresponding signal output part Out1 on a capacitor C 1 and control module 21, the first forward signal generation unit 223 comprises a high pressure NMOS transistor VT5, the grid of this high pressure NMOS transistor VT5 links to each other with the output terminal OutR+ of the phase inverter CMOS1 of the first positive level converter unit 221, and the drain electrode of this high pressure NMOS transistor VT5 links to each other with an input end drvR+ of first signal synthesis unit 225 through a capacitor C 3.Similarly, the first negative level converter unit 222 comprises a CMOS phase inverter CMOS2, the input end InR-of this phase inverter CMOS2 links to each other with its corresponding signal output part Out2 on a capacitor C 2 and control module 21, the first negative-going signal generation unit 224 comprises a high voltage PMOS transistor VT6, the grid of this high voltage PMOS transistor VT6 links to each other with the output terminal OutR-of the phase inverter CMOS2 of the first negative level converter unit 222, the drain electrode of this high voltage PMOS transistor VT6 links to each other with another input end drvR-of first signal synthesis unit 225 through a capacitor C 4, and the output terminal Out_R of first signal synthesis unit 225 links to each other with a strip shaped electric poles 141 of first conductive electrode layer 14.
As shown in Figure 5, the second positive level converter unit 231 comprises a CMOS phase inverter CMOS3, the input end InD+ of this phase inverter CMOS3 links to each other with its corresponding signal output part Out3 on a capacitor C 5 and control module 21, the second forward signal generation unit 233 comprises a high pressure NMOS transistor VT11, the grid of this high pressure NMOS transistor VT11 links to each other with the output terminal OutD+ of the phase inverter CMOS3 of the second positive level converter unit 231, the drain electrode of this high pressure NMOS transistor VT11 is divided into two-way, one the tunnel links to each other with the input end of true amplitude control module 235 through a resistance R 4, and another Lu Jingyi capacitor C 7 links to each other with an input end drvD+ of secondary signal synthesis unit 237.Similarly, the second negative level converter unit 232 comprises a CMOS phase inverter CMOS4, the input end InD-of this phase inverter CMOS4 links to each other with its corresponding signal output part Out4 on a capacitor C 6 and control module 21, the second negative-going signal generation unit 234 comprises a high voltage PMOS transistor VT12, the grid of this high voltage PMOS transistor VT12 links to each other with the output terminal OutD-of the phase inverter CMOS4 of the second negative level converter unit 232, the drain electrode of this high voltage PMOS transistor VT12 is divided into two-way, one the tunnel links to each other with the input end of negative amplitude control module 236 through a resistance R 5, another Lu Jingyi capacitor C 8 links to each other with another input end drvD-of secondary signal synthesis unit 237, and the output terminal Out_D of secondary signal synthesis unit 237 links to each other with a strip shaped electric poles 151 of second conductive electrode layer 15.
In Fig. 4 and Fig. 5, control module 21 can be single-chip microcomputer or FPGA, and positive and negative amplitude control module 235 and 236 can be transformer, and first, second signal synthesis unit 225 and 237 can be made of a plurality of diodes, by behind the diode, both synthesize a bidirectional pulse to positive negative pulse stuffing respectively.Control module 21 is used to control the R ripple output of each R ripple generation module 22 and the D ripple output of each D ripple generation module 23.A R ripple generation module 22 links to each other with two signal output parts of control module 21, exports a R ripple, and this R ripple acts on the strip shaped electric poles 141.Similarly, a D ripple generation module 23 links to each other with two signal output parts of control module 21, exports a D ripple, and this D ripple acts on the strip shaped electric poles 151.Control module 21 needs 2M+2N signal output part to finish the output of R ripple and D ripple control, the outputs of two common waveforms of control of signal output parts (R ripple or D ripple) altogether.
The principle of work of the utility model display control circuit once is described below.
According to driving requirement, general ,+VH is 12V, and-VH is-12V, and+Vpp is 100V ,-Vpp is-100V.When needs output R ripple, the signal output part Out1 of control module 21 and Out2 output amplitude are the positive pulse of 5V, this amplitude is that the positive pulse of 5V is carried out level translation by phase inverter CMOS1, output terminal OutR+ output amplitude by phase inverter CMOS1 is the positive pulse of 12V, this amplitude is that the positive pulse of 12V is passed through high pressure NMOS transistor VT5 more then, is the high pressure positive pulse of 100V by the drain electrode output amplitude of transistor VT5.Similarly, this amplitude is that the positive pulse of 5V is carried out level translation by phase inverter CMOS2, output terminal OutR-output amplitude by phase inverter CMOS2 is-negative pulse of 12V, this amplitude is passed through high voltage PMOS transistor VT6 again for the negative pulse of-12V then, by the drain electrode output amplitude of transistor VT6 is-the high pressure negative pulse of 100V.Then, to carry out pulse synthetic for the high pressure positive negative pulse stuffing of ± 100V enters first signal synthesis unit 225 by input end drvR+ and drvR-respectively for amplitude, output terminal Out_R output amplitude by first signal synthesis unit 225 is ± bidirectional pulse of 100V, and this bidirectional pulse is the R ripple.
When needs output D ripple, the signal output part Out3 of control module 21 and Out4 output amplitude are the positive pulse of 5V, this amplitude is that the positive pulse of 5V is carried out level translation by phase inverter CMOS3, output terminal OutD+ output amplitude by phase inverter CMOS3 is the positive pulse of 12V, this amplitude is that the positive pulse of 12V is passed through high pressure NMOS transistor VT11 more then, because Vpp is become 50V to true amplitude control module 235 to the drain electrode of transistor VT11 power supply, so be the high pressure positive pulse of 50V by the drain electrode output amplitude of transistor VT11.Similarly, this amplitude is that the positive pulse of 5V is carried out level translation by phase inverter CMOS4, output terminal OutD-output amplitude by phase inverter CMOS4 is-negative pulse of 12V, this amplitude is passed through high voltage PMOS transistor VT12 again for the negative pulse of-12V then, because negative amplitude control module 236 general-Vpp become-and 50V and powering to the drain electrode of transistor VT12, so be-the high pressure negative pulse of 50V by the drain electrode output amplitude of transistor VT12.Then, to carry out pulse synthetic for the high pressure positive negative pulse stuffing of ± 50V enters secondary signal synthesis unit 237 by input end drvD+ and drvD-respectively for amplitude, output terminal Out_D output amplitude by secondary signal synthesis unit 237 is ± bidirectional pulse of 50V, and this bidirectional pulse is the D ripple.
In the practical application, the R wave amplitude of control output is more than or equal to 100V, and correspondingly, the D wave amplitude is more than or equal to 50V.In circuit, choose reasonable power supply, resistance make output waveform satisfy formula (R wave amplitude-D wave amplitude)＜threshold voltage magnitude＜(R wave amplitude+D wave amplitude) and get final product.Threshold voltage is to determine according to the composition of mixolimnion 13 and thickness, is generally more than the 50V.
The demonstration of smectic liquid crystal display screen 1 is to be applied to voltage swing, frequency and action time on two conductive electrode layers 14 and 15 by control, change the arrangement form of the smectic phase liquid crystal in the mixolimnion 13, thereby light is changed realize between transmission and scattering, shown as the conversion of bright and vaporific of full impregnated on the macroscopic view.First conductive electrode layer 14 and second conductive electrode layer 15 have formed the pixel-matrix array structure of a M * N, perpendicular two strip shaped electric poles 141,151 form a pixel 3, so the state of controlling the pixel of its formation jointly in the voltage magnitude and the frequency of 141,151 generations of these two strip shaped electric poles.Output is the R ripple on the strip shaped electric poles 141, and output is the D ripple on the strip shaped electric poles 151, and the voltage between two strip shaped electric poles is the stack of R ripple and D ripple.
As shown in Figure 6, if the R ripple is identical with the D wave frequency, phase place is identical, the pulse amplitude that the stack back forms is less than the amplitude of threshold voltage, and pixel can not change so.If the R ripple is identical with the D wave frequency, but phase place phase difference of half cycle, i.e. D ' waveform shown in the figure and R waveform, the pulse amplitude that the stack back forms is greater than threshold voltage magnitude, pixel just can change so, shows as to become vaporificly by full impregnated is bright, or to become full impregnated bright by vaporific.If the waveforms amplitude after the stack is greater than threshold voltage magnitude, and frequency is about 50Hz, then pixel is vaporific by the bright change of full impregnated.If the waveforms amplitude after the stack is greater than threshold voltage magnitude, and frequency is about 1000Hz, then pixel is bright by vaporific change full impregnated.Describe in detail below.
As shown in Figure 7, when the after-applied voltage magnitude two conductive electrode layers 14 and 15 of R ripple and D ripple stack greater than threshold voltage magnitude, and frequency control is at 50Hz to 200Hz, as apply ± bidirectional pulse about 100v, 50Hz, so, when voltage action time during less than 1 second, the smectic phase liquid crystal molecule 131 in the mixolimnion 13 just twists, and forms out of order arrangement form shown in Figure 3.Because each of smectic phase liquid crystal molecule 131 (promptly passed through the long optical axis difference of each liquid crystal to diversity owing to incident ray, the anaclasis angle difference of each liquid crystal, thereby the refractive index difference of each liquid crystal), make the ray refraction of each smectic phase liquid crystal molecule 131 of incident exist very big difference, promptly in the mixolimnion 13 of this meagre thickness, optical index is producing violent variation, thereby strong scattering has taken place in light, on macroscopic view, this astigmatism effect presents a kind of as the vaporific state as the acute-matte, pixel show as by full impregnated bright become vaporific.
As shown in Figure 8, when the after-applied voltage magnitude two conductive electrode layers 14 and 15 of R ripple and D ripple stack greater than threshold voltage magnitude, and frequency control is more than 1000Hz, as apply ± 100v, bidirectional pulse about 1000Hz, so, when voltage action time during less than 1 second, smectic phase liquid crystal molecule 131 in the mixolimnion 13 just becomes regularly arranged form, at this moment, the long optical axis of smectic phase liquid crystal molecule 131 is perpendicular to the conductive electrode layer plane, the ray refraction of each smectic phase liquid crystal molecule 131 of incident does not produce acute variation, and light can freely see through mixolimnion 13, therefore, on macroscopic view, present the bright state of a kind of full impregnated, display screen is crossed in the complete transmission of light, and pixel shows as by vaporific that to become full impregnated bright.
When reality is implemented, can adjust output frequency by control module 21, by selecting the amplitude of the resistance change output waveform in the circuit, and then change is applied to voltage swing and frequency on two conductive electrode layers 14 and 15, and the part distortion takes place in the arrangement form that makes smectic phase liquid crystal molecule 131, produce astigmatic effect in various degree, at the multiple progressive state that shows as the different gray scales rank between vaporific and bright two states of full impregnated on the macroscopic view, as translucent etc.
More than be the description that 2 pairs of a certain pixels of display control circuit drive, for whole smectic liquid crystal display screen 1, its display mode is to be undertaken by the driving rule of setting in the control module 21.Classify example as with pixel-matrix shown in Figure 9 below, obviously show the demonstration control of 2 pairs of smectic liquid crystal display screens 1 of control circuit.
As Fig. 9, this pixel-matrix is classified 3 * 3 array as, R1～R3 is the control signal source, each control signal source is by the corresponding R waveform of control module 21 control outputs, each control signal source is to a strip shaped electric poles 141 outputs one fixed waveform R ripple of one first conductive electrode layer 14, D1～D3 is a data signal source, and each data signal source is by the corresponding D waveform of control module 21 control outputs, and each data signal source is to a strip shaped electric poles 151 outputs one control waveform D ripple of one second conductive electrode layer 15.T11, T12, T13, T21, T22, T23, T31, T32, T33 are the pixel that two strip shaped electric poles form, for example, T11 is the pixel that the first row strip shaped electric poles on the row strip shaped electric poles of first on first conductive electrode layer 14 and second conductive electrode layer 15 forms, this pixel is controlled jointly by the waveform of R1 and D1 output, to drive this pixel.
During driving, control module 21 is pressed the waveform output of display requirement control R ripple and D ripple, process is: at first, make R1～R3 and D1～D3 for closing, be that R1～R3 and D1～D3 are output as 0, R1 exports fixing R ripple then, R2 and R3 close, and do not export the R ripple, D1～required data-signal (the D ripple identical with the R wave phase shown in Figure 6 of D3 serial input, or with the D ' ripple in R wave phase phase difference of half cycle), deposit and open simultaneously through register, to each row while input signal, at this moment, all pixels of first row are driven and are shown as the state that needs, and other pixel does not change.Then, R1 and R3 close, and R2 opens, output R ripple, D1～new the data-signal of D3 serial input deposits and opens simultaneously through register, to each row while input signal, at this moment, all pixels of second row are driven and are shown as the state that needs, and other pixel does not change.In like manner, below each row driven successively, make each pixel become required state, lined by line scan the literal or the pattern that display screen are demonstrated need until entire display screen.
The utility model has the advantages that: because the smectic phase liquid crystal needs high-voltage bipolar voltage to drive, this practicality is new The type display control circuit boosts to action of low-voltage pulse positive and negative, and positive and negative unipolar pulse is synthesized bipolarity High-voltage pulse changes to utilize this bipolarity high-tension pulse to bring the ordered state that drives the smectic phase liquid crystal, thereby Make display screen show various patterns. In addition, R ripple and the D ripple of control output in the utility model display control circuit All be that bipolarity makes zero, use such drive waveform smectic phase liquid crystal, can effectively prolong the life-span of liquid crystal, Avoid the electrochemical reaction on surface.
Claims (7)
1, a kind of display control circuit, this display control circuit is used to control the demonstration of smectic liquid crystal display screen, this smectic liquid crystal display screen comprises first base layer and second base layer, between first base layer and second base layer, be provided with a mixolimnion that forms by smectic phase liquid crystal and additives mixed, this smectic phase liquid crystal is a category-A smectic phase liquid crystal organic compound, this additive is the compound of band conductive characteristic, be provided with first conductive electrode layer at first base layer towards a side of mixolimnion, be provided with second conductive electrode layer at second base layer towards a side of mixolimnion, first conductive electrode layer is made up of M strip shaped electric poles that is arranged in parallel, second conductive electrode layer is made up of N strip shaped electric poles that is arranged in parallel, N strip shaped electric poles of the M of first conductive electrode layer strip shaped electric poles and second conductive electrode layer is perpendicular, this first and second conductive electrode layer forms the pixel array of one M * N, it is characterized in that:
This display control circuit comprises control module, a M R ripple generation module and N D ripple generation module, and control module is connected with D ripple generation module with all R ripple generation modules, and R ripple generation module is connected with smectic liquid crystal display screen with D ripple generation module, wherein:
R ripple generation module comprises the first positive level converter unit, the first negative level converter unit, the first forward signal generation unit, the first negative-going signal generation unit and first signal synthesis unit, this first forward signal generation unit is connected with control module through the first positive level converter unit, this first negative-going signal generation unit is connected with control module through the first negative level converter unit, this first forward signal generation unit is connected with first signal synthesis unit with the first negative-going signal generation unit, and this first signal synthesis unit is connected with a strip shaped electric poles of described first conductive electrode layer;
D ripple generation module comprises the second positive level converter unit, the second negative level converter unit, the second forward signal generation unit, the second negative-going signal generation unit, the true amplitude control module, negative amplitude control module and secondary signal synthesis unit, this second forward signal generation unit is connected with control module through the second positive level converter unit, this second negative-going signal generation unit is connected with control module through the second negative level converter unit, just, negative amplitude control module respectively with the second forward signal generation unit, the second negative-going signal generation unit connects, this second forward signal generation unit is connected with the secondary signal synthesis unit with the second negative-going signal generation unit, and this secondary signal synthesis unit is connected with a strip shaped electric poles of described second conductive electrode layer.
2, display control circuit according to claim 1 is characterized in that:
The described first positive level converter unit comprises a CMOS phase inverter, the input end of this CMOS phase inverter links to each other with its corresponding signal output part on an electric capacity and described control module, the described first forward signal generation unit comprises a high pressure NMOS transistor, the transistorized grid of this high pressure NMOS links to each other with the output terminal of the CMOS phase inverter of the described first positive level converter unit, and this high pressure NMOS transistor drain links to each other with an input end of described first signal synthesis unit through an electric capacity;
The described first negative level converter unit comprises a CMOS phase inverter, the input end of this CMOS phase inverter links to each other with its corresponding signal output part on an electric capacity and described control module, the described first negative-going signal generation unit comprises a high voltage PMOS transistor, the grid of this high voltage PMOS transistor links to each other with the output terminal of the CMOS phase inverter of the described first negative level converter unit, and the drain electrode of this high voltage PMOS transistor links to each other with another input end of described first signal synthesis unit through an electric capacity.
3, display control circuit according to claim 2 is characterized in that:
Described first signal synthesis unit is made of a plurality of diodes.
4, display control circuit according to claim 1 is characterized in that:
The described second positive level converter unit comprises a CMOS phase inverter, the input end of this CMOS phase inverter links to each other with its corresponding signal output part on an electric capacity and described control module, the described second forward signal generation unit comprises a high pressure NMOS transistor, the transistorized grid of this high pressure NMOS links to each other with the output terminal of the CMOS phase inverter of the described second positive level converter unit, this high pressure NMOS transistor drain is divided into two-way, one the tunnel links to each other with described true amplitude control module through a resistance, and another Lu Jingyi electric capacity links to each other with an input end of described secondary signal synthesis unit;
The described second negative level converter unit comprises a CMOS phase inverter, the input end of this CMOS phase inverter links to each other with its corresponding signal output part on an electric capacity and described control module, the described second negative-going signal generation unit comprises a high voltage PMOS transistor, the grid of this high voltage PMOS transistor links to each other with the output terminal of the CMOS phase inverter of the described second negative level converter unit, the drain electrode of this high voltage PMOS transistor is divided into two-way, one the tunnel links to each other with described negative amplitude control module through a resistance, and another Lu Jingyi electric capacity links to each other with another input end of described secondary signal synthesis unit.
5, display control circuit according to claim 4 is characterized in that:
Described secondary signal synthesis unit is made of a plurality of diodes.
6, display control circuit according to claim 4 is characterized in that:
Described true amplitude control module and negative amplitude control module are transformer.
7, according to each the described display control circuit in the claim 1 to 6, it is characterized in that:
Described control module is single-chip microcomputer or FPGA.
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| CNU2007201909553U CN201134234Y (en) | 2007-12-27 | 2007-12-27 | Display controlling circuit |
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| CNU2007201909553U CN201134234Y (en) | 2007-12-27 | 2007-12-27 | Display controlling circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376260A (en) * | 2010-08-27 | 2012-03-14 | 北京凡达讯科技有限公司 | Method for keeping stability of output voltage pulse of electronic paper |
| CN102479490A (en) * | 2010-11-22 | 2012-05-30 | 苏州汉朗光电有限公司 | Driving method for full-screen gray scale correction of smectic liquid crystal display |
| US9417470B2 (en) | 2011-09-14 | 2016-08-16 | Cambridge Enterprise Limited | Driver circuit |
-
2007
- 2007-12-27 CN CNU2007201909553U patent/CN201134234Y/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376260A (en) * | 2010-08-27 | 2012-03-14 | 北京凡达讯科技有限公司 | Method for keeping stability of output voltage pulse of electronic paper |
| CN102479490A (en) * | 2010-11-22 | 2012-05-30 | 苏州汉朗光电有限公司 | Driving method for full-screen gray scale correction of smectic liquid crystal display |
| CN102479490B (en) * | 2010-11-22 | 2013-05-22 | 苏州汉朗光电有限公司 | Driving method for full-screen gray scale correction of smectic liquid crystal display |
| US9417470B2 (en) | 2011-09-14 | 2016-08-16 | Cambridge Enterprise Limited | Driver circuit |
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Effective date of registration: 20091016 Address after: B 18, International Building, No. 100081, South Main Street, Beijing, Haidian District, Beijing, 311, postcode: Patentee after: Chen Yuanyuan Address before: Science and Engineering Building 9, 100081 South Avenue, Beijing, Haidian District, 2017, postcode: Patentee before: Hanlang Technology (Beijing) Co., Ltd. |
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