CN201072757Y - Thin film flip-chip packaging - Google Patents
Thin film flip-chip packaging Download PDFInfo
- Publication number
- CN201072757Y CN201072757Y CN 200720072565 CN200720072565U CN201072757Y CN 201072757 Y CN201072757 Y CN 201072757Y CN 200720072565 CN200720072565 CN 200720072565 CN 200720072565 U CN200720072565 U CN 200720072565U CN 201072757 Y CN201072757 Y CN 201072757Y
- Authority
- CN
- China
- Prior art keywords
- chip
- soft board
- membrane
- encapsulation
- pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004806 packaging method and process Methods 0.000 title description 4
- 239000010409 thin film Substances 0.000 title description 3
- 238000005538 encapsulation Methods 0.000 claims abstract description 36
- 239000012528 membrane Substances 0.000 claims description 30
- 238000007789 sealing Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 10
- 239000004642 Polyimide Substances 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 229920000728 polyester Polymers 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000004382 potting Methods 0.000 abstract description 3
- 238000004804 winding Methods 0.000 abstract description 3
- 150000001875 compounds Chemical class 0.000 abstract 2
- 238000005516 engineering process Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 4
- 239000003292 glue Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000000084 colloidal system Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- -1 PI) Polymers 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000005355 lead glass Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
The utility model discloses a COF encapsulation, which is mainly composed of a soft board, a plurality of pins and two marking lines. The soft board is provided with a chip joint zone for loading a chip. The pins are arranged on the soft board, one end of the pins extends into the chip joint zone and electrically connected with the chip. The two marking lines are arranged outside the two corresponding side edges of the chip joint zone and cross the pins for defining a largest potting compound zone, wherein, the marking lines and the pins are electrically insulated. The marking line is beneficial for judging if the enforced potting compound affect the winding and folding of the soft board, thus improving the yield of the COF encapsulation product.
Description
Technical field
The utility model relates to a kind of membrane of flip chip encapsulation, and particularly is provided with the membrane of flip chip encapsulation that indicates line relevant for a kind of soft board.
Background technology
In semiconductor industry, (Integrated Circuits, production IC) mainly is divided into three phases to integrated circuit: the encapsulation (Package) of the design of integrated circuit, the making of integrated circuit and integrated circuit etc.Wherein, bare chip is via steps such as wafer (Wafer) making, circuit design, light shield manufacture and cutting crystal wafers and finish, and each cuts formed bare chip by wafer, after weld pad on the bare chip (Bonding Pad) and external signal electric connection, with adhesive material bare chip is coated again.The purpose of encapsulation is to prevent that bare chip is subjected to moisture, heat and The noise, and the media that electrically connects between bare chip and the outer enclosure substrate is provided, and so promptly finishes the encapsulation (Package) of integrated circuit.
The mode that early stage encapsulation technology adopts routing to engage more, and with the base plate for packaging of printed circuit board (PCB) (Printed CircuitBoard is called for short PCB) as carries chips, yet its shortcoming is that cost of manufacture is higher and volume is bigger.In recent years,, cause semi-conductive high density IC package requirements, make the encapsulation technology of integrated circuit also constantly develop towards microminiaturization and densification along with the rise of portable electronic product and flat-panel screens product.With display panels (LCD Panel), winding engages (Tape AutomaticBonding automatically, abbreviation TAB) technology is for further reducing cost, dwindle the volume of chip-packaging structure, and the integration of raising circuit, by winding carrying encapsulation (Tape Carrier Package, be called for short TCP) turn to gradually and cover crystal glass (Chip on Glass, be called for short COG) and membrane of flip chip encapsulation (Chip on Film, be called for short COF) etc. encapsulation technology, and become main flow in the LCD chip for driving encapsulation technology.
The membrane of flip chip encapsulation technology be for a kind of with small pieces by chip bonding (Flip Chip Bonding) technology, and for example be electrically connected at the technology of flexible circuit board bendable carriers such as (Flexible Printed Circuit Board are called for short FPC).In other words, covering brilliant thin-film package technology is the printed circuit board (PCB) that saves in the past, and drive IC and electronic component thereof directly are disposed on the soft board, reaching the purpose that makes chip-packaging structure more compact, and can have the function that connects panel and carry main passive device concurrently.In addition, with other encapsulation technologies by contrast, cover brilliant thin-film package technology and have more pliability (Flexible) and little spacing advantages such as (Fine Pitch).
Fig. 1 illustrates the generalized section into existing a kind of package structure membrane of flip chip package.Please refer to Fig. 1, the pin 112 of this package structure membrane of flip chip package 100 is to be disposed on the soft board 110, and this chip 120 is to see through projection 130 to electrically connect with pin 112.When the gluing operation of carrying out membrane of flip chip encapsulation, adhesive material 140 is to coat chip 120 peripheries, utilizes capillarity to make it evenly flow between chip 120 and the soft board 110 again and coats these projections 130.
Yet, the membrane of flip chip product is when carrying out encapsulation procedure, and can't obviously judge the packing colloid that is applied and whether exceed allowable range, therefore, the situation of back processing procedure around folding may appear influencing in packing colloid, cause the inconvenience in the successive process operation, and then influence the yield of entire product.
Summary of the invention
The utility model provides a kind of membrane of flip chip encapsulation, this encapsulating structure is to be provided with one respectively to indicate line outside the corresponding dual-side of the chip bonding area of soft board, indicate line by these two and on soft board, define a maximum sealing region (maximum potting area), be beneficial to judge the sealing that is applied whether influence soft board around folding, and then promote the yield of membrane of flip chip encapsulating products.
The utility model proposes a kind of membrane of flip chip encapsulation, comprise that mainly a soft board, a plurality of pin and two indicate line.Soft board has a chip bonding area, to carry a chip.A plurality of pin configuration are on soft board, and an end of these pins extends in the chip bonding area, and electrically connect with chip.Two indicate line is arranged at outside the corresponding dual-side of chip bonding area, and across above-mentioned pin, to define a maximum sealing region, wherein this sign line and above-mentioned pin are electrically insulated.
In membrane of flip chip of the present utility model encapsulation, above-mentioned sign line is made up of a metal material, and this membrane of flip chip encapsulation also comprises an insulating barrier, is disposed between above-mentioned pin and the sign line.Further, this metal material comprises copper.
In membrane of flip chip encapsulation of the present utility model, above-mentioned sign line is made up of nonmetallic materials.Further, these nonmetallic materials comprise polyimides (Polyimide), polyester (PET) or epoxylite (Epoxy).
Membrane of flip chip encapsulation of the present utility model is to be provided with one respectively to indicate line outside the corresponding dual-side of the chip bonding area of soft board, indicate line by these two and on soft board, define a maximum sealing region, clearly to define the sealing scope of soft board that do not influence around folding.This indicates being provided with of line will help judging the required scope that applies sealing, and the situation of the excessive glue of unlikely generation.In addition, these two indicate line also can be used as the membrane of flip chip encapsulating products around the folding reference line, so that the operation when follow-up display panels is connected with soft board.Moreover the setting that indicates line also helps to increase the structural strength of soft board, to prevent soft board buckling deformation in successive process.
Description of drawings
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent, below in conjunction with accompanying drawing embodiment of the present utility model is elaborated, wherein:
Fig. 1 illustrates the generalized section into existing a kind of package structure membrane of flip chip package.
Fig. 2 illustrates the schematic top plan view into membrane of flip chip encapsulation of the present utility model.
Embodiment
Fig. 2 illustrates the schematic top plan view into membrane of flip chip encapsulation of the present utility model.Please refer to Fig. 2, this membrane of flip chip encapsulation 200 comprises that mainly a soft board 210, a plurality of pin 212 and two indicate line 220a, 220b.Below collocation is illustrated element that membrane of flip chip encapsulation comprised and the annexation between each element.
The surface of soft board 210 has a chip bonding area C, to carry a chip 230.The material of soft board 210 can be selected resin materials such as polyimides for use.And chip 230 can be in order to drive the chip for driving of display panels.A plurality of pins 212 are to be disposed on the soft board 210, one end of these pins 212 extends in the chip bonding area C, and electrically connect with chip 230, and the other end of these pins 212 is in order to electrically connect with display panels or printed circuit board (PCB), chip 230 can be electrically connected by these pins 212 and display panels or printed circuit board (PCB).
Two indicate line 220a, 220b is disposed on the soft board 210, and these two sign line 220a, 220b are positioned at outside the corresponding dual-side of chip bonding area C, and across above-mentioned pin 212, to define a maximum sealing region 214.This indicates line 220a, 220b and above-mentioned pin 212 is electrically insulated.The utility model mainly is to go out a maximum sealing region 214 by this configuration definition that indicates line 220a, 220b, is beneficial to judge the scope of required coating sealing, and the situation of the excessive glue of unlikely generation.In addition, indicate line 220a, 220b and also can be used as the reference line of product, to make things convenient for upper plate operation (operation that display panels is connected with soft board 210) around folding.Moreover the setting that indicates line 220a, 220b also helps to increase the structural strength of soft board 210, to prevent soft board 210 buckling deformation in successive process.
Above-mentioned sign line 220a, 220b can be made of metal material or nonmetallic materials.When (for example: when copper) forming indicating line 220a, 220b by metal material, membrane of flip chip encapsulation 200 comprises that also one is disposed at the insulating barrier (not shown) between pin 212 and sign line 220a, the 220b, and pin 212 and sign line 220a, 220b are electrically insulated.In addition, indicate line 220a, 220b and also can be formed by nonmetallic materials, for example: polyimides (Polyimide, PI), polyester (PET) or epoxylite (epoxy).
In sum, membrane of flip chip encapsulation of the present utility model mainly is to be provided with one respectively to indicate line outside the corresponding dual-side of the chip bonding area of soft board, indicates line by these two and define a maximum sealing region on soft board.So, will help judging the scope of the sealing that applies, and the situation of the excessive glue of unlikely generation.In addition, these two sign lines also can be used as the reference line of product around folding, so that the operation when follow-up display panels is connected with soft board.Moreover the setting that indicates line also helps to increase the structural strength of soft board, to prevent soft board buckling deformation in successive process.
Though the utility model discloses as above with preferred embodiment; right its is not in order to limit the utility model; any those skilled in the art; in not breaking away from spirit and scope of the present utility model; when doing a little modification and perfect, therefore protection range of the present utility model is worked as with being as the criterion that claims were defined.
Claims (5)
1. a membrane of flip chip encapsulation is characterized in that, comprising:
One soft board has a chip bonding area, to carry a chip;
A plurality of pins are disposed on this soft board, and an end of those pins extends in this chip bonding area, and electrically connect with this chip; And
Two indicate line, are arranged on this soft board, and those indicate line and are positioned at outside the corresponding dual-side of this chip bonding area, and across those pins, to define a maximum sealing region, wherein those sign lines and those pins are electrically insulated.
2. membrane of flip chip as claimed in claim 1 encapsulation is characterized in that, those indicate lines is made up of a metal material, and this membrane of flip chip encapsulation also comprises an insulating barrier, is disposed between those pins and those sign lines.
3. membrane of flip chip encapsulation as claimed in claim 2 is characterized in that this metal material comprises copper.
4. membrane of flip chip encapsulation as claimed in claim 1 is characterized in that those indicate line and are made up of nonmetallic materials.
5. membrane of flip chip encapsulation as claimed in claim 4 is characterized in that these nonmetallic materials comprise polyimides, polyester or epoxylite.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200720072565 CN201072757Y (en) | 2007-07-18 | 2007-07-18 | Thin film flip-chip packaging |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200720072565 CN201072757Y (en) | 2007-07-18 | 2007-07-18 | Thin film flip-chip packaging |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201072757Y true CN201072757Y (en) | 2008-06-11 |
Family
ID=39551313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200720072565 Expired - Fee Related CN201072757Y (en) | 2007-07-18 | 2007-07-18 | Thin film flip-chip packaging |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201072757Y (en) |
-
2007
- 2007-07-18 CN CN 200720072565 patent/CN201072757Y/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6952250B2 (en) | Pressure-welded structure of flexible circuit boards | |
| KR100987479B1 (en) | Semiconductor chip and semiconductor chip package using the same | |
| KR100652519B1 (en) | Tape substrate comprising dual metal layer and chip on film package using the same | |
| US7649246B2 (en) | Tab package connecting host device element | |
| TW557522B (en) | Semiconductor device | |
| US10903127B2 (en) | Film for a package substrate | |
| US7109575B2 (en) | Low-cost flexible film package module and method of manufacturing the same | |
| US7589421B2 (en) | Heat-radiating semiconductor chip, tape wiring substrate and tape package using the same | |
| US11133262B2 (en) | Semiconductor packages and display devices including the same | |
| US20110182046A1 (en) | Electronic circuit device, method for manufacturing the same, and display device | |
| US20110169022A1 (en) | Board module and method of manufacturing same | |
| JP2005311321A (en) | Semiconductor device and its manufacturing method, and liquid crystal module/semiconductor module provided with the semiconductor device | |
| CN109844943B (en) | Laminated graphite chip-on-film semiconductor package with improved heat dissipation and electromagnetic wave shielding | |
| JP4252518B2 (en) | Semiconductor device | |
| US20090065934A1 (en) | Wiring substrate, tape package having the same, display device having the tape package, method of manufacturing the wiring substrate, method of manufacturing a tape package having the same and method of manufacturing a display device having the tape package | |
| TW539904B (en) | Tape carrier, manufacturing method for the tape carrier, and manufacturing method | |
| JP2005129846A (en) | Semiconductor device and its manufacturing method, electronic module and electronic equipment | |
| CN103972201A (en) | Package structure and display module | |
| KR100252051B1 (en) | Tap tape having a camber protecting layer | |
| TWI773855B (en) | Film substrate structure,chip-on-film package, and package module | |
| US8266796B2 (en) | Method of fabricating a semiconductor device package | |
| CN201072757Y (en) | Thin film flip-chip packaging | |
| CN102915989B (en) | Chip packaging structure | |
| CN100407420C (en) | Semiconductor device and method for making same, circuit base plate and electronic device | |
| KR102250825B1 (en) | Cof package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080611 Termination date: 20120718 |