CN201061132Y - Channel switching tester - Google Patents

Abstract

The utility model discloses a channel exchange test device, comprising a signal process unit, an attenuator, a frequency mixer, a narrowband filter, a rectifier circuit, a peak value extracting circuit, a microprocessor of A/D switching circuit or a CPU, which are arranged in a channel communicator or a channel receiver to form a start level generator of device. The utility model is characterized in also comprising a filed programmable controller FPGA or CPLD and a comparator, wherein, the channel signal is connected with the attenuator, the frequency mixer, the narrowband filter, the rectifier circuit, the peak value extracting circuit, and the microprocessor of A/D switching circuit or the CPU in order; the output of the peak value extracting circuit and the device start level are connected with the input of the comparator respectively; the output of the comparator is connected with the filed programmable controller FPGA; the data port and control port of the FPGA are connected with the corresponding interface of the microprocessor or CPU; the output port of the microprocessor or CPU is connected with a display; the signal input or output of the communicator or receiver is connected with the data input of the FPGA or CPLD via an isolator.

Description

The channel exchange test device

Technical field

The utility model relates to the relaying protection field that cooperates with high-voltage line protection in the electric power system, judges that high-voltage power line is main channel exchange test intelligent judging device.

Background technology

Common power line carrier transreceiver and route protection constitute the high frequency blocking protection together and need transmit the high frequency block signal by the passage based on high-voltage power line, so whether passage is crucial to the high frequency blocking protection normally.In order to guarantee that passage is normal, the field operator needs every day and does the quality that channel exchange test comes sense channel.Usually the operations staff judges that the quality of channel exchange test mainly is by observing waving of transceiver power gauge outfit, and whether just look at the 3dB stand by lamp of transceiver bright, and the needs that perhaps also have are seen protective device displacement situation or the like.There is a lot of inconvenience in these methods, and at first the operations staff could judge whether passage is normal after need observing a plurality of amounts, and secondly artificial judgement causes the phenomenon of failing to judge and judging by accident easily.

In the channel exchange test, the channel power level is a very important index of transceiver another one, the operations staff often need know on the one hand that the channel power level judges the quality of passage, need on the other hand to know the channel power level know transceiver post a letter level and the starting level, and the channel power level value still is the foundation that transceiver " collection of letters " output and " 3dB alarm " output produce, if therefore can provide transceiver, then greatly facilitate on-the-spot operation and attendant with the real-time measurement function of power.

Described high frequency block signal essence is the sine wave signal of single-frequency, the sine wave signal that sends correct frequency for the transmitting end transceiver causes the pass and wants, if the frequency of transceiver power amplifier amplifying signal frequency and line filter is inconsistent, then have signal and send out the situation of not coming out, perhaps the frequency sent of transmitting end transceiver and the inconsistent situation that then can cause the end transceiver of collecting mail to have no idea to receive signal of frequency of collecting mail the end transceiver.

The method that at present domestic transceiver produces frequency has two kinds usually; a kind of frequency synthesis mode that is to use based on phase-locked loop; another is based on the directly mode of synthetic (DDS) of numerical frequency; if but the synthetic problematic situation of the frequency of occurrences in the device running (as sine wave freuqency because device aging etc. change or do not have sinusoidal signal to generate because chip damages at all); transceiver does not provide corresponding measure to judge, if the outer transmission line malfunction of generating region then can cause the situation of protective device malfunction at this moment.

Summary of the invention

The utility model purpose is: proposed a kind of channel exchange test device, overcome the deficiency that existing artificial judgment channel exchange test brings, provide a kind of power intelligent to judge the device of channel exchange test, do not need the operations staff to participate in the judgement of channel exchange test, only need to wait for that transceiver provides the result of channel exchange test on man-machine interfaces such as liquid crystal, also demonstrate the reason of failure if channel exchange test is failed.

The technical scheme that the utility model adopted is: a kind of channel exchange test device, place the signal processing unit of passage sender or receiver, attenuator, frequency mixer, narrow band filter, rectification circuit and peak extraction circuit, A/D and microprocessor or CPU constitute, device starting level generator, it is characterized in that being provided with in addition field-programmable controller FPGA or CPLD, comparator, connect in the following manner, channel signal connects attenuator according to the order of sequence, frequency mixer, narrow band filter, rectification circuit and peak extraction circuit, A/D change-over circuit microprocessor or CPU, the output of described peak extraction circuit and device starting level connect comparator input terminal respectively, comparator output terminal connects field-programmable controller FPGA or CPLD, and the FPDP of FPGA or CPLD is connected microprocessor or CPU with control port respective end interface connects; The output port of microprocessor or CPU connects display; The signal of sender or receiver inputs or outputs end connects FPGA or CPLD by an isolator data input pin.

The channel exchange test device can carry out channel power and measure: sinusoidal signal decay that at first will be measured afterwards and local carrier frequency carry out mixing to obtain the difference frequency frequency be certain integer frequency signal in the 0.5-10M interval; Sinusoidal signal as 1MHz, to adopt centre frequency then be integer frequency signal (as 1MHz) narrow band filter other frequency content of filtering and extract and measure needed 1MHz signal, again 1MHz frequency sinusoidal signal is carried out obtaining DC level after precision rectifying and the peak extraction, obtain the relation of DC level value according to sinusoidal signal power and rectification, just measure the power of sinusoidal signal by the sampling DC level.

Carry out frequency measurement by the sender end again, it with frequency the sine wave of X (KHz) square-wave signal that to obtain a frequency after through a comparator shaping be X (KHz), the frequency divider that is Z through a divide ratio then, the square wave of same frequency is carried out frequency division produce low-frequency square wave, just can obtain the square-wave signal that frequency is Y (KHz); Again low-frequency square-wave cycle is carried out precise time and measure, by measuring the time that the low frequency square-wave cycle obtains and the multiple reduction sine wave freuqency of frequency divider frequency division; In measuring process, a counter is set, this counter is in the rising edge zero clearing of square wave and begin counting, zero clearing and carry out the counting of next round once more after the rising edge arrival hour counter of next square wave is saved in another register with count value; If it is K that counter whenever added for 1 used time, the count value that register holds is got off is M, then obtains:

$Y=\frac{1}{M*K}---\left(1\right)$

Know again

X＝Y*Z (2)

Have by (1) and (2)

$X=\frac{Z}{M*K}---\left(3\right)$

So just obtained the frequency X of required measurement.

Described channel exchange test intelligent decision is with the timing microprocessor of transceiver transceiver switching value " collection of letters " and " posting a letter " to be sampled, logic by these two switching values and transceiver channel exchange test compares, contrast again and have or not passage 3dB to fall alarm in the passage process of the test to produce, judge the success or failure of channel exchange test:

1) microprocessor is judged by splitting " to post a letter " into amount, if " posting a letter " is that time of 1 is 200 ± 10 milliseconds, thinks that then channel exchange test begins;

2) after microprocessor thinks that channel exchange test begins, split into " posting a letter " and leave " collection of letters " and carry out continuous monitoring, if " collection of letters " satisfies continuous 15.2 ± 0.2 seconds is 1, and the amount of " posting a letter " also is 1 in " collection of letters " is last 10 ± 0.1 second time of 1, judges that then the channel exchange test logic finishes;

3) when step 2) finish after, microprocessor checks in " collection of letters " is time of 1 do not have passage 3dB to fall alarm, the then whole channel exchange test success of final decision; If step 2) judges in that the channel exchange test logic do not finish or have passage 3dB to fall that any one does not satisfy in the alarm, then judge the channel exchange test failure.

4) begin when channel exchange test, and after the deterministic process of whole channel exchange test is finished, microprocessor can be exported the result of judgement and the record wave-wave shape of being made up of " channel levels ", " posting a letter " and " collection of letters ", also exports the reason of concrete failure if channel exchange test is failed

The utility model beneficial effect is: make transceiver monitor in real time and to detect channel power and frequency, transceiver can in time recover the frequency of setting under the situation that the running medium frequency is made mistakes, can produce the alarm notification operations staff if can't recover, avoided because the serious consequence that frequency errors may cause, improved the reliability of transceiver greatly; The channel power assessment function can be measured the level of posting a letter, starting level and the collection of letters level of transceiver easily, make the staff directly obtain the power level of passway with digital form, and do not need again to have simplified field operator and work of maintenance personnel flow process greatly by means of special measuring instrument.

The success or failure of the open close road of the utility model exchange test can be simplified operations staff's work with the method that microcomputer-based intelligent is judged

Description of drawings

Fig. 1 is the transceiver channel exchange test switching value standard time sequence figure that posts a letter and collect mail

Fig. 2 judges the judgement schematic diagram that channel exchange test begins for the utility model

Fig. 3 judges the schematic diagram whether the channel exchange test logic is finished for the utility model

Fig. 4 is the utility model channel exchange test and 3dB warning relation figure

Fig. 5 is that the utility model channel exchange test is judged back display interface schematic diagram

A among the figure, B are the transceiver of transmission line both sides, and A is the originating end of channel exchange test, and chronomere is millisecond or second.

Fig. 6 is the circuit block diagram of the utility model Channel Exchange device

Fig. 7 is a circuit diagram

Embodiment

The utility model is described in further detail below in conjunction with the drawings and specific embodiments.

Power measurement: stipulate that in the power industry standard DL/T 524-2002 of the People's Republic of China (PRC) the uneven I/O impedance of transceiver is 75 Ω, so can finish power measurement by the mode of measuring voltage.Because the general power ratio that sends and receive of transceiver is big (generally more than or equal to 10W),, handle again after it must being decayed to small-signal so can not directly handle to the signal on the passage.Why mixing produces the signal of 1MHz, be to finish all filtering requirements because make the narrow band filter that can use a fixed center frequency like this, when measured sine wave signal frequency changes, the work that need make is just with the corresponding change of local mixed frequency signal frequency, this accomplishes very easily, and narrow band filter need not to do any change, greatly reduces the requirement to filter.Sinusoidal signal is that frequency is original 2 times signal by the precise rectification circuit rectification, and then extracts the peak value of signal after the rectification, can make the extraction of peak value more easier.Record compensated curve by the method for power being estimated loop adding known signal, DC level is compensated, can improve the accuracy that channel power is estimated.

Theoretical derivation is: establishing channel signal is Asin 2 π f _XT, local mixed frequency signal are Bsin 2 π f _YT, wherein f _X+ f _Y=1MHz has behind two signal mixings:

$A\sin 2\mathrm{\π}{f}_X{t}^{*}B\sin 2\mathrm{\π}{f}_{Y}t=-\frac{\mathrm{AB}}{2}[\cos 2\mathrm{\π}(f_X+f_Y)t-\cos 2\mathrm{\π}(f_X-f_Y)t]---\left(8\right)$

(8) formula becomes behind the narrow band filter that by centre frequency is 1MHz:

$A\sin 2\mathrm{\π}{f}_X{t}^{*}B\sin 2\mathrm{\π}{f}_{Y}t\⇒-\frac{\mathrm{AB}}{2}\cos 2\mathrm{\π}(f_X+f_Y)t=-\frac{\mathrm{AB}}{2}\cos 2\mathrm{\π}{10}^{6}t---\left(9\right)$

Can know 1MHz waveform peak after the mixing from (9) formula $V_P=\frac{\mathrm{AB}}{2},$ If the peak value that measures is V _MP, again because B is a given value, therefore have:

$V_{\mathrm{MP}}=V_P=\frac{\mathrm{AB}}{2}\⇒A=\frac{2V_{\mathrm{MP}}}{B}---\left(10\right)$

If above derivation explanation know and the power measurement of signal on the passage come out the peak value of 1MHz sinusoidal signal after the mixing with regard to being easy to.

In the utility model, the method that the channel exchange test criterion has adopted microprocessor intelligence to judge is finished.Fig. 1 finishes the standard time sequence figure of the posting a letter of channel exchange test and the switching value of collecting mail for transceiver, A wherein, B is the transceiver of transmission line both sides, dash area is A, the period that two transceivers of B are posted a letter jointly, A is the originating end of channel exchange test in this sequential chart.By standard time sequence figure, the method that the utility model proposes intelligent decision channel exchange test result has three steps.1) microprocessor is judged by splitting " to post a letter " into amount, be that time of 1 is 200 ± 10 milliseconds (positive and negative 10 milliseconds is because consider the error that each producer causes owing to the timing inaccuracy) if " post a letter ", think that then the transceiver channel exchange test begins; As shown in Figure 2.2) after microprocessor thinks that channel exchange test begins, split into " posting a letter " and leave " collection of letters " and carry out continuous monitoring, if " collection of letters " satisfies continuous 15.2 ± 0.2 seconds is 1, and the amount of " posting a letter " also is 1 in " collection of letters " is last 10 ± 0.1 second time of 1, judges that then the channel exchange test logic finishes; As shown in Figure 3.3) after condition 2 satisfies, microprocessor checks in " collections of letters " is time of 1 whether have passage 3dB to fall alarm, and if not the whole channel exchange test of final decision successfully.As shown in Figure 4.As long as any one does not satisfy in the condition 2 and 3, then channel exchange test will be determined failure.When condition 1 satisfies, and after the deterministic process that whole Tong Sei exchange Lun tests is finished, microprocessor can with liquid crystal display screen that it is connected on show mouthful record wave-wave shape that the result who judges is made up of " channel levels ", " posting a letter " and " collection of letters " with Ke,, channel exchange test also demonstrates the reason of concrete failure if judging failure, as shown in Figure 5.Warn among Fig. 5: passage test failure, 3dB level down.

With reference to the accompanying drawings:

Among Fig. 1, t1=200ms; T2=5.2s; T3=10s; T4=10s; T5=15.2s

1) among Fig. 3, t1=200ms; If t5=14.80s, then channel exchange test failure; T5=15.10s, t3=9.7s, then channel exchange test failure; If t5=15.10s, t3=9.95s, then the channel exchange test logic is finished, success.

Among Fig. 4, t1, t3, t5 Jun Man II step 2) in require the time, and in time t5, do not have passage 3dB to fall alarm, then channel exchange test success.

Place the signal processing unit of passage sender or receiver, attenuator, frequency mixer, narrow band filter, rectification circuit and peak extraction circuit, A/D and microprocessor or CPU constitute, device starting level generator, other is provided with field-programmable controller FPGA or CPLD, comparator, connect in the following manner, does channel signal connects attenuator according to the order of sequence, and (circuit roughly constitute?), frequency mixer, narrow band filter, (circuit roughly constitutes several Fig. 7 for rectification circuit and peak extraction circuit, A/D change-over circuit model, DSP microprocessor or CPU model are seen figure), the output of described peak extraction circuit and device starting level connect comparator input terminal respectively, comparator (amplifier) output connects field-programmable controller FPGA or CPLD, and the FPDP of FPGA or CPLD is connected microprocessor or CPU with control port respective end interface connects; The output port of microprocessor or CPU connects display; The signal of sender or receiver inputs or outputs end connects FPGA or CPLD model by an isolator data input pin.

Transceiver is in the passage process of the test, the passage upper frequency is X (KHz), after the signal attenuation of X≤400 and frequency be the signal that the narrow band filter of 1MHz obtains 1MHz through centre frequency then for (1000-X) signal mixing (KHz), the signal of 1MHz obtains DC level after by precision rectifying and peak extraction and is sampled, sampled data is sent to DSP and carries out the estimation of channel signal power, DSP compares with the channel power value that channel power that estimates and user set, if more than the little 3dB of channel power value of the channel power that estimates than user's setting, then to fall alarm (3dBWarning) switching value be 1 to 3dB, otherwise be 0.DC level after the peak extraction also have simultaneously one the tunnel be sent to comparator and the device starting level ratio that configures, when direct current signal is 1 greater than the device starting level output switching value RCV that collects mail, otherwise be 0.Open into the letter signal process and isolate back (TX) the same FPGA of being sent to, in FPGA, carry out anti-shake processing, and form the value of register corresponding positions among the FPGA with RCV and 3dBWarning.

In whole passage process of the test, DSP is by regularly reading the value that FPGA monitors TX, RCV and 3dBWarning, whether and it is normal to judge whole passage test according to the value that monitors, result and waveform after judging are shown to the user by the LCD man-machine interface, and whole process does not need the user to participate in, and has accomplished intelligent effect.

Referring to Fig. 7 circuit diagram, specifically see the chip model.

Claims (1)

1. channel exchange test device, place the signal processing unit of passage sender or receiver, comprise attenuator, frequency mixer, narrow band filter, rectification circuit and peak extraction circuit, A/D and microprocessor or CPU constitute, device starting level generator, it is characterized in that being provided with in addition field-programmable controller FPGA or CPLD, comparator, connect in the following manner, channel signal connects attenuator according to the order of sequence, frequency mixer, narrow band filter, rectification circuit and peak extraction circuit, A/D change-over circuit microprocessor or CPU, the output of described peak extraction circuit and device starting level connect comparator input terminal respectively, comparator output terminal connects field-programmable controller FPGA or CPLD, and the FPDP of FPGA or CPLD is connected microprocessor or CPU with control port respective end interface connects; The output port of microprocessor or CPU connects display; The signal of sender or receiver inputs or outputs end connects FPGA or CPLD by an isolator data input pin.

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