CN201044435Y - Power up time delay circuit - Google Patents
Power up time delay circuit Download PDFInfo
- Publication number
- CN201044435Y CN201044435Y CNU2007201204533U CN200720120453U CN201044435Y CN 201044435 Y CN201044435 Y CN 201044435Y CN U2007201204533 U CNU2007201204533 U CN U2007201204533U CN 200720120453 U CN200720120453 U CN 200720120453U CN 201044435 Y CN201044435 Y CN 201044435Y
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- voltage
- delay circuit
- triode
- powers
- resistance
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Abstract
The utility model is suitable for the power supply circuit field and provides a power-up delay circuit comprising a MOS pipe. The circuit also comprises a thermistor connected with a power supply voltage input end as well as an output end, divider resistors R(2) and R(4) which are connected with the connecting point of the thermistor and the output end for dividing voltage, a triode which has the b pole connected with the connecting point of the divider resistors R(2) and R(4) and has the e pole earthed, and divider resistors R(5) and R(6) which are connected with the c pole of the triode to transmit divided voltage to the MOS pipe. The utility model adopts the thermistor, the triode and the divider resistors, and transmits input voltage to the output end via the MOS pipe when the divided voltage reaches the break-over voltage of the triode and the voltage of the MOS pipe reaches to break-over voltage, so as to realize power-up delay through hardware, which solves the problems that the prior power-up delay circuit is high in cost and occupies system resources.
Description
Technical field
The utility model belongs to the power supply circuits field, relates in particular to a kind of delay circuit that powers on.
Background technology
The general chip with the delay function that powers on that adopts utilizes the I/O mouth of chip to control the conducting of metal-oxide-semiconductor (insulated type field effect transistor) in the delay circuit that powers on of prior art, thereby reaches the purpose of the time-delay that powers on.
But, when adopting chip to realize powering on time-delay, not only increase cost, but also occupying system resources.
The utility model content
The purpose of this utility model is to provide a kind of delay circuit that powers on, and is intended to solve the problem of existing power on delay circuit cost height, occupying system resources.
The utility model is achieved in that a kind of delay circuit that powers on, and comprises metal-oxide-semiconductor, and first pin of metal-oxide-semiconductor is connected with the supply power voltage input, and crus secunda is connected with output, and described circuit also comprises:
Thermistor is connected with supply power voltage input and output;
Divider resistance R (2), R (4) are connected with the tie point of output with described thermistor, and the voltage of its tie point is carried out dividing potential drop;
Triode, the b utmost point is connected e utmost point ground connection with the tie point of described divider resistance R (2), R (4);
And
Divider resistance R (5), R (6) are connected with the c utmost point of described triode, will carry out voltage after partial and be transferred to described metal-oxide-semiconductor.
The delay circuit that powers on of the present utility model adopts thermistor, triode and divider resistance, reach the conducting voltage of triode in the divider resistance voltage after partial, and the voltage of metal-oxide-semiconductor makes input voltage be transferred to output through metal-oxide-semiconductor when reaching conducting voltage, thereby utilize the hardware time-delay that realized powering on, solve the existing delay circuit cost height that powers on, take the problem of system.
Description of drawings
Fig. 1 is the circuit diagram of the delay circuit that powers on that provides of the utility model.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer,, the utility model is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
The delay circuit that powers on of the present utility model adopts thermistor, triode and divider resistance, conducting by thermistor change in resistance Characteristics Control triode, and metal-oxide-semiconductor conducting when the voltage of the crus secunda of the metal-oxide-semiconductor that is connected with divider resistance reaches conducting voltage, realize powering on time-delay.
As shown in Figure 1, the delay circuit that powers on of the present utility model comprises thermistor R1, divider resistance R2, R4, triode Q2, divider resistance R5, R6 and metal-oxide-semiconductor Q1.
After the delay circuit that powers on powers on, the voltage of the other end of the thermistor R1 that is connected with the supply power voltage input (being the output voltage of output (to IC power pin)) U1=VCC-I*R1 originally.Thermistor R1 generates heat because there is electric current to pass through, thereby resistance reduces, and U1 slowly rises.Resistance R 2 and R4 and thermistor R1 are connected in parallel, and voltage U 1 is carried out dividing potential drop.Because U1 slowly rises, resistance R 2 also slowly rises with the voltage U 4 of the tie point of R4.
Voltage U 4 can be used following formulate:
U4＝U1*R4/(R2+R4)
Resistance R 2 is connected with the b utmost point of triode Q2 with the tie point of R4, and the c utmost point of triode Q2 is connected with the grid of resistance R 6 and metal-oxide-semiconductor Q1 respectively through resistance R 5.Resistance R 6 is connected with the voltage input end of resistance R 1, and metal-oxide-semiconductor Q1 is connected with the two ends of resistance R 1 respectively.Resistance R 6 is U2 with the voltage of the link of the c utmost point of triode Q2.Therefore, when voltage U 4 triode Q2 conducting during more than or equal to the conducting voltage of Q2, resistance R 5 and R6 be to the VCC dividing potential drop, this moment U2=VCC*R5/ (R5+R6).When choosing suitable R 5, R6 resistance and make VCC-U2 more than or equal to the conducting voltage of metal-oxide-semiconductor Q1, first pin and the tripod conducting of metal-oxide-semiconductor Q1, electric current flows to tripod from first pin of metal-oxide-semiconductor Q1, this moment U1=VCC.
In the middle of concrete enforcement, be connected with protective tube F1 between supply power voltage input VCC and the resistance R 1, protect the delay circuit that powers on.In addition, be connected with voltage stabilizing didoe D1 and resistance R 3 between the b utmost point of triode Q2 and resistance R 1, the R4 tie point, the protection triode.In addition, be connected with capacitor C 2 between the tie point of the e utmost point of triode Q2 and resistance R 6, metal-oxide-semiconductor Q1, the two ends of resistance R 4 are connected in parallel to capacitor C 1 and carry out rectifying and wave-filtering.
The delay circuit that powers on of the present utility model adopts thermistor, triode and divider resistance, reach the conducting voltage of triode in the divider resistance voltage after partial, and the voltage of metal-oxide-semiconductor makes input voltage be transferred to output through metal-oxide-semiconductor when reaching conducting voltage, thereby utilize the hardware time-delay that realized powering on, solve the problem of existing power on delay circuit cost height, occupying system resources.
The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.
Claims (6)
1. the delay circuit that powers on comprises metal-oxide-semiconductor, and metal-oxide-semiconductor is connected with the supply power voltage input, and crus secunda is connected with output, it is characterized in that, described circuit also comprises:
Thermistor is connected with supply power voltage input and output;
Divider resistance R (2), R (4) are connected with the tie point of output with described thermistor, and the voltage of its tie point is carried out dividing potential drop;
Triode, the b utmost point is connected e utmost point ground connection with the tie point of described divider resistance R (2), R (4); And
Divider resistance R (5), R (6) are connected with the c utmost point of described triode, will carry out voltage after partial and be transferred to described metal-oxide-semiconductor.
2. the delay circuit that powers on as claimed in claim 1 is characterized in that described circuit also comprises diode, is connected with the tie point of R (4) with the b utmost point and the divider resistance R (2) of described triode.
3. the delay circuit that powers on as claimed in claim 2 is characterized in that, is connected with resistance between the tie point of described diode and divider resistance R (2) and R (4).
4. the delay circuit that powers on as claimed in claim 1 is characterized in that, is connected with protective tube between described thermistor and the supply power voltage input.
5. the delay circuit that powers on as claimed in claim 1 is characterized in that, the two ends and the electric capacity of described resistance R (4) are connected in parallel.
6. the delay circuit that powers on as claimed in claim 1 is characterized in that, the resistance R (5) that described triode and series connection with it connect is connected in parallel with electric capacity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007201204533U CN201044435Y (en) | 2007-05-31 | 2007-05-31 | Power up time delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007201204533U CN201044435Y (en) | 2007-05-31 | 2007-05-31 | Power up time delay circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201044435Y true CN201044435Y (en) | 2008-04-02 |
Family
ID=39259326
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2007201204533U Expired - Fee Related CN201044435Y (en) | 2007-05-31 | 2007-05-31 | Power up time delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201044435Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103825263A (en) * | 2012-11-16 | 2014-05-28 | 海洋王（东莞）照明科技有限公司 | Voltage-stabilization-source start protection circuit and power-strip test circuit |
| WO2018036370A1 (en) * | 2016-08-22 | 2018-03-01 | 中兴通讯股份有限公司 | Soft start circuit, and power board and service single board having same |
-
2007
- 2007-05-31 CN CNU2007201204533U patent/CN201044435Y/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103825263A (en) * | 2012-11-16 | 2014-05-28 | 海洋王（东莞）照明科技有限公司 | Voltage-stabilization-source start protection circuit and power-strip test circuit |
| WO2018036370A1 (en) * | 2016-08-22 | 2018-03-01 | 中兴通讯股份有限公司 | Soft start circuit, and power board and service single board having same |
| CN107769535A (en) * | 2016-08-22 | 2018-03-06 | 中兴通讯股份有限公司 | A kind of soft-start circuit and power panel and service board comprising the circuit |
| CN107769535B (en) * | 2016-08-22 | 2021-03-30 | 中兴通讯股份有限公司 | Slow starting circuit, power panel comprising same and service single board |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080402 Termination date: 20150531 |
|
| EXPY | Termination of patent right or utility model |