CN201042016Y - Multi-rate and multi-protocol bit stream processor - Google Patents
Multi-rate and multi-protocol bit stream processor Download PDFInfo
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- CN201042016Y CN201042016Y CNU2007200846966U CN200720084696U CN201042016Y CN 201042016 Y CN201042016 Y CN 201042016Y CN U2007200846966 U CNU2007200846966 U CN U2007200846966U CN 200720084696 U CN200720084696 U CN 200720084696U CN 201042016 Y CN201042016 Y CN 201042016Y
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Abstract
The utility model relates to a multispeed multi-protocol bit stream processor, wherein, first and second transceivers can be respectively used for carrying out bit stream synchronization, clock recovery, clock frequency multiplication for first and second protocol-bit streams. First and second package controllers can be used for processing and converting the data packages of the first and the second protocol bit streams into the corresponding second and the first protocol bit stream. a first protocol serial bit stream firstly enters into the first transceiver, then goes by the first package controller, and finally gets sent out by the first transceiver to change into a second protocol serial bit stream; and the second protocol serial bit flow firstly enters into the first transceiver, then goes by the second package controller, and finally gets sent out by the second transceiver to change into the first protocol serial bit stream. The utility model can allow two synchronous bit streams which have different speeds and transmission protocols, to be communicated with each other in high speed. The conversion and the error correction of the protocols can be finished during the process of data transmitting. Compared with the realization of software, the utility model has higher efficiency and a qualitative leap in the transmitting speed.
Description
Technical field
The utility model relates to data communication and digital integrated circuit field, is used for the multi-rate multi-protocol bit stream processor of baseband transmission specifically.
Background technology
The development of digital integrated circuit at present is very fast, also more and more is applied to the communications field.Compare with analog integrated circuit, digital integrated circuit is more suitable for large-scale circuit design, has the characteristics integrated, easy to verify that are easy to.For the baseband portion of physical layer, the mode that normally adopts digital-to-analogue to mix designs.
In the application of data communication, three kinds of situations usually appear:
The transmission rate difference of [1] two equipment can not direct communication.
[2] but identical one of two devices transfer rate are sync caps and another is an asynchronous interface, can not direct communication.
It is identical that [3] two equipment satisfies speed, and be all to be synchronous, but the agreement of transmission is different, can not direct communication.
For [1] and [2] two kinds of situations, usually adopt FIFO to connect two equipment.
And, need finish packing, error correction and unpack for [3] kind situation.These processing can be finished by the software of single-chip microcomputer, but efficient is very low.Publishing (U.S.) BehrouzA.Forouzan work Wu Shi Lin etc. by China Machine Press, to translate " data communication and network " (the 2nd edition) be the external classical teaching material of a notebook data communications field, and it points out that " bridge that connects two kinds of LAN should be able to processed frame form difference, payload difference, data rate difference, address bit preface difference and affirmation, conflict, priority may be the part of certain agreement and problem that another agreement does not have." bridge carries out as can be seen is " transparent transmission ", promptly can not carry out error correction.If mistake has taken place in frame in transmission course, general adopt retransmit or discarded packets.Preceding a kind of mode meeting busy channel, the waste resource; A kind of mode in back can drop-out.Bridge is commonly used to connect several fixing agreements, and can not support various protocols.Bridge can not be handled the bag of a certain length-specific.
Summary of the invention
The purpose of this utility model is for a kind of multi-rate multi-protocol bit stream processor is provided, and this processor can make two transmission rate differences, bit stream asynchronous and that host-host protocol is different carry out high-speed communication.
The multi-rate multi-protocol bit stream processor that the utility model provides, it comprises first transceiver, second transceiver, first packet controller and second packet controller; Wherein,
First and second transceiver is used for respectively first, second protocol bits stream being carried out bit synchronous, clock recovery, clock multiplier, and first and second packet controller is used for the packet of first, second protocol bits stream is handled and converted to the bit stream of second, the first corresponding agreement;
The first agreement serial bit stream at first enters into first transceiver, through being sent out by first transceiver again behind first packet controller, becomes the serial bit stream of second agreement again;
The second agreement serial bit stream then at first enters into first transceiver, through being sent out by second transceiver again behind second packet controller, becomes the serial bit stream of first agreement.
The two-forty that the utility model is supported bit stream between the communication of many speed and the different agreement synchronously or the processing of asynchronous transmission.So-called many speed are meant when the transmission rate of two equipment is different and can communicate by the utility model.So-called multi-protocols are meant that the host-host protocol of two equipment is different, as token ring, FDDI, ether, HDLC, can finish symbol synchronization, clock recovery, frame synchronization, error control and unpack packing communicating by the utility model.So-called bit stream is handled and is meant that in the process of transfer of data the utility model can be handled and control bit stream according to the setting of host computer procedure.Superiority of the present utility model just is, can make two transmission rate differences, bit stream asynchronous and that host-host protocol is different carry out high-speed communication.In the process of transfer of data, finish conversion, the error correction of agreement simultaneously, go for the transfer of data between the different procotols.Realize comparing with software, efficient of the present utility model is higher, and transmission speed has qualitative leap.
Description of drawings
Fig. 1 is the structural representation of the utility model multi-rate multi-protocol bit stream processor;
Fig. 2 is the structural representation of packet controller;
Fig. 3 is the structural representation of transceiver;
Fig. 4 is the structural representation of error control device;
Fig. 5 is the structural representation of group packet controller;
Fig. 6 is the state diagram of the utility model master controller;
Fig. 7 is a multi-rate multi-protocol bit stream processor application examples structure chart described in the utility model.
Embodiment
Below in conjunction with accompanying drawing and example the utility model is described in further detail.
As shown in Figure 1, the bit stream that wherein meets different agreement represents that with A and B the utility model processor comprises first transceiver 1, second transceiver 2, first packet controller 3 and second packet controller 4.Wherein, first transceiver 1 is used for A protocol bits stream is carried out bit synchronous, clock recovery, clock multiplier, second transceiver 2 is used for B protocol bits stream is carried out bit synchronous, clock recovery, clock multiplier, first packet controller 3 is used for the packet that meets A protocol bits stream is handled and converted to the bit stream of B agreement, and second packet controller 4 is used for the packet that meets B protocol bits stream is handled and converted to the bit stream of A agreement.A agreement serial bit stream at first enters into first transceiver 1 and is sent out by first transceiver 1 again after through first packet controller 3, becomes the serial bit stream of B agreement.B agreement serial bit stream then at first enters into first transceiver 2, through being sent out by second transceiver 2 again behind second packet controller 4, becomes the serial bit stream of A agreement.First transceiver 1 and 3 collaborative works of first packet controller; Second transceiver 2 and 4 collaborative works of second packet controller.
The structure of first packet controller 3 and second packet controller 4 is identical with operation principle, and it constitutes as shown in Figure 2.
First packet controller 3 and second packet controller 4 include input-buffer 10, error control device 5, variable connector 6, group packet controller 7, output buffers 8,9,8 bus interface 11 of master controller.Be that example is described in further detail each several part with first packet controller 3 below.
Input-buffer 10: input-buffer 10 is that a degree of depth is 1K, and width is 8 FIFO.The parallel data of A agreement enters input-buffer 10, deposits the data of 1 frame at least in.After the data that deposit 1 frame in, by the data that address pointer is read the LLC layer of reading of master controller 9 control input-buffers 10, i.e. control unpacks.After being finished by output buffers 8 transmissions, data begin to handle second frame data, and the like.
Owing to always make a mistake in transmission, so error control device 5 is used for judgment frame whether mistake has taken place.If mistake has taken place, error control device 5 judges it is where mistake has taken place.Can correct by error control device 5 so long as not the mistake that LLC itself takes place.Error control device 5 can be handled the fixed length bag.
Variable connector 6 is used for selectively being communicated with 10,8 bus interface 11 of input-buffer, output buffers 8.When input 01 time, 8 bus interface 11 and master controller 9 are communicated with; When importing 10, input-buffer 10 and output buffers 8 are communicated with; When input 11 time, input-buffer 10 and output buffers 8 are communicated with and 8 bus interface 11 and master controller 9 are communicated with; When input 00 time, input-buffer 10 and output buffers 8 are not communicated with and 8 bus interface 11 and master controller 9 are not communicated with.
Output buffers 8 is that a degree of depth is 1K, and width is 8 FIFO.The LLC data add that the packet header sign, type, the check bit sum tail tag will that meet the B agreement send to first transceiver 1 from output buffers 8.
8 bus interface 11 are used for being communicated with host computer, by host computer procedure master controller 9 are controlled.
Error control device 5 among Fig. 2 can adopt structure as shown in Figure 4 to be achieved.As shown in Figure 4, error control device 5 comprises packet header comparator 20, input packet header register 21, bag type comparator 22, input bag type register 23, bag data length comparator 24, input bag data length register 25, address comparator 26, input address register 27, CRC (cyclic redundancy) checker 28, check register 29, bag tail comparator 30, input bag tail register 31.Packet header comparator 20 is used for detecting packet header byte.Input packet header register 21 has 4 bytes, storage be the packet header byte of A protocol bits stream.Set input packet header register 21 by host computer procedure.Bag type comparator 22 is used for detecting type byte, access control byte or the frame control byte of packet.Input bag type register 23 has 4 bytes, and storage is type byte, access control byte or the frame control byte of packet accordingly.Set input bag type register 23 by host computer procedure.Bag data length comparator 24 is used for the LLC data length byte of comparing data bag.If A protocol bits stream has the data length byte, so just can obtain the bag of length-specific by bag data length comparator 24.Input bag data length register 25 has 4 bytes, storage be LLC data length byte.Set input bag data length register 25 by host computer procedure.Address comparator 26 is used for testing goal address and source address.Input address register 27 has 14 bytes, is used for storage purpose address and source address.Set input address register 27 by host computer procedure.CRC check device 28 is 8 that walk abreast, and promptly once can handle the 8bit data.The generator polynomial of CRC has three kinds in the CRC check device 28, CRC-16 (adopting in U.S.'s binary system synchro system), CRC-CCITT (CCITT by Europe recommends), CRC-32 (802.3,802.4,802.5, FDDI etc.).Check register 29 has a byte.Decide by the value of setting check register 29 by host computer procedure and to select any generator polynomial for use.Destination address in 28 pairs of frames of CRC check device, source address, length, LLC data etc. are carried out CRC check, and the check digit of generation enters into output buffers 8 under the control of master controller 9.Result for CRC-16 and CRC-CCITT verification has 16, has 32 for the result of CRC-32 verification.In output time,, high byte is preceding, low byte after, and line output.Bag tail comparator 30 is used for detecting the end of packet.Input bag tail register 31 has 1 byte, is used to store tail tag will; Set input bag tail register 31 by host computer procedure.
When the packet header comparator 20 among Fig. 4 detects the packet header of A protocol bits stream, send the master controller 9 of a confirmation signal to Fig. 2.Fig. 2 master controller 9 control charts 4 bag type comparators 22 are started working.Behind the affirmation signal of receiving Fig. 4 bag type comparator 22, the bag data length comparator 24 of master controller 9 control charts 4 of Fig. 2 is started working.Behind the affirmation signal of the bag data length comparator 24 of receiving Fig. 4, the address comparator 26 of master controller 9 control charts 4 of Fig. 2 is started working.Behind the affirmation signal of the address comparator 26 of receiving Fig. 4, the bag tail comparator 30 of master controller 9 control charts 4 of Fig. 2 is started working.The CRC check device 28 of Fig. 4 also moves and finishes when data have entered the input-buffer 10 of Fig. 2.CRC check is correct, then unpacks; It is the LLC error in data that bag type comparator 22 among CRC check mistake and Fig. 4, bag data length comparator 24, address comparator 26 detect correctly then explanation, how to be handled by the host computer procedure decision; The CRC check mistake, bag type comparator 22 or bag data length comparator 24 or address comparator 26 detect mistake and then can locate mistake, promptly the data of transmission are carried out error correction.
The CRC generator polynomial of the CRC encoder 32 among Fig. 5 has three kinds, CRC-16, CRC-CCITT, CRC-32.CRC encoder 32 is 8 that walk abreast, and promptly once can handle the 8bit data.Decide any generator polynomial of employing by host computer procedure.Destination address in 32 pairs of Frames of CRC encoder, source address, length, LLC data etc. are carried out the CRC coding.
Storage is the packet header that meets the B agreement in the register 33 of output packet header.Storage is the type byte of B agreement in the output packet type register 34.Storage is the LLC data length byte that meets the B agreement in the output packet length register 35.Storage is destination address and the source address that meets the B agreement in the output packet address register 36.Storage is the tail tag will that meets the B agreement in the output packet tail register 37.Content in these memories preestablishes by the program of host computer.The bit stream of B agreement enters into the CRC encoder by variable connector 6 and enters output buffers 8 simultaneously.After coding, meet under the control of master controller 9 that the LLC data send in order in packet header byte, bag type byte, packet length byte, packet address byte, CRC check sign indicating number, bag trail byte and the output buffers 8 of A agreement.
First transceiver 1 is identical with the structure of second transceiver 2, as shown in Figure 3, they include serial received d type flip flop 12, clock recovery circuitry 15, deserializer 13, parallel receive d type flip flop 14, clock multiplier circuit 19, serial emission d type flip flop 16, parallel-to-serial converter 17, parallel emission d type flip flop 18.Here only narrate the structure of first transceiver 1.
Serial received d type flip flop 12 receives the bit stream that meets the A agreement, recovers clock by clock recovery circuitry 15 then.Enter deserializer 13 behind the data process serial received d type flip flop device 17.
Deserializer 13 receives the serial bit stream that has recovered clock, and converts it the output of to 8 parallel-by-bits.The clock of deserializer 13 derives from the later recovered clock of 8 frequency divisions.
Parallel receive d type flip flop 14 will be through the data output after string and the conversion.
Parallel emission d type flip flop 18 receives parallel bit stream and it is transferred to parallel-to-serial converter 17.
Parallel-to-serial converter 17 receives 8 parallel-by-bit data from parallel emission d type flip flop 18.These data send to serial emission d type flip flop 16 with the frequency of 8 times of REFCLK.
24 couples of REFCLK of clock multiplier carry out 8 frequencys multiplication.And with the clock control parallel-to-serial converter 17 after the frequency multiplication, parallel emission d type flip flop 18 and serial emission d type flip flop 16.
Serial emission d type flip flop 16 receives from the serial data stream of parallel-to-serial converter 17 and sends.
The reception and the process of transmitting of first transceiver, 1 data are described respectively below.
The receiving course of data: serial bit stream enters after the serial received d type flip flop 12, carries out clock recovery by clock recovery circuitry 15 earlier.Recover the clock control deserializer 13 of coming out, and have the output of one 8 frequency division to receive parallel receive d type flip flop 14.Bit stream enters deserializer 13 after recovering clock, becomes the output of 8 parallel-by-bit data by the serial input.
The process of transmitting of data: 8 parallel-by-bit data enter after the parallel emission d type flip flop 18, by clock multiplier circuit input clock are carried out 8 frequencys multiplication.Clock control that frequency multiplication is come out and string conversion 17.Temporarily do not having under the situation of data inputs, device can be with the frequency stabilization of reference frequency (REFCLK) when guaranteeing free of data of PLL locking.8 parallel-by-bit data are carried out and are gone here and there after the conversion, become serial bit stream output.
Disposed of in its entirety flow process of the present utility model is as follows: after the A bit stream among Fig. 3 enters into serial received d type flip flop 12, at first carry out clock recovery by clock recovery circuitry 15.Recovering clock enters deserializer 13 later on and goes here and there and change.Parallel data enters first packet controller 3 among Fig. 1 via parallel receive d type flip flop 14 then.In first packet controller 3 among Fig. 1, bit stream enters error control device 5 in the input-buffer 10 that enters Fig. 2.By master controller 9 control error verifications, error correction, unpack.Wrap while entering output buffers 8 group under the control of group packet controller 7 at bit stream under the control of master controller 9 and variable connector 6 then.In output buffers 8, bit stream is added packet header, frame type, address byte, length byte, check bit sum tail tag will again again, becomes the bit stream of B agreement.Data enter into first transceiver 1 of Fig. 3 again then.In Fig. 3, bit stream enters the bit stream that parallel-to-serial converter 17 is converted to serial via parallel emission d type flip flop 18.At last, bit stream adopts the clock serial after the REFCLK frequency multiplication is sent.
As shown in Figure 7, the example of this utility model processor application is:
The transmission rate of ether interface 40 be 10Mb/s and X.25 the transmission rate of interface 41 are 48Kb/s.Ether interface 40 is different with the speed of 41 transmission of interface X.25, and is asynchronous and agreement transmission is different.
Multi-rate multi-protocol bit stream processor 39 links to each other with single-chip microcomputer 38 by 8 buses, connects ether interface 40 and interface 41 X.25 more respectively.Ether interface 40 send the ether bit streams enter multi-rate multi-protocol bit stream processor 39 through unpacking, error correction, packing send to X.25 interface 41; X.25 the X.25 bit stream that sends of interface 41 enter multi-rate multi-protocol bit stream processor 39 equally through unpack, error correction, packing send to ether interface 40.
Host computer procedure is provided with the value of register in the group packet controller 7 of the error control device 5 of Fig. 4 and Fig. 5, and sets the sequencing of carrying out.The input packet header register 21 of Fig. 4 is arranged to the packet header (promptly the frame of the leading character of 7 bytes and 1 byte begins byte) of ether, input bag type register 23 is set to 00H (promptly not containing the type byte), input bag data length register 25 is set to FFH (promptly handling the bag that the LLC data length is 256 bytes), address register 6 is set to the destination address of 6 bytes and the source address of 6 bytes, check register 29 is set to 01H (promptly selecting CRC-32), A bag tail register is set to 00H (being that ether does not contain the bag trail byte).The output packet header register 33 of Fig. 5 is arranged to 7EH (leader will byte X.25), CRC encoder 32 to be set to CRC-CCITT, output packet type register 34 and to be set to 7AH (i.e. control byte X.25), output packet length register 35 and to be set to that 00H (promptly not containing the data length byte), output packet address register 36 are set to 03H (i.e. address byte X.25), output packet tail register 37 is set to 7EH (tail tag will byte X.25).Ether interface 40 and X.25 interface 41 just can communicate.
In the process of transmission, single-chip microcomputer 38 does not participate in substantially.Because the conversion of agreement is realized by hardware fully, still can not obtain very high transmission speed even therefore the cpu performance of single-chip microcomputer is high.Optimize embodiment though this explanation is of choosing, the professional and technical personnel should understand, and the utility model is not limited to above-mentioned example, but is fit to the situation of many speed, multi-protocols.
Claims (5)
1. multi-rate multi-protocol bit stream processor, it is characterized in that: it comprises first transceiver (1), second transceiver (2), first packet controller (3) and second packet controller (4); Wherein,
First and second transceiver (1,2) is used for respectively first, second protocol bits stream being carried out bit synchronous, clock recovery, clock multiplier, and first and second packet controller (3,4) is used for the packet of first, second protocol bits stream is handled and converted to the bit stream of second, the first corresponding agreement;
The first agreement serial bit stream at first enters into first transceiver (1), through being sent out by first transceiver (1) again behind first packet controller (3), becomes the serial bit stream of second agreement again;
The second agreement serial bit stream then at first enters into first transceiver (2), through being sent out by second transceiver (2) again behind second packet controller (4), becomes the serial bit stream of first agreement.
2. processor according to claim 1, it is characterized in that: first packet controller (3) is identical with the structure of second packet controller (4), includes input-buffer (10), error control device (5), variable connector (6), group packet controller (7), output buffers (8), master controller (9), 8 bus interface (11); Wherein,
Variable connector (6) is used for selectively being communicated with input-buffer (10), 8 bus interface (11) and output buffers (8);
Input-buffer (10) is used to receive the data from transceiver, and unpacks under the control of master controller (9);
Whether error control device (5) is used for judgment frame and makes a mistake; Further judge it is that frame type, LLC data length byte, source address or destination address make a mistake and corrected if make a mistake;
Group packet controller (7) adds packet header, frame type, LLC data length byte, source address, destination address, check digit, bag tail tag will under the control of master controller (9) the LLC data;
Output buffers (8) is used under the control of master controller (9) the LLC data being added that packet header sign, type, the check bit sum tail tag will of protocol compliant send to transceiver from output buffers (8) in order;
8 bus interface (11) are used for being communicated with host computer, by host computer procedure master controller (9) are controlled;
Master controller (9) comprises 4 states, moves, resets, hovers and restart; When being in running status, master controller (9) control error controller (5) carries out the error control verification; Control the data that address pointer is read the LLC layer of reading of input-buffer (10); Control input-buffer (10), 8 bus interface (11), organize the connection between packet controller (7) and the output buffers (8) by control variable connector (6); Come the group bag of control data by control group packet controller (7); Order of transmission by control output buffers (8) control data.
3. processor according to claim 2 is characterized in that: described error control device (5) comprising:
Be used to detect the packet header comparator (20) of packet header byte,
Be used to store the input packet header register (21) of the packet header byte of A protocol bits stream,
Be used for detecting the bag type comparator (22) of type byte, access control byte or the frame control byte of packet,
Be used to store the input bag type register (23) of type byte, access control byte or the frame control byte of packet,
The bag data length comparator (24) that is used for the LLC data length byte of comparing data bag,
Be used to store the input bag data length register (25) of LLC data length byte,
The address comparator (26) that is used for testing goal address and source address,
The input address register (27) that is used for storage purpose address and source address,
Be used for destination address, source address, length, LLC data and carry out the cyclic redundancy checker (28) of cyclic redundancy check (CRC) frame,
Be used to store the check register (29) of check value,
Be used to detect the bag tail comparator (30) of the end of packet,
With the input bag tail register (31) that is used to store tail tag will;
When packet header comparator (20) detects the packet header of protocol bits stream, send a confirmation signal to master controller (9); Master controller (9) controlling packet type comparator (22) is started working; Behind the affirmation signal of receiving bag type comparator (22), master controller (9) controlling packet data length comparator (24) is started working; Behind the affirmation signal of receiving bag data length comparator (24), master controller (9) control address comparator (26) is started working; Behind the affirmation signal of receiving address comparator (26), master controller (9) controlling packet tail comparator (30) is started working; Cyclic redundancy checker (28) is also moved and is finished when data have entered input-buffer (10); Cyclic redundancy check (CRC) is correct, then unpacks; It is the LLC error in data that cyclic redundancy check error and bag type comparator (22), bag data length comparator (24), address comparator (26) detect correctly then explanation, how to determine cycle of treatment redundancy check mistake by host computer procedure, bag type comparator (22) or bag data length comparator (24) or address comparator (26) detect mistake then can locate mistake, promptly the data that send is carried out error correction.
4. processor according to claim 3 is characterized in that: described group of packet controller (7) comprises
Be used for destination address, source address, length, LLC data and carry out the cyclic redundancy code device (32) of cyclic redundancy code frame,
Be used to store the output packet header register (33) in the packet header of protocol compliant,
The output packet type register (34) that is used for the type byte of storage protocol,
Be used to store the output packet length register (35) of the LLC data length byte of protocol compliant,
Be used to store the destination address of protocol compliant and the output packet address register (36) of source address,
Be used to store the output packet tail register (37) of the tail tag will of protocol compliant,
Bit stream enters into cyclic redundancy code device (32) by variable connector (6) and enters output buffers (8) simultaneously, after coding, the LLC data send in order in packet header byte, bag type byte, packet length byte, packet address byte, cyclic redundancy check (CRC) code, bag trail byte and the output buffers (8) of the control protocol compliant of master controller (9).
5. according to arbitrary described processor in the claim 1 to 4, it is characterized in that: described first transceiver (1) is identical with the structure of second transceiver (2), includes serial received d type flip flop (12), clock recovery circuitry (15), deserializer (13), parallel receive d type flip flop (14), clock multiplier circuit (19), serial emission d type flip flop (16), parallel-to-serial converter (17) and parallel emission d type flip flop (18); Wherein,
Serial received d type flip flop (12) receives the bit stream that meets first or second agreement, recovers clock by clock recovery circuitry (15) then and enters deserializer (18);
Deserializer (18) receives the serial bit stream that has recovered clock, and converts it the output of to 8 parallel-by-bits;
Parallel receive d type flip flop (19) parallel receive d type flip flop (14) will be through the data output after string and the conversion;
The high-speed bit stream that clock recovery circuitry (15) receives from parallel receive d type flip flop (19) extracts clock, and the output RCLK of one 8 frequency division is provided;
Parallel emission d type flip flop (18) is used for the parallel data of receiving end/sending end and it is transferred to parallel-to-serial converter (17);
Parallel-to-serial converter (17) receives 8 parallel-by-bit data from parallel emission d type flip flop (23), goes here and there and changes, and send to serial emission d type flip flop (21) with the frequency of 8 times of REFCLK;
Clock multiplier circuit (19) carries out 8 frequencys multiplication to REFCLK, and launches d type flip flop (16) with the clock control parallel-to-serial converter (17) after the frequency multiplication, parallel emission d type flip flop (18) and serial;
The serial data stream that serial emission d type flip flop (16) receives from parallel-to-serial converter (17) sends to first packet controller (3).
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