CN201041037Y

CN201041037Y - Petroleum exploration logging instrument data gathering device

Info

Publication number: CN201041037Y
Application number: CNU2007201489720U
Authority: CN
Inventors: 孙钦涛; 陈宝
Original assignee: China National Petroleum Corp; China Petroleum Logging Co Ltd
Current assignee: China National Petroleum Corp; China Petroleum Logging Co Ltd
Priority date: 2007-04-28
Filing date: 2007-04-28
Publication date: 2008-03-26
Anticipated expiration: 2017-04-28

Abstract

The utility model relates to a data collector of a petroleum exploration logger, the input of a multi-way analogy switch is connected with the output of the logger, the output of the multi-way analogy switch is connected with the output of a programmable gain amplifier; the output of the programmable gain amplifier is connected with the input of an A/D converter; the data bus of the A/D converter is connected with a CPLD data bus; the data bus, the address bus, the reading and writing control signal line of a DSP controller are connected with the data bus, the address bus, the reading and writing control signal line of the CPLD; the selector bus of a CPLD analog channel is connected with the selector bus of the analog channel of the multi-way analogy switch; the CPLD control signal line is connected with the control signal line of the A/D converter; the CPLD gain control signal line is connected with the gain control signal line of the programmable gain amplifier; the CPLD control signal line is connected with the input of a level driver, the output of the level driver is connected with the control input end of a relay; the data collector can accurately collect the millivolt grade signals, meet the need of the data collection of the instrument under well, the circuit is steady and reliable.

Description

A kind of oil exploration logging instrument data acquisition unit

Technical field

The utility model relates to a kind of oil exploration logging instrument data acquisition unit.

Technical background

Oil exploration logging instrument data acquisition unit comprises Acquisition Circuit, communication interface.The log data acquisition device is the intermediate link of contact downhole instrument and the spread of the rumours, is connected with the spread of the rumours by downhole toolbus, is responsible for the downhole instrument data acquisition and processing (DAP), control command that reception ground issues and the data of uploading collection and handling.The downhole instrument kind is more, but has a lot of general character, as collection of simulant signal, relay control etc.She Ji collector adopted some discrete devices to realize logic function in the past, caused the circuit complexity, and cost is too high.

The utility model content

The purpose of this utility model provides a kind of employing CPLD chip and realizes the separation logic device function, satisfy the logger high-accuracy data acquisition, downhole instrument reduces component number to the processing of complex data, increases the oil exploration logging instrument data acquisition of the reliability of instrument.

The utility model adopts following technical scheme:

A kind of logger data acquisition unit comprises: multiway analog switch 1, programmable gain amplifier 2, A/D converter 3, dsp controller 4, CPLD chip 5 and level drive chip 6;

Circuit structure is as follows: the input signal IN1 of multiway analog switch 1～IN8 connects the output of logger front-end processing circuit; Multiway analog switch 1 output pin 12 connects the input pin 3 of programmable gain amplifier 2; The output pin 8,9 of programmable gain amplifier 2 connects the input pin 13 of A/D converter 3; The data/address bus AD0 of A/D converter 3～AD11 connects the data/address bus AD0～AD11 of CPLD chip 5; Data/address bus D0～the D15 of dsp controller 4, address bus A0～A4, read-write control signal line IS, RD, WE connect the data/address bus D0～D15 of CPLD chip 5, address bus A0～A4, read-write control signal line IS, RD, WE; Bus SA0～SA2 is selected in the simulation road that the simulation road of CPLD chip 5 selects bus SA0～SA2 to connect multiway analog switch 1; Control signal wire STS, the R/C of CPLD chip 5 connects control signal wire STS, the R/C of A/D converter 3; The gain control signal line GAIN of CPLD chip 5 connects the gain control signal line GAIN of programmable gain amplifier 2; Control signal wire ST0, the ST1 of CPLD chip 5 connects 1,3 input pins that level drives chip 6; 2,4 output pin Relay0, Relay1 that level drives chip 6 connect the relay control input end.

The course of work of logger data acquisition circuit is:

1, data acquisition state control lock storage is used to latch the control signal from DSP, select control signal as multiway analog switch simulation road, programmable gain amplifier gain control signal, AD converter are read/conversion starting signal, and the relay status control signal etc.The multi-analog signal is connected to the signal input part of multiway analog switch 1, by multiway analog switch 1 gating one tunnel input that exports programmable gain amplifier 2 to wherein, exports the 10V range input of A/D converter 3 after the gain transformations to.Dsp controller 4 carries out signals collecting control by CPLD chip 5.

2, every road analog signal through AD conversion back dsp controller 4 will according to the first time result value determine whether carrying out second time AD and change.As the first time result at-312mV～312mV, DSP can be adjusted into 16 times to gain, carries out the AD conversion second time, otherwise with conversion for the first time as final entry.

The beneficial effects of the utility model: the logger data acquisition unit is installed on the downhole electronics skeleton, is connected with the spread of the rumours by communication interface.Can accurately collect the signal of millivolt level in the well logging construction, satisfy the needs of downhole instrument data acquisition process, circuit is reliable and stable.And reduced the Acquisition Circuit component number, improved the log data acquisition level.

Description of drawings

Fig. 1 is the utility model logger data acquisition circuit schematic diagram.

Among the figure, 1. multiway analog switch, 2. programmable gain amplifier, the 3.A/D converter, the 4.DSP controller, the 5.CPLD chip, 6. level drives chip.

The specific embodiment

Be described in detail below in conjunction with 1 pair of the utility model of accompanying drawing.

Multiway analog switch 1 adopts 8 the tunnel to select 1 high-speed analog switch AD7501SQ, and input signal IN1～IN8 is from the output of logger front-end processing circuit, and output pin 12 connects the input pin 3 of programmable gain amplifier 2; Programmable gain amplifier 2 adopts AD526SD, characteristics such as have that gain error is low, non-linear distortion is little, DC precision is high and input offset voltage is low, and the output pin 8,9 of programmable gain amplifier 2 connects the input pin 13 of A/D converters 3; A/D converter 3 is selected AD1674TD for use, be complete a, multipurpose, 12 analog-digital converter, voltage reference, clock and tristate output buffer with sampling/hold amplifier (SHA), 10V in the sheet, sampling rate is 10 μ s, having higher switching rate and conversion accuracy, the modelled signal input range is-5V～+ 5V; The data/address bus AD0 of A/D converter 3～AD11 connects the data/address bus AD0～AD11 of CPLD chip 5; CPLD chip 5 is selected EPM7128AETI for use ,+3.3V power supply, and compatibility+5V input is used for realizing that data latch and function such as logic decoding; Dsp controller 4 has adopted TMS320LF2407APGES; Data/address bus D0～the D15 of dsp controller 4, address bus A0～A4, read-write control signal line IS, RD, WE connect the data/address bus D0～D15 of CPLD chip 5, address bus A0～A4, read-write control signal line IS, RD, WE; Bus SA0～SA2 is selected in the simulation road that the simulation road of CPLD chip 5 selects bus SA0～SA2 to connect multiway analog switch 1; Control signal wire STS, the R/C of CPLD chip 5 connects control signal wire STS, the R/C of A/D converter 3; The gain control signal line GAIN of CPLD chip 5 connects the gain control signal line GAIN of programmable gain amplifier 2; Control signal wire ST0, the ST1 of CPLD chip 5 connects 1,3 input pins that level drives chip 6; Level drives chip 6 and adopts 54HC04, and 2,4 output pin Relay0, Relay1 that level drives chip 6 connect the relay control input end.

Be connected to the signal input part of multiway analog switch 1 through conditioning, filtered 8 road analog signalses, select wherein one tunnel input that exports programmable gain amplifier 2 to by multiway analog switch 1, export the 10V range input of A/D converter 3 after the gain transformations to.Dsp controller 4 carries out signals collecting control by CPLD chip 5.

For reducing the size of circuit board, reduce the components and parts usage quantity, improve instrument reliability, the utility model adopts CPLD to realize the function of some separation logic devices.5 internal structures of CPLD chip Multiplexer Channel select latch, gain control lockmaking storage, AD to read/change startup latch, relay status control lock storage, AD transformation result latch.Every kind of latch all distributes an address, and dsp controller 4 writes in the CPLD latch by address data bus with the state of a control variable can realize the AD data acquisition, relay status control etc.

Dsp controller 4 writes control command to each control lock storage of CPLD chip 5, the channel selecting of control multiway analog switch 1, the gain of programmable gain amplifier 2, the reading/conversion starting signal of A/D converter 3, and relay status control signal.The state of relay status control signal control relay after driving chip 6 drivings.Behind A/D converter 3 EOCs result is latched in and waits in the AD transformation result latch of CPLD chip 5 that dsp controller 4 reads.

Send into multiway analog switch behind the good analog signal LPF of downhole instrument front-end processing, during data acquisition, at first carry out channel selecting, dsp controller 4 is carried out write operation, channel address to be selected is write Multiplexer Channel select latch, with the channel address signal of control SA0～SA2 as multiway analog switch 1.Then write 0, so that the gain of programmable gain amplifier 2 is 1 to gain control lockmaking storage.The R/C of A/D converter 3 is a high level before the AD conversion, STS is a low level, dsp controller 4 sends and starts the A/D conversion command with R/C step-down startup conversion, this moment, STS was during high level represents that conversion is carried out, EOC behind the 10 μ s, the negative jump pulse of STS generation latchs AD result to be latched in waits in the CPLD chip 5 that dsp controllers 4 read, to solve A/D converter output level+5V and the unmatched problem of DSP incoming level+3.3V.

Every road analog signal will judge that through AD conversion back dsp controller 4 result's value determines whether carrying out the AD conversion second time according to the first time to the result.When the first time AD transformation result at-312mV～312mV, dsp controller 4 can be adjusted into 16 to gain, carry out the AD conversion second time, if the result is not in this scope for the first time, just with the first time result as final outcome record, can make full use of the range of AD converter like this, guarantee the conversion accuracy of small-signal.

Claims

1. oil exploration logging instrument data acquisition unit, it comprises that multiway analog switch (1), programmable gain amplifier (2), A/D converter (3), dsp controller (4), CPLD chip (5) and level drive chip (6), is characterized in that: input signal IN1, the IN2 of multiway analog switch (1), IN3, IN4, IN5, IN6, IN7, IN8 connect the output of logger front-end processing circuit; Multiway analog switch (1) output pin 12 connects the input pin 3 of programmable gain amplifier (2); The output pin 8,9 of programmable gain amplifier (2) connects the input pin 13 of A/D converter (3); Data/address bus AD0, the AD1 of A/D converter (3), AD2, AD3, AD4, AD5, AD6, AD7, AD8, AD9, AD10, AD11 connect data/address bus AD0, AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8, AD9, AD10, the AD11 of CPLD chip (5); Data/address bus D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, the D15 of dsp controller (4), address bus A0, A1, A2, A3, A4, read-write control signal line IS, RD, WE connect data/address bus D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, the D15 of CPLD chip (5), address bus A0, A1, A2, A3, A4, read-write control signal line IS, RD, WE; Bus SA0, SA1, SA2 are selected in the simulation road that the simulation road of CPLD chip (5) selects bus SA0, SA1, SA2 to connect multiway analog switch (1); Control signal wire STS, the R/C of CPLD chip (5) connects control signal wire STS, the R/C of A/D converter (3); The gain control signal line GAIN of CPLD chip (5) connects the gain control signal line GAIN of programmable gain amplifier (2); Control signal wire ST0, the ST1 of CPLD chip (5) connects 1,3 input pins that level drives chip (6); 2,4 output pin Relay0, Relay1 that level drives chip (6) connect the relay control input end.