CN201011563Y - Disk array assistant processing controlling card - Google Patents
Disk array assistant processing controlling card Download PDFInfo
- Publication number
- CN201011563Y CN201011563Y CNU2006201633515U CN200620163351U CN201011563Y CN 201011563 Y CN201011563 Y CN 201011563Y CN U2006201633515 U CNU2006201633515 U CN U2006201633515U CN 200620163351 U CN200620163351 U CN 200620163351U CN 201011563 Y CN201011563 Y CN 201011563Y
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- interface
- disk array
- xor
- nvram
- flash memory
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Abstract
The utility model relates to a disk array coprocessor control card, belonging to the computer memory technology field, aiming to expedite the executing speed of the XOR operation, reinforce the data security and increases the storage access speed, used for starting the disk array system. The utility model comprises a PCI interface, an XOR processing engine, an encrypting logic block, a Flash Memory interface, an NVRAM interface, a Flash Memory clip and an NVRAM clip, the utility model has a PCI interface which is realized through adopting the FPGA, having a strong flexibility, and the XOR processing engine, the encrypting logic block and the onboard NVRAM are capable of increasing the input and output processing capacity, the data security and shortening the input and output response time, effectively improving the storage access speed, and solving the safety problem of the storage, etc, The utility model guarantees the authenticity and stability of the control system of the disk array and is capable of starting the storage system of the disk array and reinforcing the performance.
Description
Technical field
The utility model belongs to computer memory technical field, is specifically related to a kind of assistant processing control card of disk array, is used for by PCI device start disc array system, improves system performance.
Background technology
The integrated form disk array that adopts general-purpose computer components to constitute, its traditional starting outfit comprises floppy disk, hard disk and DOM, USB device etc.Consider the requirement of reliability, stability, cost and the data security of array system, be not suitable for adopting floppy disk, hard disk or other conventional starting outfit.On the other hand, these equipment do not possess yet provides the function that strengthens performance of disk arrays.
The disk array control card of using is connected on the main frame by pci interface at present, and a plurality of hard-disk interfaces are provided, at main frame internal build disk array.This disk array control card needs the support of host operating system, and itself can not be as starting outfit.This disk array assists transaction card to adopt dedicated IC chip to realize that hardware capability can not be changed.Other association transaction card only possesses simple function, as the association's transaction card that carries out data encryption specially and association's transaction card of carrying out the XOR computing specially.Some realizes that with dedicated IC chip some is realized with FPGA this class association transaction card.
Summary of the invention
The utility model proposes a kind of assistant processing control card of disk array, purpose is to accelerate execution speed, the enhancing data security of XOR computing, improves memory access speed, is used to start disc array system.
A kind of assistant processing control card of disk array of the present utility model, comprise pci interface, XOR processing engine, encryption logic unit, Flash Memory interface, NVRAM interface, and FlashMemory chip and NVRAM chip, wherein Flash Memory chip is connected with Flash Memory interface, NVRAM interface electric signals respectively with the NVRAM chip, and XOR processing engine, encryption logic unit, Flash Memory interface and NVRAM interface are connected with pci interface by PCI rear end equipment signal; Pci interface is finished order and the data interaction between main frame and this assistant processing control card of disk array; The XOR processing engine is finished XOR; The encryption logic unit performs encryption processing; Flash Memory interface and NVRAM interface are responsible for control Flash Memory chip and NVRAM chip respectively; Flash Memory chip is deposited the disk array control program simultaneously as the expansion ROM of pci card; The NVRAM chip is as the high-speed cache of disk array.
Described assistant processing control card of disk array is characterized in that: described Flash Memory chip is deposited the firmware of following the BBS agreement as expansion ROM; For the operating system pSOS+ that the disk array Control Software adopts, VxWorks or Linux, this firmware are respectively the corresponding version of following the BBS agreement.
Described assistant processing control card of disk array, it is further characterized in that: adopt FPGA to realize described pci interface, XOR processing engine, encryption logic unit, Flash Memory interface and NVRAM interface; Described Flash Memory chip and NVRAM chip are that plate carries storer.
Described assistant processing control card of disk array, described XOR processing engine can comprise XOR arithmetic element, dual-port data RAM, dual-port address RAM, local Master module, dma module and local Target module; The XOR arithmetic element is responsible for the XOR of data; The dual-port data RAM is used to preserve the intermediate result and the net result of XOR; Dual-port address RAM is used to preserve the internal memory first address of pending data block and the internal memory first address of the result returned; Local Master module is responsible for by pci interface visit host memory; Dma module is responsible for controlling local Master module, and provides access interface to upper layer software (applications); Local T arget module be responsible for will be by pci interface transmission pending data block first address and result of calculation deposit first address and deposit in the two-port RAM 260.
Pci interface is the interface of carrying out order, data interaction between array main frame and the assistant processing control card of disk array in the utility model.When main frame need be visited assistant processing control card of disk array, send request command by pci interface to assistant processing control card of disk array, assistant processing control card of disk array is done corresponding operation according to the content of order, comprise that read-write board carries storer, carries out XOR computing and encryption, submits the data of returning to by pci interface after finishing again.Pci interface is widely used computer external apparatus interface, has guaranteed that this assistant processing control card of disk array has favorable compatibility.
XOR processing engine and encryption logic unit can be carried out the XOR and the cryptographic calculation of data in enormous quantities at a high speed, and the use dma controller is finished the data transmission between ram in slice (Random Access Memory, random access storage device) and the host memory.
Comprise three data structures in the expansion ROM of assistant processing control card of disk array: expansion ROM head (Option ROM Header), PCI head (PCI Data Structure) and PNP extended head (PNP Expansion Header).The expansion ROM head is used for the population parameter of whole expansion ROM and institutional framework etc. are defined, and it also comprises the entrance of INIT function.The PCI head has defined and this device-dependent basic parameter.The PNP extended head has then defined BBS agreement predetermined parameter, comprises the entry address of BEV (Bootstrap Entry Vector) equipment.Also comprise the INIT function in addition in the expansion ROM.The INIT function is carried out in the POST of BIOS process, and it is used to detect BIOS and whether supports BBS.The loading procedure of customization is pointed in the entry address of BEV equipment, and this program copies operating system loading procedure and operating system nucleus in the internal memory to, and the execution of the loading procedure that starts the operating system.
The utility model is the unconventional starting outfit that has pci interface, adopts FPGA to realize, its XOR processing engine, encryption logic unit, plate carry I/O processing power, the data security that NVRAM can improve system, shortens the I/O response time.Simultaneously, the utility model adopts FPGA to realize that very strong dirigibility is arranged, and by the modification to the FPGA configuration file, can provide different functional parts at concrete application, as the quantity that increases the XOR processing engine, adopt different cryptographic algorithm etc.The method that realizes the multi-functional assistant processing control card of disk array of this pci interface is applied in the design of storage system control card, can effectively improves problems such as memory access speed, solution storage security; The assistant processing control card of disk array that the utility model is realized has guaranteed to can be used for the reliability and stability of disk array control system the startup of disk array storage system and strengthen its performance.
Description of drawings
Fig. 1 is a structural representation of the present utility model;
Fig. 2 is the structural representation of the utility model XOR processing engine;
Fig. 3 is the process flow block diagram of the utility model encryption logic unit;
Fig. 4 is for once encrypting the process flow block diagram of iteration.
Embodiment
The utility model is described in further detail below in conjunction with accompanying drawing.
As shown in Figure 1, assistant processing control card of the present utility model comprises pci interface 110, Flash Memory interface 120, XOR processing engine 130, encryption logic unit 140 and the NVRAM interface of being realized by the FPGA device 150, and plate carries storer Flash Memory chip 160 and NVRAM chip 170 several main parts.Pci interface 110 is PCI (the Peripheral Component Interconnect) interface of 32/64 33MHz/66MHz, can also adopt more PCI-X interface at a high speed and obtains higher speed ability.Main frame is by pci interface visit Flash Memory interface 120, XOR processing engine 130, encryption logic unit 140 and NVRAM interface 150.Flash Memory chip 160 is deposited the disk array control program simultaneously as the expansion ROM of pci card; NVRAM chip 170 is as the Cache of disk array.
Fig. 2 is the treatment scheme structured flowchart of XOR processing engine.The XOR processing engine comprises XOR arithmetic element 240, dual-port data RAM 250, dual-port address RAM260, local Master module 210, dma module 220 and local Target module 230.XOR arithmetic element 240 is responsible for the XOR of data; Dual-port data RAM 250 is used to preserve the intermediate result and the net result of XOR; Dual-port address RAM260 is used to preserve the internal memory first address of pending data block and the internal memory first address of the result returned; Local Master module 210 is responsible for by pci interface visit host memory; Dma module 220 is responsible for the local Master module of control, and provides access interface to upper layer software (applications); Local T arget module 230 be responsible for will be by the pci interface transmission pending data block first address and result of calculation deposit first address and deposit in the two-port RAM 260.
When needs are carried out the XOR processing to data block, program is earlier deposited first address with the first address of pending data block and result of calculation and is write successively among the dual-port address RAM 260 by local T arget module 230, and pending number of data blocks and size passed to dma module 220, dma module 220 reads the first address of the pending data block among the dual-port address RAM 260 immediately, read the pending data in the internal memory and deposit in the dual-port data RAM 250 by local Master module 210, XOR arithmetic element 240 is carried out the XOR of data subsequently, after handling total data, dma module 220 is delivered to assigned address in the host memory by local Master module 210 with result of calculation once more.
Fig. 3 is the process flow block diagram of encryption logic unit, the cryptographic algorithm that adopts is data encryption standard algorithm (Data Encryption Starndard, DES), 64 clear datas are exported with 64 encrypt datas afterwards through initial permutation, 16 encryption iteration, contrary initial permutations.
Fig. 4 enters 64 bit data of encrypting iteration for once encrypting the treatment scheme of iteration, and 32 on the left side constitutes L
I-1, 32 on the right constitutes R
I-164 keys produce 16 sub-keys through conversion, encrypt iteration for 16 times respectively and use; Expand displacement E with 32 R
I-1Be extended for 48 outputs; This output and sub-key are made XOR, and the result who obtains is as the input of choice function group S; Choice function group S determines according to the input data row number of each selection matrix of its correspondence and row number to obtain 32 outputs thus; Result and L that this output obtains by in-place computation P
I-1XOR obtains the right 32 bit data R of next iteration
iAnd R
I-1The left side 32 bit data L as next iteration
i
After system powered on, FPGA carried out active arrangement by its special-purpose configuring chip, and assistant processing control card of disk array is finished self initial work in 10 seconds.In System self-test POST (Power-On SelfTest) process, BIOS can find that assistant processing control card of disk array is a starting outfit.Then whether the INIT function detecting system BIOS of assistant processing control card of disk array BIOS supports BBS, if support then provide rreturn value by the BBS agreement, interrupts if do not support then seize 19H.After POST normally finishes, then call 19H and interrupt carrying out system bootstrap, the 19H Interrupt Service Routine can be carried out the loading procedure of assistant processing control card of disk array, and operating system loading procedure and file destination are loaded in the internal memory, jump to operating system loading procedure porch, finish guiding.So far, disk array enters normal operating conditions, and control program is coordinated and the control total system, by the visit commander assistant processing control card of PCI assistant processing control card register being carried out the operations such as buffer memory, encryption and XOR to data.
Claims (4)
1. assistant processing control card of disk array, it is characterized in that: it comprises pci interface, XOR processing engine, encryption logic unit, Flash Memory interface, NVRAM interface, and FlashMemory chip and NVRAM chip, wherein Flash Memory chip is connected with Flash Memory interface, NVRAM interface electric signals respectively with the NVRAM chip, and XOR processing engine, encryption logic unit, Flash Memory interface and NVRAM interface are connected with pci interface by PCI rear end equipment signal; Pci interface is finished order and the data interaction between main frame and this assistant processing control card of disk array; The XOR processing engine is finished XOR; The encryption logic unit performs encryption processing; Flash Memory interface and NVRAM interface are responsible for control Flash Memory chip and NVRAM chip respectively; Flash Memory chip is deposited the disk array control program simultaneously as the expansion ROM of pci card; The NVRAM chip is as the high-speed cache of disk array.
2. assistant processing control card of disk array as claimed in claim 1 is characterized in that: described Flash Memory chip is deposited the firmware of following the BBS agreement as expansion ROM; For the operating system pSOS+ that the disk array Control Software adopts, VxWorks or Linux, this firmware are respectively the corresponding version of following the BBS agreement.
3. assistant processing control card of disk array as claimed in claim 1 or 2 is characterized in that: adopt FPGA to realize described pci interface, XOR processing engine, encryption logic unit, FlashMemory interface and NVRAM interface; Described Flash Memory chip and NVRAM chip are that plate carries storer.
4. assistant processing control card of disk array as claimed in claim 3 is characterized in that: described XOR processing engine comprises XOR arithmetic element, dual-port data RAM, dual-port address RAM, local Master module, dma module and local Target module; The XOR arithmetic element is responsible for the XOR of data; The dual-port data RAM is used to preserve the intermediate result and the net result of XOR; Dual-port address RAM is used to preserve the internal memory first address of pending data block and the internal memory first address of the result returned; Local Master module is responsible for by pci interface visit host memory; Dma module is responsible for controlling local Master module, and provides access interface to upper layer software (applications); Local T arget module be responsible for will be by pci interface transmission pending data block first address and result of calculation deposit first address and deposit in the two-port RAM 260.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006201633515U CN201011563Y (en) | 2006-12-01 | 2006-12-01 | Disk array assistant processing controlling card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006201633515U CN201011563Y (en) | 2006-12-01 | 2006-12-01 | Disk array assistant processing controlling card |
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| Publication Number | Publication Date |
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| CN201011563Y true CN201011563Y (en) | 2008-01-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNU2006201633515U Expired - Lifetime CN201011563Y (en) | 2006-12-01 | 2006-12-01 | Disk array assistant processing controlling card |
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| CN (1) | CN201011563Y (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101667103B (en) * | 2008-09-01 | 2011-05-04 | 智微科技股份有限公司 | Disk array 5 controller and access method |
| CN102760045A (en) * | 2011-04-29 | 2012-10-31 | 无锡江南计算技术研究所 | Intelligent storage device and data processing method thereof |
| CN104158875A (en) * | 2014-08-12 | 2014-11-19 | 上海新储集成电路有限公司 | Method and system for sharing and reducing tasks of data center server |
-
2006
- 2006-12-01 CN CNU2006201633515U patent/CN201011563Y/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101667103B (en) * | 2008-09-01 | 2011-05-04 | 智微科技股份有限公司 | Disk array 5 controller and access method |
| CN102760045A (en) * | 2011-04-29 | 2012-10-31 | 无锡江南计算技术研究所 | Intelligent storage device and data processing method thereof |
| CN102760045B (en) * | 2011-04-29 | 2015-07-08 | 无锡江南计算技术研究所 | Intelligent storage device and data processing method thereof |
| CN104158875A (en) * | 2014-08-12 | 2014-11-19 | 上海新储集成电路有限公司 | Method and system for sharing and reducing tasks of data center server |
| CN104158875B (en) * | 2014-08-12 | 2018-04-20 | 上海新储集成电路有限公司 | It is a kind of to share the method and system for mitigating data center server task |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20080123 |
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| EXPY | Termination of patent right or utility model |