CN200962632Y - Dual processor communication circuit of TV set - Google Patents
Dual processor communication circuit of TV set Download PDFInfo
- Publication number
- CN200962632Y CN200962632Y CNU2006200113509U CN200620011350U CN200962632Y CN 200962632 Y CN200962632 Y CN 200962632Y CN U2006200113509 U CNU2006200113509 U CN U2006200113509U CN 200620011350 U CN200620011350 U CN 200620011350U CN 200962632 Y CN200962632 Y CN 200962632Y
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- chip
- main process
- analog codec
- terminal
- communication circuit
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Abstract
The utility model discloses a dual processor telecommunication circuit of a television comprising a body core and a simulation decode chip, wherein the simulation decode chip comprises an independent CPU and a data communication terminal and a clock signal terminal of the body core are separately and correspondingly connected with a data terminal and a clock terminal of the simulation decode chip. A reading request receiving end, a writing request sending end and preparation command receiving end of the body core is separately and correspondingly connected with a reading request sending end, a writing request receiving end and preparation command sending end of the simulation decode chip. The utility model makes use of GPIO end simulation I[2] C bus end, reading and writing request end, and preparation command end for resolving a communication channel and a protocol between the CPU of the body core and the simulation decode chip by simple circuit structure, thereby simplifying integral design of system circuit board and saving cost of a set of liquid crystal television product.
Description
Technical field
The utility model belongs to technical field of television sets, relate to a kind of improvement of TV set circuit, specifically, relate to a kind of in the TV set circuit that includes the high integration decoding chip, the double processor communication circuit that designs for the exchanges data that realizes between the separate CPU in television set master control system CPU and the decoding chip.
Background technology
At present, the control system of liquid crystal TV set is generally single CPU, just controls in the TV set circuit other chip with a CPU and makes the whole system operate as normal.But, continuous development along with decoding chip, PHILIPS Co. has released the high analog codec chip UOC3 of a integrated level, its inside not only includes circuit such as small-signal processing, audio processing, picture and text processing and beautiful sound processing, and compare traditional analog circuit, its cost is lower, needs the peripheral circuit of configuration simple, can help the popularization of world market in global All Countries work.In the LCD TV machine circuit, use described analog codec chip UOC3, not only can effectively simplify the global design of circuit board, save taking up room of pcb board, and can make the complete machine cost reduce, help improving the market competitiveness of tv product.But, because analog codec chip UOC3 has own independent CPUs, and oneself CPU is also arranged, therefore as the control chip of primary processor, how to allow two CPU intercom mutually well, thereby make the whole TV system operate as normal just become the problem that needs solve.
Summary of the invention
The utility model is in order to solve the problem of accurately communicating by letter between the separate CPU in the television set master process chip and decoding chip in the prior art, a kind of novel double processor communication circuit is provided, realize the proper communication of data between main process chip and the decoding chip with simple circuit configuration, thereby guaranteed the operate as normal of whole TV system.
For solving the problems of the technologies described above, the utility model is achieved by the following technical solutions:
Double processor communication circuit in a kind of television set comprises main process chip and analog codec chip, wherein, includes independent CPUs in described analog codec chip; The data communication end of described main process chip and clock signal terminal respectively be connected corresponding of data terminal of described analog codec chip with clock end; The read data request receiving terminal of main process chip, write data requests transmitting terminal and be ready to the order receiving terminal respectively with read data request transmitting terminal, the write data requests receiving terminal of analog codec chip be ready to that the order transmitting terminal is corresponding to be connected.
In the utility model, it is the integrated chip realization of GM2221 that described main process chip adopts model; It is that UOC3 high integration analog codec chip is realized that the analog codec chip adopts model.Described main process chip utilize its 5 GPIO mouths as data communication end, clock signal terminal, read data request receiving terminal, write data requests transmitting terminal and be ready to the order receiving terminal respectively with 5 corresponding connections of GPIO mouth of described analog codec chip.
In order to realize the reliable communication of signal between main process chip and the analog codec chip, be connected by pull-up resistor on the level of DC power supply and draw branch road being connected with one on the GPIO mouth line of described main process chip and analog codec chip respectively.The magnitude of voltage of described DC power supply is+5V.
Compared with prior art, advantage of the present utility model and good effect are: the utility model utilizes the GPIO mouth Simulation with I of main process chip and analog codec chip
2C bus end and reading and writing request of data end and warning order end, solved communication port and the agreement between the CPU in main process chip and the analog codec chip with simple circuit configuration, make the proper communication that has realized data between the two, the stability and the reliability of liquid crystal TV set system works have been guaranteed, effectively simplify the global design of system circuit board, saved the complete machine cost of LCD TV product.
Description of drawings
Fig. 1 is the theory diagram of double processor communication circuit in the utility model.
Embodiment
Below in conjunction with the drawings and specific embodiments the utility model is done explanation in further detail.
The utility model is that the integrated chip of GM2221 is an example as television set master process chip with the model, specifically sets forth the reliable communication of data between main process chip and the analog codec chip UOC3.5 universal input and output port GPIO mouth: GPIO0 (SDA), GPIO1 (SCL), GPIO2 (ReqReadEvent), GPIO3 (ReqComm), the GPIO4 (ReadyComm) that utilizes main process chip GM2221 respectively as data bus terminal, clock bus end, read data request receiving terminal, write data requests transmitting terminal and be ready to the order receiving terminal respectively with 5 GPIO mouth: P1.7 (SDA), P1.6 (SCL), P1.3 (ReqReadEvent), P0.0 (ReqComm), corresponding connection of P0.1 (ReadyComm) of analog codec chip UOC3, as shown in Figure 1.In order to realize the reliable communication of signal between main process chip GM2221 and the analog codec chip UOC3, draw branch road being connected with respectively on the line of described main process chip GM2221 and 5 corresponding GPIO mouths of analog codec chip UOC3 on the level by 3.3K Ω pull-up resistor connection+5V DC power supply, not shown in the accompanying drawing.
Under the normal condition, main process chip GM2221 and analog codec chip UOC3 do not communicate, but require every 10ms～20ms to detect once.Main process chip GM2221 detects read data request holding wire ReqReadEvent, and analog codec chip UOC3 detects write data requests holding wire ReqComm, finds that the other side carries out correspondingly communication operation when request is arranged.For example: when main process chip GM2221 will write data to analog codec chip UOC3, it is low level that main process chip GM2221 is provided with its GPIO3 (ReqComm) port, after analog codec chip UOC3 detects its P0.0 (ReqComm) port and is low level, stop its inner I
2The C bus activity, it is low level that its P0.1 (ReadyComm) port is set; After main process chip GM2221 detects its GPIO4 (ReadyComm) port and is low level, begin to write data among the analog codec chip UOC3 by bus port GPIO0 (SDA), GPIO1 (SCL); After analog codec chip UOC3 is received the data of main process chip GM2221 transmission, it is high level that main process chip GM2221 is provided with its GPIO3 (ReqComm) port, it is high level that analog codec chip UOC3 is provided with its P0.1 (ReadyComm) port, and analog codec chip UOC3 returns holotype.Will be from analog codec chip UOC3 during read data as main process chip GM2221, execution sequence writes data to the sequential of analog codec chip UOC3 with main process chip GM2221; Analog codec chip UOC3 reminds main process chip GM2221 state-event to change, be that its P1.3 (ReqReadEvent) port is set is low level to analog codec chip UOC3, after main process chip GM2221 detects its GPIO2 (ReqReadEvent) port and is low level, carry out main process chip GM2221 from the order of analog codec chip UOC3 read data, and then from analog codec chip UOC3, read event information.
The utility model is by adopting above-mentioned simple circuit configuration and communication protocol, the mainboard of separate CPU and the data communication between the decoding deck have been realized having separately in the liquid crystal TV set, not only simplified the global design of circuit board, and saved the television set cost, improved the stability of system works.
Certainly; above-mentioned explanation is not to be to restriction of the present utility model; the utility model also is not limited in above-mentioned giving an example, and variation, remodeling, interpolation or replacement that those skilled in the art are made in essential scope of the present utility model also should belong to protection range of the present utility model.
Claims (6)
1. the double processor communication circuit in the television set, comprise main process chip and analog codec chip, wherein, in described analog codec chip, include independent CPUs, it is characterized in that: the data communication end of described main process chip and clock signal terminal respectively be connected corresponding of data terminal of described analog codec chip with clock end; The read data request receiving terminal of main process chip, write data requests transmitting terminal and be ready to the order receiving terminal respectively with read data request transmitting terminal, the write data requests receiving terminal of analog codec chip be ready to that the order transmitting terminal is corresponding to be connected.
2. double processor communication circuit according to claim 1 is characterized in that: described main process chip utilize its 5 GPIO mouths as data communication end, clock signal terminal, read data request receiving terminal, write data requests transmitting terminal and be ready to the order receiving terminal respectively with 5 corresponding connections of GPIO mouth of described analog codec chip.
3. double processor communication circuit according to claim 2 is characterized in that: be connected by pull-up resistor on the level of DC power supply and draw branch road being connected with one on the GPIO mouth line of described main process chip and analog codec chip respectively.
4. double processor communication circuit according to claim 3 is characterized in that: the magnitude of voltage of described DC power supply is+5V.
5. double processor communication circuit according to claim 1 is characterized in that: described analog codec chip is that model is a UOC3 high integration analog codec chip.
6. double processor communication circuit according to claim 1 is characterized in that: the model of described main process chip is GM2221.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006200113509U CN200962632Y (en) | 2006-10-22 | 2006-10-22 | Dual processor communication circuit of TV set |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006200113509U CN200962632Y (en) | 2006-10-22 | 2006-10-22 | Dual processor communication circuit of TV set |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN200962632Y true CN200962632Y (en) | 2007-10-17 |
Family
ID=38799141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2006200113509U Expired - Fee Related CN200962632Y (en) | 2006-10-22 | 2006-10-22 | Dual processor communication circuit of TV set |
Country Status (1)
| Country | Link |
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| CN (1) | CN200962632Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104679715A (en) * | 2013-12-03 | 2015-06-03 | 厦门雅迅网络股份有限公司 | Simple inter-chip communication method and simple inter-chip communication device |
-
2006
- 2006-10-22 CN CNU2006200113509U patent/CN200962632Y/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104679715A (en) * | 2013-12-03 | 2015-06-03 | 厦门雅迅网络股份有限公司 | Simple inter-chip communication method and simple inter-chip communication device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071017 Termination date: 20101022 |