CN1996563A - The encapsulation structure of the optical component semiconductor and its encapsulation method - Google Patents
The encapsulation structure of the optical component semiconductor and its encapsulation method Download PDFInfo
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- CN1996563A CN1996563A CNA2006100025485A CN200610002548A CN1996563A CN 1996563 A CN1996563 A CN 1996563A CN A2006100025485 A CNA2006100025485 A CN A2006100025485A CN 200610002548 A CN200610002548 A CN 200610002548A CN 1996563 A CN1996563 A CN 1996563A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
Abstract
This invention provides one semiconductor sealing structure with optical elements and its sealing method, wherein, the sealing structure comprises one chip, one metal distribution circuit, one transparent insulation layer and one metal reset circuit, wherein, the crystal circle has one main surface, one back surface, at least one pass hole, one optical part and at least one top weld pad; the metal reset circuit is on crystal circle main surface to connect weld pad and metal column; the transparent insulation layer is on main surface of the crystal circle.
Description
[technical field]
The present invention is about a kind of semiconductor package and method for packing thereof, especially about a kind of semiconductor package and method for packing thereof with optical module.
[background technology]
Please refer to Fig. 1 and Fig. 2, its demonstration be United States Patent (USP) US6, the encapsulating structure and the method for packing that are disclosed for 040, No. 235.The method for packing of this encapsulating structure 10 is as follows, at first, an insulation material 11 is fitted in the active surface of a wafer.Then, this wafer is cut into several crystal grain (die) 12, and expose the weld pad 13 on these crystal grain 12 active surfaces.Then, again after those crystal grain 12 lower surfaces form two insulating barriers 14,15, form several wiring (electrical contact) 16, an end of those wiring 16 connects weld pad 13, and it extends to the upper surface 112 of insulation material 11 along the side surface 111 of insulation material 11.Afterwards, along a line of cut 17 cuttings, to form this encapsulating structure 10.
Please refer to Fig. 3 and Fig. 4, its demonstration be United States Patent (USP) US6, the method for packing that is disclosed for 271, No. 469.This method is inserted a chip 20 in the opening 23 of colloid 22 in its passive 21 mode down earlier, and exposes several weld pads 24 on its active surface.Then, on this active surface, form one first insulating barrier 26.Afterwards, on this first insulating barrier 26, form several openings 27, to expose those weld pads 24, as shown in Figure 3.Then, form a metallic circuit 28 on first insulating barrier 26, this metallic circuit 28 sees through those openings 27 and is electrically connected with those weld pads 24.Afterwards, on first insulating barrier 26 and metallic circuit 28, form one second insulating barrier 29.By this, can form the encapsulating structure of a bumpless, yet if this chip 20 is optical module, its active surface must can receive light source, so the technology that this patent disclosed and be not suitable for the encapsulating optical assembly, its application is limited.
Therefore, be necessary to provide the semiconductor package with optical module and the method for packing thereof of a kind of innovation and tool progressive, to address the above problem.
[summary of the invention]
The present invention's main purpose is to provide a kind of semiconductor package and method for packing thereof with optical module, and this method processing procedure is simple, and required cost is low.
For achieving the above object, the invention provides a kind of method for packing with semiconductor package of optical module, it comprises: a wafer (a) is provided, this wafer has an active surface and a back side, have an optical module and at least one weld pad of going up on this active surface, wherein this optical module system is electrically connected to weld pad on this; (b) on this wafer active surface, form at least one perforate; (c) on the hole wall of this perforate, form an insulating barrier; (d) forming metal level on this wafer active surface, and should go up metal level and fill up this perforate; (e) patterning should be gone up metal level, forming metal rerouting circuit on, and then made that weld pad is electrically connected to the interior metal of this perforate this on; (f) applying one transparent insulating layer on this wafer active surface; (g) remove the partly back side of wafer, so that the metal exposed in this perforate goes out the back side of this wafer; (h) form the circuit of metal rerouting at wafer rear, this time metal rerouting circuit is electrically connected the metal in the perforate; And (i) cut this wafer, to form other semiconductor package.
The present invention provides a kind of semiconductor package with optical module in addition, and it comprises metal rerouting circuit on the chip,, a transparent insulating layer and the circuit of metal rerouting once.This chip has an active surface, a back side and at least one through hole, have an optical module and at least one weld pad of going up on this active surface, wherein this optical module is electrically connected to weld pad on this, fills up a metal column in this through hole, has an insulating barrier between the hole wall of this through hole and this metal column.Should go up metal rerouting circuit and be positioned on this chip active surface, and connect upward weld pad and this metal column.This transparent insulating layer is positioned on this wafer active surface.This time metal rerouting circuit system is positioned at this wafer rear, and is electrically connected this metal column.
[description of drawings]
Fig. 1 and Fig. 2 show a traditional semiconductor package and a method for packing thereof;
Fig. 3 and Fig. 4 show the method for packaging semiconductor that another is traditional;
Fig. 5 has the flow chart of method for packing one preferred embodiment of the semiconductor package of optical module for the present invention; And
Fig. 6 to 23 is the structural representation corresponding to each step among Fig. 5.
[embodiment]
Please refer to Fig. 5, this is illustrated as the flow chart of method for packing one preferred embodiment that the present invention has the semiconductor package of optical module.Please in the lump with reference to figure 6 to 23, those are illustrated as the structural representation corresponding to each step among Fig. 5 again.
At first, step S101 provides a wafer 30, and this wafer 30 has an active surface 301, a back side 302 and some lines of cut 305.Have an optical module 303 and at least one weld pad 304 of going up on this active surface 301, this optical module 303 wherein, for example (ComplementaryMetal-Oxide Semiconductor CMOS), is electrically connected to weld pad 304 on this to a complementary metal oxide silicon.Those lines of cut 305 define several chip 306, as shown in Figure 6.
Then, step S102 forms a dielectric layer (dielectriclayer) 31 on the active surface 301 of wafer 30, as shown in Figure 7.The reason that forms this dielectric layer 31 is for follow-up metal level is formed on the active surface 301 of this wafer 30 with comparalive ease, and therefore, this step S102 is the selectivity step.
Then, step S103 forms at least one perforate 32 at the active surface 301 of wafer 30, as shown in Figure 8.In the present embodiment, this perforate 32 does not run through this wafer 30, and this perforate 32 reaches between the weld pad 304 at line of cut 305.The mode that forms this perforate 32 can include but not limited to laser cutting and dry-etching, wherein, if adopt the mode of dry-etching, then need to form opening prior to the position of these dielectric layer 31 relative these perforates 32, utilize this wafer 30 of gas etch of sulphur hexafluoride (SF6) again; If adopt the mode of laser cutting, then directly remove this wafer 30 of part and this dielectric layer 31 and get final product.
Then, step S104 forms an insulating barrier 34 on the hole wall of this perforate 32.In the present embodiment, this step S104 is reached by the following step.At first, on dielectric layer 31, form a photoresist layer 33, as shown in Figure 9.Then, form at least one opening 331 on photoresist layer 33, this opening 331 is corresponding to described perforate 32, as shown in figure 10.In the present embodiment, this opening 331 utilizes the exposure imaging mode to form.Afterwards, on the hole wall of perforate 32, form an insulating barrier 34, as shown in figure 11.In the present embodiment, this insulating barrier 34 utilizes the long-pending mode in gas phase Shen to form.At last, remove this photoresist layer 33, as shown in figure 12.
Then, step S105 is forming metal level 35 on the dielectric layer 31 on the active surface 301 of wafer 30; If there is not this dielectric layer 31, then should goes up metal level 35 and be formed on the active surface 301 of wafer 30, and should go up metal level 35 and fill up described perforate 32, and form a metal column (metal post) 36, as shown in figure 13.In the present embodiment, this step S105 is reached by the following step.At first, on the hole wall of dielectric layer 31 and perforate 32, utilize sputtering way to form a kind of crystal layer (seed layer).Then, utilize plating mode metal level 35 on formation on this kind crystal layer is described, so that should go up the enough thickness of metal level 35 accumulations, and upward metal level 35 fills up perforate 32.
Then, step S106 patterning should be gone up metal level 35, to form metal rerouting circuit (redistribution layer, RDL) 37 on one.Upward weld pad 304 is electrically connected to the metal (being metal column 36) in the perforate 32 through metal rerouting circuit 37 on this, as shown in figure 14.
Then, step S107 utilizes a glue-line 39 transparent insulating layer 38 (a for example glass) of fitting on the dielectric layer 31 on the active surface 301 of wafer 30, as shown in figure 15, if there is not this dielectric layer 31, then this transparent insulating layer 38 utilizes glue-line 39 to fit on the active surface 301 of wafer 30.
Then, step S108 removes the partly back side 302 of wafer 30, so that the metal (being metal column 36) in the perforate 32 exposes the back side 302 of wafer 32, as shown in figure 16.In the present embodiment, utilize lapping mode to grind whole wafer 32 back sides 302, at this moment, perforate 32 can become the through hole of consistent transcrystalline circle 30, and the lower surface of metal column 36 exposes the back side 302 of wafer 32.In addition, if necessary, can utilize the dry-etching mode to remove the partly back side 302 of wafer 32 again, to expose the lower end of metal column 36, in order to subsequent job, as shown in figure 17.
Then, step S109 forms a stress-buffer layer 40 at the back side 302 of wafer 30, and this stress-buffer layer 40 does not cover the lower surface of metal column 36, as shown in figure 18.Be noted that this step S109 is a selectivity step.
Then, step S110 forms the circuit of metal rerouting 41 on the stress-buffer layer 40 at the back side 302 of wafer 30, and this time metal rerouting circuit 41 is connected in the lower surface of metal column 36, as shown in figure 19.If there is not this stress-buffer layer 40, then this time metal rerouting circuit 41 is formed on the back side 302 of wafer 30.
Then, step S111 is forming a welding resisting layer (solder mask) 42 on metal rerouting circuit 41 and the stress-buffer layer 40 down, as shown in figure 20.Wherein this welding resisting layer 42 has at least one opening 421, and this opening 421 defines the following connection pad 43 of this time metal rerouting circuit 41.
Then, step S112 promptly forms several tin balls 44, as shown in figure 21 for planting the ball step on this time connection pad 43.Be noted that this step S112 is a selectivity step.
At last, step S113 is a cutting step.In the present embodiment, before cutting, be that earlier the line of cut 305 corresponding positions of wafer 30 form a breach (notch) 45, as shown in figure 22.Carry out cutting operation afterwards again, to form an encapsulating structure 50, as shown in figure 23.
Please refer to Figure 23, its demonstration be the schematic diagram of the preferred embodiment of the semiconductor package of the present invention with optical module.Semiconductor package 50 of the present invention comprises metal rerouting circuit 37, transparent insulating layer 38 and the circuit of metal rerouting once 41, a welding resisting layer 42 and an at least one tin ball 44 on the chip 306.
Described chip 306 has an active surface 301, a back side 302 and at least one through hole 46, have an optical module 303 and at least one weld pad 304 of going up on this active surface 301, wherein this optical module 303 is electrically connected to weld pad 304 on this, fill up a metal column 36 in this through hole 46, have an insulating barrier 34 between the hole wall of this through hole 46 and this metal column 36.
The described metal rerouting circuit 37 of going up is positioned on the active surface 301 of chip 30, and metal rerouting circuit 37 connects upward weld pad 304 and this metal column 36 on this.Preferably, 301 of active surfaces of metal rerouting circuit 37 and wafer 30 have a dielectric layer 31 on this.This transparent insulating layer 38 (a for example glass) is positioned on the active surface 301 of wafer 30.Preferably, 301 of this transparent insulating layer 38 and this active surfaces have a glue-line 39.This time metal rerouting circuit 41 is positioned at the back side 302 of wafer 30, and this time metal rerouting circuit 41 is electrically connected in the lower surface of metal column 36.Preferably, the back side 302 of wafer 30 and 41 in following metal rerouting circuit also comprise a stress-buffer layer 40.
The lower surface of metal rerouting circuit 41 and stress-buffer layer 40 under described welding resisting layer 42 is positioned at, it has at least one opening, and this opening defines down the following connection pad 43 of metal rerouting circuit 41.Described tin ball 44 is arranged at this time connection pad 43.
Though the present invention discloses as above with aforesaid embodiment, it is not in order to limit the present invention.Without departing from the spirit and scope of the present invention, those of ordinary skill in the art can carry out various changes to the present invention.If modification of the present invention is belonged within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes interior.
Claims (14)
1. the method for packing with semiconductor package of optical module is characterized in that, this method comprises the steps:
(a) provide a wafer, this wafer has an active surface and a back side, has an optical module and at least one weld pad of going up on this active surface, and wherein this optical module is electrically connected to weld pad on this;
(b) active surface at wafer forms at least one perforate;
(c) on the hole wall of perforate, form an insulating barrier;
(d) forming metal level on the active surface of wafer, and should go up metal level and fill up described perforate;
(e) patterning should be gone up metal level, to form metal rerouting circuit on, made this go up weld pad and was electrically connected to the interior metal of described perforate;
(f) applying one transparent insulating layer on the active surface of wafer;
(g) remove the partly back side of wafer, so that the metal exposed in the described perforate goes out the back side of wafer;
(h) form the circuit of metal rerouting at the back side of wafer, this time metal rerouting circuit is electrically connected the metal in the described perforate; And
(i) cut described wafer, to form other semiconductor package.
2. method for packing as claimed in claim 1 is characterized in that: described step (a) comprises also that afterwards (a1) forms a dielectric layer at the active surface of wafer.
3. method for packing as claimed in claim 1 is characterized in that: what form the perforate employing in the described step (b) is laser cutting mode or dry-etching mode.
4. method for packing as claimed in claim 1 is characterized in that: described step (c) further comprises the steps:
(c1) active surface at wafer forms a photoresist layer;
(c2) form at least one opening on photoresist layer, this opening is corresponding to described perforate;
(c3) hole wall in perforate forms an insulating barrier; And
(c4) remove photoresist layer.
5. method for packing as claimed in claim 4 is characterized in that: described step (c2) is to utilize the exposure imaging mode to form described opening, and described step (c3) is to utilize the long-pending mode in gas phase Shen to form described insulating barrier.
6. method for packing as claimed in claim 1 is characterized in that: described step (d) further may further comprise the steps:
(d1) form a kind of crystal layer at the active surface of wafer and the hole wall of perforate; And
(d2) metal level on formation on kind of the crystal layer is described.
7. method for packing as claimed in claim 6 is characterized in that: described step (d1) is to utilize sputtering way to form described kind of crystal layer, and described step (d2) is to utilize plating mode to form described metal level.
8. method for packing as claimed in claim 1 is characterized in that: described step (g) further may further comprise the steps:
(g1) remove partly wafer rear, so that described perforate forms a through hole; And
(g2) remove partly wafer rear again, so that the metal exposed in the described perforate goes out the back side of wafer.
9. method for packing as claimed in claim 8 is characterized in that: described step (g1) is to utilize lapping mode to remove partly wafer rear, and described step (g2) is to utilize the dry-etching mode to remove partly wafer rear.
10. method for packing as claimed in claim 1 is characterized in that: described step (h) further may further comprise the steps:
(h1) form a stress-buffer layer at wafer rear, this stress-buffer layer does not cover the metal in the described perforate;
(h2) form a lower metal layer on this stress-buffer layer, this lower metal layer connects the metal in the described perforate; And
(h3) this lower metal layer of patterning is to form described metal rerouting circuit down.
(h4) forming a welding resisting layer on the metal rerouting circuit down; And
(h5) form at least one opening on this welding resisting layer, this opening defines down the following connection pad of metal rerouting circuit.
(h6) form several tin balls at following connection pad.
11. method for packing as claimed in claim 1, it is characterized in that: described step (h) also is included in down the step that forms a welding resisting layer on the metal rerouting circuit afterwards, and the step that on this welding resisting layer, forms at least one opening, wherein this opening defines down the following connection pad of metal rerouting circuit.
12. semiconductor package with optical module, it is characterized in that, this encapsulating structure comprises: a chip, it has an active surface, a back side and at least one through hole, have an optical module and at least one weld pad of going up on this active surface, this optical module is electrically connected in weld pad on this, fills up a metal column in this through hole, has an insulating barrier between the hole wall of this through hole and this metal column; One is positioned at the last metal rerouting circuit of chip active surface, and it is connected in weld pad and this metal column on this; One is positioned at the transparent insulating layer of chip active surface; And a following metal rerouting circuit that is positioned at chip back, it is electrically connected in this metal column.
13. semiconductor package as claimed in claim 12, it is characterized in that: this encapsulating structure also comprises a dielectric layer between last metal rerouting circuit and chip active surface, one stress-buffer layer between chip back and following metal rerouting circuit, and one be positioned at the down welding resisting layer of metal rerouting circuit lower surface, described welding resisting layer has at least one opening, and this opening defines down the following connection pad of metal rerouting circuit.
14. semiconductor package as claimed in claim 12 is characterized in that: this encapsulating structure also comprises several tin balls that are positioned on the following metal rerouting circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100025485A CN100452330C (en) | 2006-01-06 | 2006-01-06 | The encapsulation structure of the optical component semiconductor and its encapsulation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100025485A CN100452330C (en) | 2006-01-06 | 2006-01-06 | The encapsulation structure of the optical component semiconductor and its encapsulation method |
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| Publication Number | Publication Date |
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| CN1996563A true CN1996563A (en) | 2007-07-11 |
| CN100452330C CN100452330C (en) | 2009-01-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2006100025485A Active CN100452330C (en) | 2006-01-06 | 2006-01-06 | The encapsulation structure of the optical component semiconductor and its encapsulation method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101710581B (en) * | 2009-10-16 | 2012-12-26 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure of semiconductor chip and manufacturing technology thereof |
| CN105789062A (en) * | 2014-09-05 | 2016-07-20 | 台湾积体电路制造股份有限公司 | Package Structure And Method Of Forming The Same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1210789C (en) * | 2002-09-19 | 2005-07-13 | 威盛电子股份有限公司 | Semiconductor packaging element with heat sink structure |
| CN1316611C (en) * | 2004-03-19 | 2007-05-16 | 矽品精密工业股份有限公司 | Wafer-level semiconductor package having lamination structure and making method thereof |
-
2006
- 2006-01-06 CN CNB2006100025485A patent/CN100452330C/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101710581B (en) * | 2009-10-16 | 2012-12-26 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure of semiconductor chip and manufacturing technology thereof |
| CN105789062A (en) * | 2014-09-05 | 2016-07-20 | 台湾积体电路制造股份有限公司 | Package Structure And Method Of Forming The Same |
| US10672738B2 (en) | 2014-09-05 | 2020-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming |
| US11444057B2 (en) | 2014-09-05 | 2022-09-13 | Taiwan Semiconductor Manufacturing Company Ltd | Package structures and methods of forming |
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| Publication number | Publication date |
|---|---|
| CN100452330C (en) | 2009-01-14 |
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