CN1996147A - TFT array semi-exposure photoetching technology - Google Patents
TFT array semi-exposure photoetching technology Download PDFInfo
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- CN1996147A CN1996147A CNA2005101122577A CN200510112257A CN1996147A CN 1996147 A CN1996147 A CN 1996147A CN A2005101122577 A CNA2005101122577 A CN A2005101122577A CN 200510112257 A CN200510112257 A CN 200510112257A CN 1996147 A CN1996147 A CN 1996147A
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- photo etching
- tft array
- tft
- exposure
- pattern
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Abstract
A TFT array half exposure photo etching technique sets photo mask plate lower than the marginal resolution ratio pattern at the slot of the thin film transistor, applying photo etching at the liner of the already formed half semi conductor film and metal film. It can be used for TFT-LCD silicon island pattern and source/leakage pattern formation, using one time photo etching process to form the above pattern, with one more less photo etching times, reduced photo etching mask plate cost and processes, playing a big role in saving cost, reducing process time and increasing production volume.
Description
Technical field
The present invention relates to a kind of tft array semi-exposure photoetching technology
Background technology
Form thin film transistor (TFT) (TFT in order to go up at transparent insulation substrate (as glass), Thin FilmTransistor) array, in the tft array production technology, need to use the photomask blank (Photo Mask) of some on substrate, to carry out photoetching processes such as film forming, exposure, etching repeatedly, with the lead-in wire that forms tft array, electrode, terminal, each insulating film layer etc.Since the large-scale production manufacturing of TFT-LCD in 1993 begins, in order to reduce production costs, improve yield of products, each manufacturer constantly by changing the structural design of TFT, makes great efforts to reduce the photoetching process number of times in the array processes.The TFT structure finally develops into contact hole (Contact Hole) integrate type that generally adopts at present through raceway groove (Channel) protection type, channel-etch type, and the photoetching number of times also reduces to 5 times by 6～8 times.Be difficult to reduce the number of times of photoetching process at present, can only improve existing photoetching process itself by the change of TFT structure.
When the tft array explained hereafter, need carry out repeatedly photoetching repeatedly, just can finish the making of thin film transistor (TFT) array.Gate electrode, source electrode and electric leakage level, channel semiconductor, source-drain electrode are connected with transparency electrode with being formed in the thin film transistor (TFT) array production of contact hole, transparency electrode figures and are absolutely necessary.During common thin film transistor (TFT) array is produced, in order to form above-mentioned figure, need to adopt the photomask blank more than 5, the photoetching process of carrying out more than 5 times realizes, production cost height, operation number are many.
Usually in thin film transistor (TFT) array is produced, need the figure of Twi-lithography ability formation source electric leakage level and channel semiconductor.Promptly elder generation by a photoetching, forms required semiconductor figure on the substrate after the semiconductor film forming, carries out the metal film forming of source-drain electrode afterwards, again by photoetching for the second time, forms the source-drain electrode figure.
Summary of the invention
The objective of the invention is existing processes is improved to simplify technology, to reduce the lay photoetching mask plate usage quantity.
The objective of the invention is to be achieved through the following technical solutions:
A kind of tft array semi-exposure photoetching technology is provided with the photomask blank that is lower than the critical resolution sizes figure of exposure sources in the thin film transistor channel position, implements photoetching process on the substrate that forms semiconductor film and metallic diaphragm.
Through to the first time of metallic diaphragm at wet quarter, to after semi-conductive dried quarter, the more residual photoresist of previous step is carried out etching, remove the residual photoresist of channel part, then metallic diaphragm is carried out wet quarter second time.
Positive progressive effect of the present invention is: silicon island pattern and source/leakage level pattern that can be applied in the TFT-LCD production form, can only utilize a photoetching process promptly to form above-mentioned figure, reduce the one or many photoetching than traditional handicraft, can reduce the cost of lay photoetching mask plate and reduce the operation number, for saving cost and shortening the process time, increase turnout great role is arranged.
Description of drawings
Fig. 1 a-1d is the process synoptic diagram of one embodiment of the invention.
Embodiment
Provide preferred embodiment of the present invention below in conjunction with accompanying drawing, to describe technical scheme of the present invention in detail.
Shown in Fig. 1 a-1d, a kind of tft array semi-exposure photoetching technology is provided with the photomask blank that is lower than the critical resolution sizes figure of exposure sources in the thin film transistor channel position, implements photoetching process on the substrate that forms semiconductor film and metallic diaphragm.
Through to the first time of metallic diaphragm at wet quarter, to after semi-conductive dried quarter, the more residual photoresist of previous step is carried out etching, remove the residual photoresist of channel part, then metallic diaphragm is carried out wet quarter second time.
For a glass substrate that gate pattern has been arranged and formed semiconductor film and metallic diaphragm, through the clean operation before the photoresist coating, photoresist coating (2.2 μ m) and through 120 ℃ prebake, enter into exposure device (can adopt Canon to produce MPA-7800).
Adopt the exposure of 85mJ during exposure, use one to be provided with the lithography mask version (as the HOYA system) that is lower than the critical resolution sizes figure of exposure sources in the thin film transistor channel position and to expose, afterwards through development, after cure and finish photoetching process.Process to wet the first time of metallic diaphragm, to after semi-conductive dried quarter at quarter again, and semiconductor figure forms, and afterwards photoresist is carried out etching, removes the residual photoresist of channel part, and metallic diaphragm is carried out the second time wet quarter, thus formation source-drain electrode figure.
Claims (2)
1, a kind of tft array semi-exposure photoetching technology is characterized in that, the photomask blank that is lower than the critical resolution sizes figure of exposure sources is set in the thin film transistor channel position, implements photoetching process on the substrate that forms semiconductor film and metallic diaphragm.
2, tft array semi-exposure photoetching technology according to claim 1, it is characterized in that, process is to the first time of metallic diaphragm at wet quarter, to after semi-conductive dried quarter, again the residual photoresist of previous step is carried out etching, remove the residual photoresist of channel part, then metallic diaphragm is carried out wet quarter second time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2005101122577A CN1996147A (en) | 2005-12-28 | 2005-12-28 | TFT array semi-exposure photoetching technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2005101122577A CN1996147A (en) | 2005-12-28 | 2005-12-28 | TFT array semi-exposure photoetching technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1996147A true CN1996147A (en) | 2007-07-11 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005101122577A Pending CN1996147A (en) | 2005-12-28 | 2005-12-28 | TFT array semi-exposure photoetching technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1996147A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517896A (en) * | 2014-12-12 | 2015-04-15 | 深圳市华星光电技术有限公司 | Doping method and manufacturing equipment of array substrate |
| CN105068373A (en) * | 2015-09-11 | 2015-11-18 | 武汉华星光电技术有限公司 | Manufacturing method of TFT (Thin Film Transistor) substrate structure |
| CN105914182A (en) * | 2016-06-15 | 2016-08-31 | 苏州众显电子科技有限公司 | TFT array semi-exposure photo-etching process |
-
2005
- 2005-12-28 CN CNA2005101122577A patent/CN1996147A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517896A (en) * | 2014-12-12 | 2015-04-15 | 深圳市华星光电技术有限公司 | Doping method and manufacturing equipment of array substrate |
| WO2016090689A1 (en) * | 2014-12-12 | 2016-06-16 | 深圳市华星光电技术有限公司 | Doping method and manufacturing equipment for array substrate |
| CN104517896B (en) * | 2014-12-12 | 2017-09-15 | 深圳市华星光电技术有限公司 | The doping method and manufacturing equipment of a kind of array base palte |
| CN105068373A (en) * | 2015-09-11 | 2015-11-18 | 武汉华星光电技术有限公司 | Manufacturing method of TFT (Thin Film Transistor) substrate structure |
| CN105068373B (en) * | 2015-09-11 | 2019-05-31 | 武汉华星光电技术有限公司 | The production method of TFT substrate structure |
| CN105914182A (en) * | 2016-06-15 | 2016-08-31 | 苏州众显电子科技有限公司 | TFT array semi-exposure photo-etching process |
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