CN1992187A - Manufacturing process for array packaging substrate - Google Patents

Manufacturing process for array packaging substrate Download PDF

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Publication number
CN1992187A
CN1992187A CNA2005101352761A CN200510135276A CN1992187A CN 1992187 A CN1992187 A CN 1992187A CN A2005101352761 A CNA2005101352761 A CN A2005101352761A CN 200510135276 A CN200510135276 A CN 200510135276A CN 1992187 A CN1992187 A CN 1992187A
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CN
China
Prior art keywords
chip
colloid
branch
dies
epoxy compound
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2005101352761A
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Chinese (zh)
Inventor
高仁杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CNA2005101352761A priority Critical patent/CN1992187A/en
Publication of CN1992187A publication Critical patent/CN1992187A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

It is a packaging and manufacturing process of array packaging substrate. First, providing a number of packaging unit array packaging substrates, it is used to configure a number of chips in these packaging units. Then, placing a plastic mold in each package unit, the plastic mold has a number of mold-cavities, arranged with branch shape, and the mold-cavity accommodates each chip correspondingly. When the filled plastic is inserted into the filled plastic molds, and after the filled plastic flows into these mold-cavities in branch, it covers the chip of each branch. After the filled plastic solids, the filled plastic mold can be removed, to complete the packaging operation. Based on the above, the time and cost of the manufacturing process is reduced thereby.

Description

The manufacture process of array package base plate
Technical field
The present invention relates to a kind of chip-packaging structure and manufacture process thereof, particularly a kind of chip-packaging structure and manufacture process thereof of using array package base plate.
Background technology
The array package manufacture process is carried out encapsulation step such as chip join, sealing and cutting on large-area circuit base plate.Wherein, the weld pad of chip (bonding pad) can pass through the substrate electric connection of the encapsulation unit of gold thread or Solder Bumps and trellis distribution.Then, chip around coated with the sealing (for example epoxy resin) of hot setting.Treat after the sealing cooling forming that cutting tool separates the substrate of each encapsulation unit along the path of predetermined cuts, to become independently chip-packaging structure.On manufacture process, for the chip-packaging structure of single specification product, adopt the array package manufacture process can increase the speed of encapsulation, the time and the cost of minimizing encapsulation, so industry adopt the array package manufacture process to improve production capacity more.
Fig. 1～Fig. 4 is respectively the schematic diagram of package fabrication process of a kind of array package base plate of prior art.At first, please refer to Fig. 1, most chip 100 correspondences are disposed on the substrate 110 of each encapsulation unit 10, and electrically connect the weld pad (not illustrating) of chip 100 and the joint sheet 112 of substrate 110 with most leads 120.Then, please refer to Fig. 2, dies with epoxy compound 20 is pressed on the substrate 110, and die cavity 22 correspondences of dies with epoxy compound 20 cover on all chips 100, to form a packing space independently.At last, please refer to Fig. 3, the colloid 130 of molten state is filled in the die cavity 22, gas in the die cavity 22 is squeezed and discharges.Colloid 130 after the hot setting breaks away from dies with epoxy compound 20 and during moulding, colloid 130 is with chip 100 and lead 120 sealings.At last, please refer to Fig. 4, cut the substrate 110 of each encapsulation unit 10, to form independently chip-packaging structure 140.
It should be noted that, because the substrate 110 of encapsulation unit 10 is heated and buckling deformation easily, make closely driving fit between the not good substrate 110 of dies with epoxy compound 20 and flatness, cause colloid 130 to flow out via the slit easily and residue between the adjacent substrate 110, influence the quality of manufacture process.In addition, when the gas in the die cavity 22 can't be discharged smoothly, will make residual bubbles and influence the reliability of encapsulation in the colloid 130.
Summary of the invention
Purpose of the present invention is exactly, and a kind of packaging body of array package base plate is provided, and improves at the problem of residual bubble in the colloid, to improve the reliability of encapsulation.
Another object of the present invention is to, a kind of package fabrication process of array package base plate is provided, improve, so that manufacture process high-quality more at the adaptation between dies with epoxy compound and substrate.
The present invention proposes a kind of packaging body of array package base plate, comprises most encapsulation units, most first contacts, most second contacts, a welding cover layer, most chips and most sealings.Each encapsulation unit has the substrate of a first surface, a second surface and at least one line layer.First joint configuration is around the first surface of each encapsulation unit, and second joint configuration is around the second surface of each encapsulation unit.In addition, welding cover layer is covered on the encapsulation unit, and exposes first contact and second contact.Chip configuration and is electrically connected by the line layer of encapsulation unit and first contact, second contact on each encapsulation unit.In addition, the sealing branch-like is arranged on each encapsulation unit, and wherein sealing covers the chip that is positioned in each branch respectively.
Described according to preferred embodiment of the present invention, above-mentioned sealing is for example filled with a dies with epoxy compound, and dies with epoxy compound is provided with most die cavitys, and holds the chip in each branch respectively.In addition, dies with epoxy compound for example also has a total runner, is communicated in the die cavity in each branch, and sealing flows into die cavity in each branch, then curing molding via total runner.In addition, sealing for example is transparent sealing.
The present invention proposes the package fabrication process of another kind of array package base plate.At first, provide an array package base plate with most encapsulation units.Then, most chips of configuration are on these encapsulation units.Then, place a dies with epoxy compound on each encapsulation unit, dies with epoxy compound is provided with most die cavitys, arrange with branch-like, and the die cavity correspondence is held chip.Afterwards, insert a sealing in dies with epoxy compound, and sealing branch flows in after these die cavitys, cover the chip in each branch.At last, solidify sealing, and remove dies with epoxy compound.
Described according to preferred embodiment of the present invention, above-mentioned dies with epoxy compound for example also has a total runner, is communicated in the die cavity in each branch, and sealing flows into die cavity in each branch, then curing molding via total runner.
Described according to preferred embodiment of the present invention, the package fabrication process of above-mentioned array package base plate also can comprise the cutting array package base plate, to form the encapsulation unit that independently separates.
The present invention proposes a kind of chip-packaging structure again, comprises a substrate, most first contacts, most second contacts, a welding cover layer, a chip and sealings.Substrate has a first surface, a second surface and at least one line layer.First joint configuration is in the first surface of substrate, and second joint configuration is in the second surface of substrate, and second contact and first contact electrically connect.In addition, welding cover layer covers first surface and second surface, and exposes first contact and second contact respectively.Chip configuration is in first surface, and electrically connected by line layer and first contact, second contact of substrate, and chip by sealant covers.
Described according to preferred embodiment of the present invention, above-mentioned chip for example electrically connects with the mode of wire bonds and the line layer of substrate.In addition, chip for example electrically connects with the mode of flip-chip encapsulation and the line layer of substrate.In addition, sealing for example is a transparent colloid.
The present invention is because of adopting novel dies with epoxy compound, its have die cavity correspondence that branch arranges cover each chip around, and the adaptation of dies with epoxy compound and substrate is preferable.In addition, when colloid flowed in the die cavity that branch arranges via runner, colloid can be discharged the gas in the die cavity via runner, and can not remain in the colloid, to improve the reliability of encapsulation.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1～Fig. 4 is respectively the schematic diagram of the package fabrication process of a kind of array package base plate of prior art;
Fig. 5～Figure 10 is the flow chart of package fabrication process of a kind of array package base plate of a preferred embodiment of the present invention;
Figure 11 A and Figure 11 B are the vertical view and the end view of chip-packaging structure of the present invention;
Figure 12 is the schematic perspective view of packaging body of a kind of array package base plate of a preferred embodiment of the present invention.
Wherein, Reference numeral
10,30: encapsulation unit 20,40: dies with epoxy compound
22,52,54: die cavity 32: Cutting Road
42,44: colloid runner 46: total runner
46a, 46b: outlet 100: chip
110: substrate 112: joint sheet
120: lead 130: colloid
140: chip-packaging structure 200: chip
210: substrate 212: first surface
214: second surface 216: joint sheet
218: welding cover layer 220: lead
224: the second contacts of 222: the first contacts
226: guide pillar 230: colloid
232,234: cull 240: chip-packaging structure
250: the packaging body of array package base plate
Embodiment
Fig. 5～Figure 10 is the flow chart of package fabrication process of a kind of array package base plate of a preferred embodiment of the present invention.At first, please refer to the profile of the array package base plate of Fig. 5, the first surface 212 of each substrate 210 and the line layer (not illustrating) on the second surface 214 for example are hedged off from the outer world with the insulation characterisitic of welding cover layer (solder mask) 218 or anti-welding green enamelled coating, only expose the chip joint pad 216 that links to each other with the end of line layer in the opening of welding cover layer 218, as the usefulness of chip signal connection.Please refer to Figure 11 B, the also configurable majority of present embodiment first contact 222 and most second contacts 224 are in the edge of each substrate 210, and chip 200 electrically connects first contact 222 and second contact 224 by line layer.Therefore, the signal of chip 200 can be passed to other electronic installation by first contact 222 or second contact 224.
Then, please refer to the chip join manufacture process of Fig. 6, most chips 200 are disposed on the substrate 210 of each encapsulation unit 30, and chip 200 for example is electrically connected on the line layer or joint sheet 216 of substrate 210 with lead 220 hot press.In addition, chip 200 also can flip-chip the projection (not illustrating) of encapsulation be electrically connected to the line layer or the joint sheet 216 of substrate 210, or finish the manufacture process of Fig. 6 with the chip join technology of other technology maturation.
Then, please refer to the sealing manufacture process of Fig. 7, a dies with epoxy compound 40 is covered on the substrate 210 of a plurality of encapsulation units 30.Dies with epoxy compound 40 has two colloid runners 42,44 at least, is communicated in outlet 46a, the 46b of a total runner 46 as the channel of branch-like.Colloid runner 42 is by a plurality of die cavity (only illustrating one) 52 formed branched bottoms of polyphone mutually, and another colloid runner 44 also is to be formed by a plurality of 54 of die cavitys (only illustrating one) of polyphone mutually.Colloid 230 is flowed into respectively in the two more small- bore colloid runners 42,44 by total runner 46 of larger caliber, is filled in each die cavity 52,54 more in regular turn.At the beginning of the colloid 230 that is preheated to melt temperature flowed into each colloid runner 42,44, the air that is adjacent to first die cavity 52,54 of total runner 46 was pushed backward by colloid 230.
Then please refer to Fig. 8, colloid 230 is filled in after first die cavity 52,54, readvances by runner and pushes air in second die cavity (not illustrating), air is pushed rearward is extruded into till last die cavity (not illustrating), last air-out.In the design of die cavity, last die cavity for example is the space that is used for storing cull (as shown in figure 12) 232, does not place chip 200 in last die cavity.Identical design also can be applicable to the least significant end of total runner 46, so that the cull (as shown in figure 12) 234 that does not flow in the colloid runner 42,44 also can be stored in the die cavity (not illustrating) of total runner 46 ends at last.In the manufacture process of Fig. 8, when finishing after colloid 230 fills, dies with epoxy compound 40 is heated to the temperature that colloid solidifies, make colloid produce bond and solidify.
Afterwards, please refer to the manufacture process of Fig. 9, diminish,, so can finish stripping operation smoothly, and dies with epoxy compound 40 is removed the demoulding ability between colloid 230 and the dies with epoxy compound 40 is increased because colloid 230 solidifies viscosity afterwards.
At last, please refer to the cutting manufacture process of Figure 10, the substrate 210 of each encapsulation unit 30 cuts along predetermined Cutting Road 32 (as shown in Figure 9) with cutting tool, and Cutting Road 32 is between adjacent substrate 210.Please refer to Figure 11 B, when first contact 222 of substrate 210 and second contact 224 are desired to be exposed to the side of substrate 210, the outside of the edge of Cutting Road (not illustrating) and first contact 222 and second contact 224 trims, so that the cutter prodigiosin cuts first contact 222 and second contact 224 of stay aligned, form the chip-packaging structure 240 shown in Figure 11 A and Figure 11 B at last.
Figure 11 A and Figure 11 B are the vertical view and the end view of chip-packaging structure of the present invention, and first contact 222 and second contact 224 are arranged in the both sides of substrate 210, and chip 200 and lead 220 are coated by colloid 230, and chip 200 electrically connects with substrate 210.In the present embodiment, first contact 222 and second contact 224 are positioned at the corresponding surface of substrate 210, and can be electrically connected to each other by guide pillar 226 or conduction duct, and soldered ball (not illustrating) or other connected structure alternative are configured in first contact 222 and/or second contact 224, for the usefulness that electrically connects external electronic or storehouse encapsulation.In addition, colloid 230 for example is a transparent colloid, and chip 200 for example is CMOS sensitive chip or Charged Coupled Device.When light was incident to chip 200 by transparent colloid 230, the light signal produced electric signal via photoelectric conversion component, exported with the picture element image at last.As for the material of colloid 230 and the type of chip 200, do not do any restriction in the present embodiment.
Please refer to Figure 12, be the schematic perspective view of the packaging body of a kind of array package base plate of a preferred embodiment of the present invention.Please also refer to Fig. 7, Fig. 8, Fig. 9 and Figure 12, when colloid 230 flowed into each colloid runner 42,44 of square crossings by total runner 46 of strip, colloid 230 coated chip 200 and the curing molding that is positioned in each branch.At last, dies with epoxy compound 40 is removed, can obtain the packaging body 250 of the array package base plate of Figure 12.Because dies with epoxy compound 40 is arranged on each colloid runner 42,44 with the die cavity 52,54 of branch-like, is difficult for residual bubble in the colloid 230, so can improve the reliability of manufacture process.Also owing to the improvement of dies with epoxy compound 40, even substrate 210 is not good because of the temperature distortion flatness, colloid 230 still can flow in each die cavity 52,54 via runner, and is difficult for remaining on the substrate 210 by flowing out in the slit, so can make manufacture process high-quality more.
In sum, the present invention is because of adopting novel dies with epoxy compound, its have die cavity correspondence that branch arranges cover each chip around, and the adaptation of dies with epoxy compound and substrate is preferable.In addition, when colloid flowed in the die cavity that branch arranges via runner, colloid can be discharged the gas in the die cavity via runner, and can not remain in the colloid, to improve the reliability of encapsulation.In addition, the time of manufacture process shortens because of the improvement of the design of die cavity, and then improves production capacity.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.

Claims (3)

1, a kind of package fabrication process of array package base plate is characterized in that, comprising:
One array package base plate with most encapsulation units is provided;
Most chips of configuration are on a described majority encapsulation unit;
Place a dies with epoxy compound on a described majority encapsulation unit, described dies with epoxy compound is provided with most die cavitys, arrange with branch-like, and a described majority die cavity correspondence is held a described majority chip;
Insert colloid in described dies with epoxy compound, and described colloid branch flows in after the described majority die cavity, cover the described majority chip in each branch; And
Solidify described colloid, and remove described dies with epoxy compound.
2, the package fabrication process of array package base plate according to claim 1, it is characterized in that, described dies with epoxy compound also has a total runner, be communicated in the described majority die cavity in each branch, and described sealing flows into a described majority die cavity in each branch, then curing molding via described total runner.
3. the package fabrication process of array package base plate according to claim 1 also comprises the described array package base plate of cutting, to form a described majority encapsulation unit that independently separates.
CNA2005101352761A 2005-12-29 2005-12-29 Manufacturing process for array packaging substrate Pending CN1992187A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNA2005101352761A CN1992187A (en) 2005-12-29 2005-12-29 Manufacturing process for array packaging substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNA2005101352761A CN1992187A (en) 2005-12-29 2005-12-29 Manufacturing process for array packaging substrate

Publications (1)

Publication Number Publication Date
CN1992187A true CN1992187A (en) 2007-07-04

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859690B (en) * 2009-04-10 2012-09-05 日月光半导体制造股份有限公司 Packaging structure, sealing compound module and sealing compound mold for packaging same
CN104409368A (en) * 2014-12-17 2015-03-11 大连泰一精密模具有限公司 Method for packaging semiconductor combination device by packaging mould

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859690B (en) * 2009-04-10 2012-09-05 日月光半导体制造股份有限公司 Packaging structure, sealing compound module and sealing compound mold for packaging same
CN104409368A (en) * 2014-12-17 2015-03-11 大连泰一精密模具有限公司 Method for packaging semiconductor combination device by packaging mould

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