CN1991458A - Liquid crystal display device and driving method thereof - Google Patents

Abstract

The invention discloses a liquid crystal display device, comprising: a liquid crystal panel, having a first data line intersecting with a gate line in a first area of the liquid crystal panel and a second data line intersecting with a gate line in a second area of the liquid crystal panel; a data converter for converting first video data having a first frame frequency into second video data having a second frame frequency higher than the first frame frequency; a backlight unit having a first lamp group of at least two lamps for irradiating light on the sub-areas and a second lamp group including at least two lamps for respectively irradiating light on the sub-areas of the second area; and a driver for following the second video The data drive gate line, the first data line and the second data line are used to drive the first and second lamp groups at the second frame frequency, so that the lamps of the first lamp group are sequentially turned on and synchronized with the lamps of the second lamp group closure.

Description

Liquid crystal display device and driving method thereof

This invention claims the benefit of Korean Patent Application No. 2005-0132789 filed on December 29, 2005 and Korean Patent Application No. 10-2006-0080887 filed on August 25, 2006 , the entire contents of which are hereby incorporated by reference.

technical field

The present invention relates to a liquid crystal display device, and in particular to a liquid crystal display device and a driving method thereof. The invention is suitable for a wide range of uses. In particular, some embodiments are adapted to prevent image retention and/or image blurring.

Background technique

With the continuous development of the information society, the requirements for various display devices are also increasing. In order to meet these requirements, development of flat panel display devices such as liquid crystal display devices (LCDs), plasma display panels (PDPs), and electroluminescence displays (ELDs) has been initiated. In particular, LCDs are lightweight, thin, and have low power consumption. At the same time, LCD can also provide high image quality. Due to these advantages of LCDs, LCDs have replaced CRTs. For example, LCDs are widely used as display devices for TVs, computer monitors, and other types of display devices.

LCDs display images using optical anisotropy and polarization characteristics of liquid crystals. Since the liquid crystal molecules are elongated, the liquid crystal molecules can be aligned in a predetermined direction. Also, the molecular alignment direction of the liquid crystal molecules can be controlled by applying an electric field to the liquid crystal molecules. When the molecular orientation direction of the liquid crystal is controlled, the liquid crystal aligns so that the polarization state of light changes along the chain of the liquid crystal molecules. Thus, image information is displayed by controlling the molecular alignment direction of the liquid crystal molecules.

FIG. 1 is a schematic diagram of a prior art LCD. As shown in Figure 1, the prior art LCD includes a liquid crystal panel 2 for displaying images, a gate driver 4 and a data driver 6 for driving the liquid crystal panel 2, and a timing controller 8 for controlling the gate driver 4 and the data driver 6 . A backlight unit 10 for generating light having a predetermined brightness to be irradiated onto the liquid crystal display panel 2 .

In the liquid crystal display panel 2, a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm are arranged to cross each other. Thin film transistors (TFTs) are formed at intersections of the gate lines GL1 to GLn and the data lines DL1 to DLm to serve as switching elements. The TFTs respond to scan signals applied from the corresponding gate lines GL to switch data voltages supplied from the corresponding data lines DL to the liquid crystal cells Clc connected to the common voltage line Vcom.

The gate driver 4 applies scan signals to the gate lines GL1 to GLn in response to gate control signals generated from the timing controller 8 . The scan signals are applied to the gate lines GL1 to GLn and each scan signal has a pulse of the gate high voltage VGH shifted one by one. The width of the pulse of the high voltage VGH is equal to the width of the period of the horizontal synchronizing signal. In response to the scan signal, the gate lines GL1 to GLn are sequentially enabled once in each frame period, that is, each period of each vertical synchronization signal.

The data driver 6 responds to the data control signal to convert one row of red (R), green (G), blue (B) pixel data into an analog data voltage. The data driver 6 periodically applies a row of data voltages to the data lines DL1 to DLm according to the horizontal synchronization signal.

The timing controller 8 employs vertical/horizontal synchronizing signals (Vsync/Hsync), data enable signals (DE) and The clock signal generates a gate control signal, a data control signal, and a backlight control signal. In addition, the timing controller 8 receives from a system (not shown) video data containing R, G, and B pixel data for each pixel, that is, in each frame, and converts the input pixel data in a row-by-row manner. Provided to the data driver 6.

The backlight unit 10 includes a lamp (not shown), an optical sheet, and a lamp driver for driving the lamp. The lamp generates light having a predetermined brightness in response to a lamp driving signal supplied from the lamp driver and supplies the generated light to the liquid crystal panel 2 . The lamp driver generates a lamp driving voltage for driving the lamp by using a voltage (Vdd) supplied from a power supply (not shown). The lamp driving voltage is supplied to the lamp according to the lamp control signal generated by the timing controller 8 .

The timing controller 8 generates gate control signals, data control signals and backlight control signals. When the gate control signal is applied to the gate driver 4, the gate driver 4 supplies a scan signal having sequential translation pulses of the gate high voltage VGH to the gate lines GL1 to GLn. The gate high voltage VGH of the scan signal sequentially enables the gate lines GL1 to GLn. The TFT connected to the enabled gate line GL is turned on, so that the data voltage on the data line DL corresponding to the TFT is transmitted to the corresponding liquid crystal cell Clc. Therefore, when the scan signal is switched from the gate high voltage VGH to the gate low voltage VGL, the TFT is turned off so that the data line DL is not connected to the corresponding liquid crystal cell Clc. The liquid crystal cell Clc maintains the charged data voltage during the pulse period until another pulse of the gate high voltage VGH is applied in the next frame. The liquid crystal panel 2 is driven through this process, thereby displaying an image on the liquid crystal panel 2 .

Although the data voltage supplied to the liquid crystal cells is maintained for one frame, the lamps of the backlight unit 10 are turned on irrespective of the timing within a frame. When displaying moving images, such hold-type LCDs cannot cope with rapid image changes, and motion blur occurs. Accordingly, unclear images or image sticking deteriorating image quality are generated in the LCD.

In addition, in the related art LCD, liquid crystal molecules in the liquid crystal cell need a predetermined time to align in a direction corresponding to the applied data voltage after the data voltage is applied to the liquid crystal cell (hereinafter referred to as an alignment saturation period). During the alignment saturation period, the liquid crystal cell cannot display pixel data correctly, resulting in motion blur and worse image quality degradation.

Contents of the invention

Accordingly, the present invention is directed to an LCD and a driving method thereof that substantially obviate one or more problems due to limitations and disadvantages of the related art.

An object of the present invention is to provide an LCD that improves image quality by preventing motion blur.

Another object of the present invention is to provide an LCD driving method capable of improving image quality by preventing motion blur.

Another object of the present invention is to provide an LCD capable of improving image quality by preventing image sticking.

Another object of the present invention is to provide an LCD driving method capable of improving image quality by preventing image sticking.

Additional advantages, objects and features of the invention will be set forth in the description which follows and will become apparent to those skilled in the art from the description, or may be learned by practice of the invention. These objectives and other advantages of the present invention can be realized and obtained by the structure specifically pointed out in the description and claims hereof as well as the appended drawings.

To achieve these objects and other advantages, and in accordance with the object of the present invention, as specifically and broadly described herein, there is provided a liquid crystal display device comprising: a liquid crystal panel having The first data line and the second data line intersecting the gate line in the second area of the liquid crystal panel; a data converter for converting the first video data having a first frame frequency into a first video data having a frequency higher than the first frame frequency Second video data at two frame frequencies; a backlight unit having a first lamp group comprising at least two lamps for respectively illuminating light on the sub-regions of the first region and comprising at least two lamps for respectively illuminating light on the sub-regions of the second region a second lamp group of at least two lamps irradiating light; and a driver for driving the gate line, the first data line, and the second data line in accordance with the second video data and for driving the first and second data lines at a second frame frequency. lamp groups, so that the lamps of the first lamp group are sequentially turned on and off in synchronization with the lamps of the second lamp group.

In another aspect, a liquid crystal display device includes: a liquid crystal panel having gate lines and data lines intersecting each other; a backlight unit having a second lamp including two lamps for irradiating light on a first area of the liquid crystal panel by divisions. A first lamp group of at least two lamps of a lamp group and a second lamp group including at least two lamps for irradiating light on the second area of the liquid crystal panel by division; video data for driving the grid lines and data lines and for controlling the first and second lamp groups to be simultaneously driven at a second frame frequency higher than the first frame frequency, so that the lamps of the first lamp group and the lamps of the second lamp group The lights are sequentially turned on and off in sync.

In another aspect, a liquid crystal display device includes: a liquid crystal panel having a first data line intersecting the gate line in a first area of the liquid crystal panel and a second data line intersecting the gate line in a second area of the liquid crystal panel a backlight unit having a first lamp group comprising at least two lamps for respectively irradiating light on subregions of the first region and at least two lamps comprising at least two lamps for respectively irradiating light on subregions of the second region The second lamp group; and a driver, which is used to drive the gate line and the data line to simultaneously write the data voltage of the video data into the liquid crystal unit of the first area and the liquid crystal unit of the second area in a row-by-row manner in each frame, and use In order to drive the first and second lamp groups, at least two lamps of the first lamp group are sequentially turned on or off synchronously with at least two lamps of the second lamp group.

In another aspect, a liquid crystal display device includes: a liquid crystal panel having a first data line crossing the gate line in a first region of the liquid crystal panel and a second data line crossing the gate line in a second region of the liquid crystal panel a backlight unit having a first lamp group comprising at least two lamps for respectively irradiating light on subregions of the first region and at least two lamps comprising at least two lamps for respectively irradiating light on subregions of the second region the second lamp group; and a driver for operating the gate line and the data line to simultaneously write the data voltage of the video data in the liquid crystal unit of the first area and the liquid crystal unit of the second area in a row-by-row manner in each frame, and use to drive the first and second lamp groups, so that the lamps of the first and second lamp groups are turned on or off when the orientation saturation period elapses after the data voltage is written into the liquid crystal cells in the corresponding sub-regions.

In another aspect, a liquid crystal display device includes: a liquid crystal panel having gate lines and data lines intersecting each other; a backlight unit having a second lamp including two lamps for irradiating light on a first area of the liquid crystal panel by divisions. a lamp group and a second lamp group including two lamps for divisionally irradiating light on the second area of the liquid crystal panel; and a driver for driving the gate line and the data line to convert the data voltage of the video data to The liquid crystal cells of the liquid crystal panel are sequentially written in a row-by-row manner, and used to drive the first and second lamp groups to be sequentially turned on or off in synchronization with each other.

In another aspect, a driving method of a liquid crystal display device, the liquid crystal display device has a liquid crystal panel, a first data line intersecting with a gate line on a first region of the liquid crystal panel, second data lines intersecting on the region, the method comprising converting first video data having a first frame frequency to second video data having a second frame frequency higher than the first frame frequency; driving the gate line according to the second video data , first and second data lines; and controlling the first and second lamp groups to simultaneously turn on and off at a second frame frequency, the first lamp group having at least two lamps for the first area and the second lamp group having at least two lamps in the second zone.

In another aspect, a method of driving a liquid crystal display device having a liquid crystal panel in which gate lines and data lines cross each other includes driving the gate lines and the data lines in accordance with video data having a first frame frequency; and controlling the first and second lamp groups to be simultaneously turned on and off at a second frame frequency higher than the first frame frequency, the first lamp group having at least two lamps for the first area of the liquid crystal panel and the second lamp group having At least two lamps for the second area of the liquid crystal panel.

In another aspect, a method for controlling a liquid crystal display device, the liquid crystal display device having a liquid crystal panel, a first data line intersecting a gate line in a first area and a second data line intersecting the gate line in a second area, At least two first lamps partially corresponding to the first area of the liquid crystal panel, and at least two second lamps partially corresponding to the second area of the liquid crystal panel, the method includes driving the gate line and the data line to transfer the data of the video data The voltage is simultaneously written in the liquid crystal cells of the first region and the liquid crystal cells of the second region in a row-by-row manner; and the first lamp and the second lamp are turned on and off simultaneously.

In another aspect, a method for controlling a liquid crystal display device, the liquid crystal display device having a liquid crystal panel, a first data line intersecting a gate line in a first area and a second data line intersecting the gate line in a second area, At least two first lamps partially corresponding to the first area of the liquid crystal panel, and at least two second lamps partially corresponding to the second area of the liquid crystal panel, the method includes driving the gate line and the data line to convert the data voltage of the video data to Write the liquid crystal unit in the first area and the liquid crystal unit in the second area simultaneously in a row-by-row manner; and drive the first and second lamps, so that the lamps of the first and second lamp groups write the liquid crystal on the liquid crystal panel at the data voltage The cells are then simultaneously turned on or off when the orientation saturation period has elapsed.

It is to be understood that both the foregoing general description of the invention and the following detailed explanation are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Description of drawings

The accompanying drawings, which are included to provide a further explanation of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the attached picture:

FIG. 1 is a schematic diagram of a prior art LCD;

FIG. 2 is a schematic diagram of an LCD according to a first embodiment of the present invention;

Fig. 3 is a sequence diagram of each part in Fig. 2;

4 is a schematic diagram of an LCD according to a second embodiment of the present invention;

Fig. 5 is the sequence diagram of each part in Fig. 4;

6 is a schematic diagram of a LOG type LCD according to a third embodiment of the present invention;

7 is a schematic diagram of an LCD according to a fourth embodiment of the present invention;

8 is a schematic diagram of an LCD according to a fifth embodiment of the present invention;

9A and 9B are timing diagrams of various parts in FIG. 8 according to the first driving mode; and

10A and 10B are timing diagrams of each part in FIG. 8 according to the second driving mode.

Detailed ways

Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings for the same or like parts.

FIG. 2 is a schematic diagram of an LCD according to a first embodiment of the present invention. As shown in Figure 2, the LCD includes a liquid crystal panel 102 for displaying images, a gate driver 104 for driving a plurality of gate lines GL1-GL2k in the liquid crystal panel 102, and a plurality of upper data bars formed on the liquid crystal display panel 102 for driving. The first data driver 106A for the lines UDL1-UDLm, and the second data driver 106B for driving the plurality of lower data lines LDL1-LDLm formed on the liquid crystal display panel 102.

The upper data lines UDL1-UDLm are arranged on the upper portion A of the liquid crystal panel 102 and cross the first k gate lines GL1-GLk arranged in a vertical direction. The lower data lines LDL1-LDLm are arranged on the lower portion B of the liquid crystal panel 102 and cross the second k gate lines GL(k+1)-GL2k arranged in a vertical direction. TFTs serving as switching elements are formed at intersections of the gate lines GL1-GL2k and the upper and lower data lines UDL1-UDLm and LDL1-LDLm. The TFTs switch data voltages provided from the corresponding data lines UDL and LDL to the pixel cells Clc connected to the common line Vcom in response to scan signals applied to the corresponding gate lines GL. The liquid crystal cells Clc of the liquid crystal panel 102 transmit light proportional to or inversely proportional to the potential difference of the data voltage and the reference voltage of the data lines UDL and LDL, ie, the common voltage Vcom.

The gate driver 104 generates scan signals for the gate lines GL1-GL2k in response to the gate control signal. The scan signal from the gate driver 104 causes the first k gate lines GL1 to GLk to be sequentially driven once in a half period of a vertical synchronizing signal, and causes the second k gate lines GL(k+1) to GL2k to be sequentially driven once in a half period of a vertical synchronization signal. The vertical sync signal is driven sequentially once in half cycle. For example, while enabling the first gate line GL1 in the upper part A of the liquid crystal panel 102 (that is, one period of a horizontal synchronization signal), the first gate line GL (k+ 1). In another embodiment, during a period of the horizontal synchronization signal that enables the last gate line GLk in the upper part A of the liquid crystal panel 102, the last gate line GL2k in the lower part B of the liquid crystal panel 102 is also enabled. Thus, each of the k scan signals applied to the first k gate lines GL1 to GLk arranged on the upper portion A of the liquid crystal panel 102 has a shifted pulse of the gate high voltage VGH. Also, each of the second k scan signals applied to the second k gate lines GL(k+1) to GL2k arranged on the lower portion B of the liquid crystal panel 102 has a shifted pulse of the gate high voltage VGH. The scan signal supplied to the first k gate lines GL1-GLk arranged in the upper part A of the liquid crystal panel 102 has the same scanning signal as that supplied to the second k gate lines GL(k+1)- The same waveform as the scanning signal of GL2k. The pulse width of the gate high voltage VGH included in the scanning signal is equal to the period of a horizontal synchronizing signal.

In each period of the horizontal synchronous signal, the first data driver 106A responds to the data control signal to convert the R, G, B pixel data corresponding to one row into an analog data voltage, and provides the data voltage of one row to the array of parts A on the liquid crystal panel 102. Upper data lines UDL1-UDLm. That is to say, as long as any one of the gate lines GL1-GLk arranged in part A on the liquid crystal panel 102 is enabled, that is, in each period of a horizontal synchronous signal, the first data driver 106A outputs the data voltage of one row. When one of the gate lines GL1-GLk is enabled by the pulse of the gate high voltage VGH, the TFT connected to the enabled gate line is turned on, so that the data voltage from the corresponding upper data line UDL is transmitted to the corresponding liquid crystal cell Clc. When the scan signal changes from the gate high voltage VGH to the gate low voltage VGL, the turned-on TFT is turned off, so that the corresponding liquid crystal cell Clc is not electrically connected to the corresponding upper data line UDL. The liquid crystal cell Clc is charged with the data voltage provided by the corresponding data line UDL during the turn-on period of the TFT, and the charged data voltage is maintained until the corresponding TFT is turned on again.

Similarly, in each period of the horizontal synchronization signal, the second data driver 106B converts the R, G, B pixel data corresponding to one line into analog data voltages in response to the data control signal, and supplies the data voltages of one line to the lower part of the liquid crystal panel 102 The lower data lines LDL1-LDLm of the B arrangement. As long as any one of the gate lines GL(k+1)-GL2k arranged in the lower part B of the liquid crystal panel 102 is enabled, that is, in each period of a horizontal synchronous signal, the second data driver 106B outputs a row of data voltages. When one of the gate lines GL(k+1)-GL2k is enabled by the pulse of the gate high voltage VGH, the TFT connected to the enabled gate line is turned on, so that the data voltage from the corresponding lower data line LDL is transmitted to the corresponding liquid crystal Unit Clc. When the scan signal changes from the gate high voltage VGH to the gate low voltage VGL, the turned-on TFT is turned off so that the corresponding liquid crystal cell Clc is not electrically connected to the corresponding lower data line LDL. The liquid crystal cell Clc is charged with the data voltage provided by the corresponding data line LDL during the turn-on period of the TFT, and the charged data voltage is maintained until the corresponding TFT is turned on again.

The gate driver 104 and the first and second data drivers 106A and 106B write data voltages to the liquid crystal cells of the liquid crystal panel 102 once every half cycle of the frame cycle, ie, half cycle of the vertical synchronization signal.

Referring to FIG. 2, the LCD includes a timing controller 108 for controlling the gate driver 104, first and second data drivers 106A and 106B, and a data converter 110 for converting the frame frequency of video data to be supplied to the timing controller 108. , and a backlight unit 112 for irradiating light to the liquid crystal panel 102 . The timing controller 108 uses vertical/horizontal synchronous signals (Vsync/Hsync), data enable signals (DE) and The clock signal generates gate control signals and data control signals. In response to the gate control signal, the gate driver 104 enables the first k gate lines GL1-GLk arranged on the upper portion A of the liquid crystal panel 102 to be sequentially driven once in a half period of a vertical synchronous signal, and is forced on the liquid crystal panel 102 The second k lines GL(k+1)-GL2k arranged in the lower part B are sequentially driven in synchronization with the first k gate lines GL1-GLk. In response to the data control signal, the first data driver 106A provides a row of data voltages to the upper data lines UDL1-UDLm when any one of the first k gate lines GL1-GLk is enabled, and the second data driver 106B enables the second k gate lines. Any one of the lines GL(k+1)-GL2k provides a row of data voltages to the lower data lines LDL1-LDLm.

In addition, the timing controller 108 arranges the R, G, B pixel data provided by the external system into row-by-row R, G, B pixel data, and supplies the R, G, B pixel data of one row to the first and second data drivers 106 and 106B. Accordingly, the first and second data drivers 106A and 106B convert one row of R, G, B pixel data into analog data voltages. A row of data voltages converted by the first data driver 106A and a row of data voltages converted by the second data driver 106B are simultaneously supplied to the upper and lower data lines UDL1-UDLm and LDL1-LDLm.

The data converter 110 converts the frame frequency of the frame-based pixel data provided to the timing controller 108 by an external system. The frame-based pixel data supplied to the data converter 110 by the external system has a frame frequency of a first integer (for example, 60 Hz), and the frame-based pixel data output from the data converter 110 has a first integer corresponding to a multiple of the first integer. Two integer frame frequency (eg, 120Hz). In other words, the data converter 110 multiplies the frame frequency of the pixel data from the external system by at least two times. The data converter 110 generates frame-based interpolation pixel data from frame-based pixel data output from an external system, and arranges the frame-based interpolation pixel data between frame-based original pixel data to generate new pixel data, and converts The new pixel data is provided to the timing controller 108 . The timing controller 108 controls the gate driver 104 and the first and second data drivers 106A and 106B to drive the liquid crystal panel 102 at a frame frequency (eg, 120 Hz) at least twice the original frame frequency (eg, 60 Hz).

The backlight unit 112 includes first to eighth lamps 113A to 113H arranged horizontally below the liquid crystal panel 102 . The first to fourth lamps 113A to 113D are arranged to correspond to the upper portion A of the liquid crystal panel 102 , and the fifth to eighth lamps 113E to 113H are arranged to correspond to the lower portion B of the liquid crystal panel 102 . The first to fourth lamps 113A to 113D irradiate light to first to fourth sub-regions A1 to A4 defined by dividing the upper portion A of the liquid crystal panel 102 into four. For example, the first lamp 113A irradiates light to the uppermost sub-area A1 in the upper part A of the liquid crystal panel 102 , and the fourth lamp 113D irradiates light to the lowermost sub-area A4 in the upper part A of the liquid crystal panel 102 . Similarly, the fifth to eighth lamps 113E to 113H irradiate light to four subregions B1 to B4 defined by dividing the lower portion B of the liquid crystal panel 102 into four. For example, the fifth lamp 113E irradiates light to the uppermost subregion B1 in the lower part B of the liquid crystal panel 102 , and the eighth lamp 113H irradiates light to the lowermost subregion B4 in the lower part B of the liquid crystal panel 102 .

The backlight unit 112 includes first to fourth lamp drivers 115A to 115D commonly connected to the timing controller 108 . Each of the first to fourth lamp drivers 115A to 115D simultaneously turns on and off (or turns off and on) one of a plurality of lamps for the upper part A of the liquid crystal panel 102 and a plurality of lamps for the lower part B of the liquid crystal panel 102. One of the lights. In response to the lamp control signal output by the timing controller 108, the first to fourth lamp drivers 115A to 115D sequentially turn on and off once for the upper part of the liquid crystal panel 102 in a half cycle of a vertical synchronous signal in a manner of shifting the turn-on period by a predetermined interval. A's first to fourth lamps 113A to 113D. The shift period between the turn-on periods of the first to fourth lamps 113A to 113D may be at least a period of charging data voltages of the liquid crystal cells Clc on the sub-regions A1 to A4 of the liquid crystal panel 102 corresponding to the lamps 113A to 113D. Meanwhile, the first to fourth lamp drivers 115A to 115D switch the fifth to eighth lamps 113E to 113H for the lower part B of the liquid crystal panel 102 and the fifth lamps 113E to 113H for the upper part A of the liquid crystal panel 102 during a half period of a vertical synchronizing signal. The first to fourth lamps 113A to 113D are turned on and off once together (more specifically, before or after). Accordingly, the fifth to eighth lamps 113E to 113H are also sequentially turned on such that the turn-on period is shifted by a predetermined interval. In other words, the turn-on periods of the lamps 113A to 113D or 113E to 113H of the sub-regions A1 - A4 or B1 to B4 of the liquid crystal panel 102 can be different. Thus, at least one of the lamp driving voltages generated by the second to fourth lamp drivers 115A to 115D has a different duty factor from the others.

In response to the lamp control signal output by the timing controller 108, the first lamp driver 115A simultaneously turns off and on the first lamp for the uppermost sub-area A1 of the upper portion A of the liquid crystal panel 102 in a half-frame period or a half-period of a vertical synchronizing signal. 113A and the fifth lamp 113E for the uppermost subregion B1 of the lower portion B of the liquid crystal panel 102 once. The first lamp driver 115A charges the liquid crystal cells Clc in the uppermost sub-regions A1 and B1 of the upper part A and the lower part B of the liquid crystal panel 102 at the period of the data voltage (the high voltage period of DW113AE in FIG. 3 ) or before and after the high voltage period. Thereafter, the first and fifth lamps 113A and 113E are turned off for a period including a predetermined interval (the low voltage period of LE113AE in FIG. 3 ). On the other hand, during the period in which the liquid crystal cells Clc in the uppermost sub-regions A1 and B1 of the liquid crystal panel 102 maintain the charged data voltage (the low voltage period of DW113AE in FIG. 3 ), the first lamp driver 115A turns on the first and fifth lamps. 113A and 113E predetermined time (the high voltage period of LE113AE in Fig. 3).

In response to the lamp control signal output from the timing controller 108, the second lamp driver 115B simultaneously turns off and on the second lamp for the second uppermost sub-region A2 of the portion A on the liquid crystal panel 102 in a half-frame period or a half-period of a vertical synchronizing signal. The lamp 113B and the sixth lamp 113F for the second uppermost subregion B2 of the lower portion B of the liquid crystal panel 102 once. The second lamp driver 115B charges the liquid crystal cell Clc in the second uppermost sub-regions A2 and B2 of the upper part A and the lower part B of the liquid crystal panel 102 at the period of the data voltage (the high voltage period of DW113BF in FIG. 3 ) or includes the data voltage The periods of predetermined time intervals before and after the charging period (the low voltage period of LE 113BF in FIG. 3 ) turn off the second and sixth lamps 113B and 113F. On the other hand, the liquid crystal cells Clc in the second uppermost sub-regions A2 and B2 of the upper part A and the lower part B of the liquid crystal panel 102 maintain the period of the charged data voltage during which the second lamp driver 115B ( FIG. 3 The high voltage period of LE 113BF) turns on the second and sixth lamps 113B and 113F.

In response to the lamp control signal output from the timing controller 108, the third lamp driver 115C simultaneously turns off and on the second lowermost sub-area A3 for the upper part A of the liquid crystal panel 102 in a half frame period or a half period of a vertical synchronizing signal. Three lamps 113C and a seventh lamp 113G for the second lowermost subregion B3 of the lower portion B of the liquid crystal panel 102 once. The third lamp driver 115C charges the period of the liquid crystal cell Clc in the second lowermost sub-regions A3 and B3 of the upper part A and the lower part B of the liquid crystal panel 102 at the data voltage (the high voltage period of DW113CG in FIG. 3 ) or includes the data voltage Periods of predetermined time intervals before and after the charging period (the low voltage period of LE 113CG in FIG. 3 ) turn off the third and seventh lamps 113C and 113G. On the other hand, during the period in which the liquid crystal cells Clc in the second lowermost sub-regions A3 and B3 of the liquid crystal panel 102 maintain the charged data voltage, the third lamp driver 115C turns on the third and seventh lamps 113C and 113G for a predetermined time ( Figure 3 for the high voltage cycle of the LE113CG).

In response to the lamp control signal output from the timing controller 108, the fourth lamp driver 115D simultaneously turns off and on the fourth lamp for the lowermost sub-area A4 of the upper portion A of the liquid crystal panel 102 in a half frame period or a half period of a vertical synchronizing signal. 113D and the eighth lamp 113H for the lowermost sub-area B4 of the lower portion B of the liquid crystal panel 102 once. The fourth lamp driver 115D charges the liquid crystal cells Clc in the lowermost sub-regions A4 and B4 of the upper part A and the lower part B of the liquid crystal panel 102 during the data voltage charging cycle (the high voltage cycle of DW113DH in FIG. 3 ) or includes the data voltage charging cycle The period before and after the predetermined time interval (the low voltage period of LE113DH in FIG. 3 ) turns off the fourth and eighth lamps 113D and 113H. On the other hand, during the period in which the liquid crystal cells Clc in the lowermost sub-regions A4 and B4 of the liquid crystal panel 102 maintain the charged data voltage (the low voltage period of DW113DH in FIG. 3 ), the fourth lamp driver 115D turns on the fourth and eighth lamp drivers. The lamps 113D and 113H are maintained for a predetermined time (high voltage period of LE113DH of FIG. 3 ).

It can be seen from the timing diagram of FIG. 3 that the timing controller 108 controls the first to fourth lamp drivers 115A to 115D so that the first to fourth lamps 113A to 113D for the upper part A of the liquid crystal panel 102 and the first to fourth lamps 113A to 113D for the upper part A of the liquid crystal panel The fifth to eighth lamps 113F to 113H of the lower part B of 102 are sequentially turned on and off together, so as to be synchronized at each converted frame period, and at the same time, the data voltage is simultaneously written in the upper part A of the liquid crystal panel 102 and the lower part of the liquid crystal panel 102 Liquid crystal cell Clc in Part B. On the other hand, on the liquid crystal panel 102, video data and black level data are displayed at a frame frequency (second frame frequency, for example, 120 Hz) twice that of video data generated from an external system (for example, a first frame frequency of 60 Hz). ) are displayed alternately once. Therefore, an LCD according to an embodiment of the present invention can quickly display video data on a liquid crystal panel. Thus, no motion blur phenomenon occurs when displaying moving pictures. In addition, providing charging data voltages to the two liquid crystal panels at the same time can also prevent unclear images or image retention, so that images can appear quickly. Therefore, according to the embodiment of the present invention, the LCD can display higher quality images.

In addition, since a plurality of lamps for upper subregions of the liquid crystal panel 102 and a plurality of lamps for lower subregions of the liquid crystal panel can be turned on and off by a single lamp driver, circuits for driving the lamps can be simplified.

FIG. 4 is a schematic diagram of an LCD according to a second embodiment of the present invention. Referring to FIG. 4 , the LCD includes: a first gate driver 204A for driving a plurality of left gate lines LGL1-LGL2k arranged on the left part of the liquid crystal panel 202; A second gate driver 204B for the lines RGL1-RGL2k, and a data driver 206 for driving a plurality of data lines DL1-DL2j provided on the liquid crystal panel.

The left gate lines LGL1-LGL2k are arranged on the left portion C of the liquid crystal panel 202 and cross the first j data lines DL1-DLj arranged in the horizontal direction. The right gate lines RGL1-RGL2k are arranged in the right part D of the liquid crystal panel 202 and cross the second j data lines DL(j+1)-DL2j arranged in the horizontal direction. TFTs serving as switching elements are formed at intersections of the data lines DL1-DL2j and the left and right gate lines LGL1-LGL2k, RGL1-RGL2k. The TFTs respond to scan signals supplied from corresponding gate lines GL to supply data voltages supplied from corresponding data lines to liquid crystal cells Clc connected to the common voltage line Vcom. The liquid crystal cells Clc of the liquid crystal panel 202 transmit light that is proportional or inversely proportional to the potential difference between the data voltage and the reference voltage of the data line DL, that is, the common voltage Vcom.

In each period of a vertical synchronization signal, that is, in each frame period, the first gate driver 204A generates scan signals for the left gate lines LGL1-LGL2k in response to the gate control signal. The scan signal from the first gate driver 204A sequentially enables the first 2k gate lines LGL1 to LGL2k once in a period of a vertical sync signal. The first 2k scan signals are exclusively provided to the first 2k left gate lines LGL1-LGL2k arranged in the left portion C of the liquid crystal panel 202 as shifted pulses of the gate high voltage VGH. The pulse width of the gate high voltage VGH included in the scanning signal is equal to the period of a horizontal synchronizing signal.

In each period of a vertical synchronization signal, that is, in each frame period, the second gate driver 204B generates scanning signals for the right gate lines RGL1-RGL2k in response to the gate control signal. The scan signal from the second gate driver 204B sequentially enables the second 2k gate lines RGL1 to RGL2k once in a period of a vertical sync signal. The second 2k scan signals generated by the second gate driver 204B have the same waveform as the first 2k scan signals generated by the first gate driver 204A. Accordingly, the right gate lines RGL1 - RGL2 k disposed at the right portion D of the liquid crystal panel 202 are sequentially enabled or disabled together with the left gate line LGL disposed at the left portion of the liquid crystal panel 202 .

The data driver 206 converts one row of R, G, B pixel data into analog data voltages in response to the data control signal in each period of the horizontal synchronization signal, and supplies one row of data voltages to the data lines DL1-DL2j arranged on the liquid crystal panel 202 . When 2k pairs of left and right gate lines LGL1-LGL2k and RGL1-RGL2k are sequentially enabled in pairs, that is, in each period of a horizontal synchronization signal, the data driver 206 outputs data voltages for one row. If a pair of gate lines among 2k pairs of left and right gate lines LGL1-LGL2k and RGL1-RGL2k is enabled by a pulse of gate high voltage VGH, the TFTs connected to the enabled left and right gate lines LGL and RGL are turned on, Thus, the data voltage from the corresponding data line DL is transmitted to the corresponding liquid crystal cell Clc. When a pair of scan signals changes from the gate high voltage VGH to the gate low voltage VGL, the turned-on TFT is turned off, so that the corresponding liquid crystal cell Clc is not electrically connected to the corresponding data line DL. The liquid crystal cell Clc is charged with the data voltage provided by the corresponding data line DL during the turn-on period of the TFT, and the charged data voltage is maintained until the corresponding TFT is turned on again.

The gate driver 104 and the first and second data drivers 106A and 106B write data voltages to the liquid crystal cells Clc of the liquid crystal panel 102 once in a frame period, that is, every period of a vertical synchronization signal.

Referring to FIG. 4 , the LCD includes a timing controller 208 for controlling first and second gate drivers 204A and 204B, a data driver 206 , and a backlight unit 210 for irradiating light to a liquid crystal panel 202 . The timing controller 208 uses vertical/horizontal synchronous signals (Vsync/Hsync), data enable signals (DE) and The clock signal generates a gate control signal for controlling the first and second gate drivers 204A and 204B and a data control signal for the data driver 206 . In response to a gate control signal generated from the timing controller 208, the first and second gate drivers 204A and 204B make 2k pairs of gate lines LGL1-LGL2k and RGL1-RGL2k arranged on the left part C and the right part D of the liquid crystal panel 202 in A period of a vertical synchronization signal, that is, a frame period is sequentially driven once. In response to the data control signal, the data driver 206 supplies a row of data voltages to the data lines DL1-DL2j in a row-by-row manner when any pair of the 2k pairs of gate lines LGL1-LGL2k and RGL1-RGL2k is enabled.

In addition, the timing controller 208 arranges the R, G, B pixel data supplied row by row from an external system, and supplies the R, G, B pixel data of one row to the data driver 206 at each cycle of the horizontal synchronization signal. The data driver 206 converts one row of R, G, B pixel data into an analog data voltage. The data voltages for one row converted by the data driver 206 are simultaneously supplied to the data lines DL1-DL2j.

The backlight unit 210 includes first to eighth lamps 213A to 213H arranged horizontally below the liquid crystal panel 202 . The first to fourth lamps 213A to 213D are arranged to correspond to the upper portion A of the liquid crystal panel 202 , and the fifth to eighth lamps 213E to 213H are arranged to correspond to the lower portion B of the liquid crystal panel 202 . The first to fourth lamps 213A to 213D respectively irradiate light to first to fourth sub-regions A1 to A4 defined by dividing the upper portion A of the liquid crystal panel 202 into four. For example, the first lamp 213A irradiates light to the uppermost sub-area A1 in the upper part A of the liquid crystal panel 202 , and the fourth lamp 213D irradiates light to the lowermost sub-area A4 in the upper part A of the liquid crystal panel 202 . Similarly, the fifth to eighth lamps 213E to 213H respectively irradiate light to four subregions B1 to B4 defined by dividing into four in the lower portion B of the liquid crystal panel 202 . For example, the fifth lamp 213E irradiates light to the uppermost subregion B1 in the lower part B of the liquid crystal panel 202 , and the eighth lamp 213H irradiates light to the lowermost subregion B4 in the lower part B of the liquid crystal panel 202 .

The backlight unit 210 includes first to fourth lamp drivers 215A to 215D commonly connected to the timing controller 208 . Each of the first to fourth lamp drivers 215A to 215D simultaneously turns on and off (more specifically, before or after) one of the plurality of lamps for the upper part A of the liquid crystal panel 202 and for the lower part of the liquid crystal panel 202. One of B's lights twice. In response to the lamp control signal output by the timing controller 208, the first to fourth lamp drivers 215A to 215D sequentially turn on and off the first to fourth lamps for the upper part A of the liquid crystal panel 202 in a vertical synchronous signal period in a manner of shifting the turn-on period by a predetermined interval. The first to fourth lamps 213A to 213D once. The shift period between the turn-on periods of the lamps may be a period in which the liquid crystal cell Clc on one of the sub-regions A1 to A4 corresponding to the lamps 213A to 213D charges the data voltage. At the same time, the first to fourth lamp drivers 215A to 215D turn on and off the fifth to eighth lamps 213E to 213H for the lower portion B of the liquid crystal panel 202 together with the first to fourth lamps 213A to 213D. Accordingly, the fifth to eighth lamps 213E to 213H are sequentially turned on such that the turn-on period is shifted by a predetermined interval in a half period of the vertical synchronization signal, that is, a half frame period. In other words, the turn-on periods of the lamps 213A to 213D or 213E to 213H of the sub-regions A1-A4 or B1-B4 can be different. Thus, at least one of the lamp driving voltages generated by the first to fourth lamp drivers 215A to 215D has a different duty factor from the others.

In response to the lamp control signal output by the timing controller 208, the first lamp driver 215A simultaneously turns on and off the first lamp driver 215A for the uppermost sub-region A1 of the upper part A of the liquid crystal panel 202 in half a cycle of the vertical synchronization signal, that is, a half frame period. The lamp 213A and the fifth lamp 213E for the uppermost subregion B1 of the lower portion B of the liquid crystal panel 202 once. The first lamp driver 215A charges the liquid crystal cells Clc of the uppermost sub-regions A1 and B1 of the uppermost sub-regions A1 and B1 of the liquid crystal panel 202 at the data voltage (the high voltage period of DW213A and DW213E in FIG. 5 ) or is included in the data voltage charging period. The first and fifth lamps 213A and 213E are turned off for periods of predetermined intervals before and after (the low voltage period of LE213AE in FIG. 5). On the other hand, when the liquid crystal cells Clc in the uppermost sub-regions A1 and B1 of the liquid crystal panel 202 maintain the charged data voltage period (the low voltage period of DW213A and DW213E in FIG. 5), the first lamp driver 215A turns on the first and fifth Lamps 213A and 213E are scheduled for a predetermined time (high voltage period of LE213AE in FIG. 5).

In response to the lamp control signal output from the timing controller 208, the second lamp driver 215B simultaneously turns off and on the second uppermost sub-area A2 of the upper portion A of the liquid crystal panel 202 in half a cycle of the vertical synchronizing signal, that is, a half frame period. The second lamp 213B and the sixth lamp 213F for the second uppermost sub-area B2 of the lower part B of the liquid crystal panel 202 once. The second lamp driver 215B charges the liquid crystal cells Clc in the second uppermost sub-regions A2 and B2 of the upper part A and the lower part B of the liquid crystal panel 202 during the data voltage period (the high voltage period of DW213B and DW213F in FIG. 5 ) or includes The period of a predetermined time interval before and after the data voltage charging period (low voltage period of LE213BF in FIG. 5) turns off the second and sixth lamps 213B and 213F. On the other hand, during the period in which the liquid crystal cells Clc of the second uppermost sub-regions A2 and B2 of the upper part A and the lower part B of the liquid crystal panel 202 maintain the charged data voltage, the second lamp driver 215B turns on the second and second lamps. Six lamps 213B and 213F for a predetermined time (high voltage period of LE213BF of FIG. 5).

In response to the lamp control signal output from the timing controller 208, the third lamp driver 215C simultaneously turns off and on the lamps for the second lowermost sub-area A3 of the upper part A of the liquid crystal panel 202 in half a cycle of the vertical synchronizing signal, that is, a half frame period. The third lamp 213C and the seventh lamp 213G for the second lowermost subregion B3 of the lower portion B of the liquid crystal panel 202 once. The third lamp driver 215C charges the liquid crystal cells Clc in the second lowermost sub-regions A3 and B3 of the upper part A and the lower part B of the liquid crystal panel 202 during the data voltage period (the high voltage period of DW213C and DW213G in FIG. 5 ) or includes Periods of predetermined time intervals before and after the data voltage charging period (the low voltage period of LE213CG in FIG. 5 ) turn off the third and seventh lamps 213C and 213G. On the other hand, during a period in which the liquid crystal cells Clc of the second lowermost sub-regions A3 and B3 of the liquid crystal panel 202 maintain the charged data voltage, the third lamp driver 215C turns on the third and seventh lamps 213C and 213G for a predetermined time. (High voltage cycle of LE213CG in Figure 5).

In response to the lamp control signal output from the timing controller 208, the fourth lamp driver 215D simultaneously turns off and on the fourth lamp driver 215D for the lowermost sub-area A4 of the upper part A of the liquid crystal panel 202 at the half cycle of the vertical synchronizing signal, that is, the half frame period. The lamp 213D and the eighth lamp 213H for the lowermost subregion B4 of the lower portion B of the liquid crystal panel 202 once. The fourth lamp driver 215D charges the period of the liquid crystal cell Clc in the lowermost sub-regions A4 and B4 of the upper part A and the lower part B of the liquid crystal panel 202 at the data voltage (the high voltage period of DW213D and DW213H in FIG. 5 ) or includes the data voltage Periods of predetermined time intervals before and after the charging period (the low voltage period of LE213DH in FIG. 5 ) turn off the fourth and eighth lamps 213D and 213H. On the other hand, during the period during which the liquid crystal cells Clc in the lowermost sub-regions A4 and B4 of the liquid crystal panel 202 maintain the charged data voltage (low voltage period of DW213D and DW213H in FIG. 5 ), the fourth lamp driver 215D turns on the fourth lamp driver 215D. And the eighth lamps 213D and 213H are maintained for a predetermined time (high voltage period of LE213DH of FIG. 5 ).

It can be seen from the timing diagram of FIG. 5 that the first to fourth lamp drivers 215A to 215D are used for liquid crystal in a manner in which the first to fourth lamps 213A to 213D are synchronized with the fifth to eighth lamps 213F to 213H in each frame period. The first to fourth lamps 213A to 213D of the upper part A of the panel 202 and the fifth to eighth lamps 213E to 213H for the lower part B of the liquid crystal panel 202 are sequentially turned on and off twice together while sequentially writing multiple A row in a row of liquid crystal cells. Thus, video data and black level data alternate on the liquid crystal panel 202 at a frame frequency (second frame frequency, for example, 120 Hz) twice that of video data generated from an external system (for example, a first frame frequency of 60 Hz). displayed twice. Therefore, an LCD according to an embodiment of the present invention can quickly display video data on a liquid crystal panel. Thus, no motion blur phenomenon occurs when displaying moving pictures.

In addition, a plurality of lamps for a plurality of subregions in the upper part of the liquid crystal panel 202 and a plurality of lamps for a plurality of subregions in a lower part of the liquid crystal panel can be turned on and off by a single lamp driver. Therefore, the circuit for driving the lamp can be simplified.

In an LCD according to an embodiment of the present invention, gate lines for enabling one row of TFTs are divided into left and right gate lines so that the left and right gate lines can be driven respectively. Therefore, the propagation delay of the scanning signal on the gate line can be reduced. Therefore, an LCD according to an embodiment of the present invention can respond to a rapidly changing image, thereby improving image quality.

FIG. 6 is a schematic diagram of a line-on-glass (LOG) type LCD according to a third embodiment of the present invention. 6, the LCD includes: a liquid crystal panel 302 for displaying images; a plurality of data carrier tape packages (TCP) 318a to 318c connected between the liquid crystal panel 302 and a data printed circuit board (PCB) 320, on the liquid crystal panel 302 A plurality of gate TCPs 316a to 316d provided on one side and the other side, data driver ICs 306a to 306c mounted on the data TCPs 318a to 318c, and a plurality of data driver ICs 304a to 304d mounted on the gates TCP316a to 316d. The liquid crystal panel 302 includes a lower substrate 311 , an upper substrate 313 , and a liquid crystal (not shown) sandwiched between the lower substrate 311 and the upper substrate 313 . The lower substrate 311 and the upper substrate 313 are transparent insulating substrates. Among the plurality of gates TCP 316 a and 316 d , first and second gates TCP 316 a and 316 b are disposed at one side of the liquid crystal panel 302 . The first LOG type signal line group 314a is provided on the lower substrate 311 to connect in series the first and second gate driving ICs 304a and 304b mounted on the first and second gate TCPs 316a and 316b. In addition, third and fourth gates TCP 316c and 316d are disposed on the other side of the liquid crystal panel 302 . The second LOG type signal line group 314b is disposed on the lower substrate 311 to connect in series the third and fourth gate driver ICs 304c and 304d mounted on the third and fourth gate TCPs 316c and 316d.

The liquid crystal panel 302 includes a plurality of left gate lines LGL1-LGL2k vertically arranged on the left part C of the liquid crystal panel 302 and a plurality of right gate lines RGL1-RGL2k vertically arranged on the right part D of the liquid crystal panel 302. The left gate lines LGL1-LGL2k intersect with the first j data lines DL1-DLj provided on the left part C of the liquid crystal panel 302, and the right gate lines RGL1-RGL2k intersect with the second j data lines provided on the right part D of the liquid crystal panel 302. The data lines DL1(j+1)-DL2j cross. The left gate lines LGL1-LGL2k are sequentially driven by the first and second gate driver ICs 304a and 304b, and the right gate lines RGL1-LGL1- RGL2k. When a pair of gate lines among the left gate line LGL and the right gate line RGL is enabled, the data lines DL1-DL2j are all charged with a data voltage. The gate lines LGL1-LGL2k and RGL1-RGL2k and the data lines DL1-DL2j arranged on the liquid crystal panel 302 are driven in the same manner as shown in FIG. That is, the liquid crystal panel 302 , first to fourth gate driver ICs 304 a to 304 d and first to third data driver ICs 306 a to 306 c connected to the liquid crystal panel 302 are driven in the same manner as shown in FIG. 4 . Therefore, detailed descriptions of the liquid crystal panel 302, the first to fourth gate driver ICs 304a to 304d, and the first to third data driver ICs 306a to 306c are omitted below.

The LOG type LCD of FIG. 6 includes first to eighth lamps 213A to 213H horizontally arranged below the liquid crystal panel 302 , a timing controller 308 and a lamp driver 215 mounted on a data PCB 320 . The first to fourth lamps 213A to 213D are arranged to correspond to the upper portion A of the liquid crystal panel 302 , and the fifth to eighth lamps 213E to 213H are arranged to correspond to the lower portion B of the liquid crystal panel 302 . The first to fourth lamps 213A to 213D irradiate light to sub-regions defined by dividing the upper portion A of the liquid crystal panel 302 into four, respectively. For example, the first lamp 213A irradiates light to the uppermost sub-area A1 in the upper part A of the liquid crystal panel 302 , and the fourth lamp 213D irradiates light to the lowermost sub-area A4 in the upper part A of the liquid crystal panel 302 . Similarly, the fifth to eighth lamps 213E to 213H respectively irradiate light to sub-regions defined by dividing the lower part B of the liquid crystal panel 302 into four parts. For example, the fifth lamp 213E irradiates light to the uppermost subregion B1 in the lower part B of the liquid crystal panel 302 , and the eighth lamp 213H irradiates light to the lowermost subregion B4 in the lower part B of the liquid crystal panel 302 .

In response to the lamp control signal output by the timing controller 308, the lamp driver 215 simultaneously and sequentially turns on and off the lamps 213A to 213D for the upper portion A of the liquid crystal panel 302 and the lamps for The lamps 213E to 213H of the lower part B of the liquid crystal panel 302 are turned on once. The first to fourth lamps 213A to 213D are sequentially turned off and on in such a manner that their turn-on periods are shifted by predetermined intervals. The shift period between the turn-on periods of the first to fourth lamps 213A to 213D corresponds to the period in which the liquid crystal cell Clc in the sub-region is charged with the data voltage. The fifth to eighth lamps 213E to 213H for the lower portion B of the liquid crystal panel 302 are turned on and off simultaneously with the first to fourth lamps 213A to 213D, respectively. Therefore, the fifth to eighth lamps 213E to 213H are sequentially turned on once within a half period of the vertical signal, that is, a half frame period, so that their turn-on periods are shifted by a predetermined interval. In order to drive the first to eighth lamps 213A to 213H in the above-described manner, the lamp driver 215 includes first to fourth lamp drivers 215A to 215D shown in FIG. 4 . Since the lamp driver 215 and the first to eighth lamps 213A to 213H are similar to the detailed description of FIG. 4 , a detailed description about the lamp driver is omitted.

It can be seen from the timing diagram of FIG. 5 that the timing controller 308 controls the gate driver ICs 304a to 304d and the data drivers 306a to 306c to sequentially write data to the liquid crystal cells Clc of the liquid crystal panel 302 one row at a time in each frame, and The lamp driver 215 is controlled to turn on and off the first to eighth lamps 213A to 213H twice. Since the timing controller 308 is similar to the detailed description of FIG. 4 , the detailed description of the timing controller 308 is omitted here.

It can be seen from the timing diagram of FIG. 5 that in the LOG type LCD of FIG. The eighth lamps 213E to 213H are sequentially turned on and off twice for the first to fourth lamps 213A to 213D for the upper part A of the liquid crystal panel 302 and the fifth to eighth lamps for the lower part B of the liquid crystal panel 302 213E to 213D. That is, on the liquid crystal panel 302, the video data and black level data. Therefore, the LOG type LCD according to the embodiment of the present invention can quickly respond to video data. Thereby, no motion blur phenomenon occurs when a moving image is displayed.

In addition, the lamps for the upper sub-area and the lamps for the lower sub-area are turned on and off by the same lamp driver. Therefore, the circuit for driving the lamp can be simplified.

In the LOG type LCD according to the third embodiment, a gate line for enabling a row of TFTs divides the left gate line and the right gate line so that the left gate line and the right gate line are respectively driven. Therefore, the propagation delay time of the scan signal on the gate line can be reduced. Therefore, the LOG type LCD according to the embodiment of the present invention can respond to a rapidly changing image, thereby improving image quality.

FIG. 7 is a schematic diagram of an LCD according to a fourth embodiment of the present invention. Referring to FIG. 7, an LCD according to a fourth embodiment of the present invention includes a gate driver 404 for driving a plurality of gate lines GL1-GL2k arranged on a liquid crystal panel 402; - Data Driver 406 for DL2j.

The gate lines GL1-GL2k are arranged on the liquid crystal panel 402 and cross the data lines DL1-DL2j arranged in the horizontal direction. TFTs serving as switching elements are formed at intersections of the data lines DL1-DL2j and the gate lines GL1-GL2k. The TFTs switch data voltages supplied from the corresponding data lines DL to the liquid crystal cells Clc connected to the common voltage line Vcom in response to scan signals applied from the corresponding gate lines GL. The liquid crystal cells Clc of the liquid crystal panel 402 transmit light proportional to the potential difference between the data voltage of the data line DL and the reference voltage, that is, the common voltage Vcom.

In each period of a vertical synchronous signal, that is, in each frame period, the gate driver 404 generates scanning signals provided to the gate lines GL1-GL2k in response to the gate control signal. The scanning signal from the gate driver 404 causes the 2k gate lines GL1 to GL2k to be sequentially driven once in a period of a vertical synchronizing signal. For this, 2k scan signals supplied to the 2k gate lines GL1-GL2k arranged on the liquid crystal panel 402 have translation pulses of the gate high voltage VGH differently from each other. The width of the pulse of the gate high voltage VGH included in the scanning signal is equal to one horizontal step signal period.

In each cycle of the horizontal synchronization signal, the data driver 406 converts the R, G, B pixel data corresponding to one row into analog data voltages in response to the data control signal, and supplies the data voltages of one row to the data lines arranged on the liquid crystal panel 402 DL1-DL2j. Specifically, as long as any one of the 2k gate lines GL1-GL2k is enabled, that is, in each period of a horizontal synchronization signal, the data driver 406 outputs a row of data voltages. When one of the gate lines GL1-GL2k is enabled by the pulse of the gate high voltage VGH, the TFT connected to the enabled gate line GL is turned on, so that the data voltage from the corresponding data line DL is transmitted to the corresponding liquid crystal cell Clc. When the scan signal changes from the gate high voltage VGH to the gate low voltage VGL, the turned-on TFT is turned off, so that the corresponding liquid crystal cell Clc is not electrically connected to the corresponding data line DL. The liquid crystal cell Clc is charged with the data voltage provided by the corresponding data line DL during the turn-on period of the TFT, and the charged data voltage is maintained until the corresponding TFT is turned on again.

The gate driver 404 and the data driver 406 write data voltages to the liquid crystal cells of the liquid crystal panel 402 once in each frame period, that is, each period of the vertical synchronization signal.

Referring to FIG. 7 , the LCD includes a timing controller 408 for controlling a gate driver 404 , a data driver 406 , and a backlight unit 410 for irradiating light to a liquid crystal panel 402 . The timing controller 408 uses vertical/horizontal synchronous signals (Vsync/Hsync), data enable signals (DE) and The clock signal generates a gate control signal for controlling the gate driver 404 and a data control signal for controlling the data driver 406 . The gate driver 404 sequentially drives 2k gate lines GL1-GL2k arranged on the liquid crystal panel 402 in response to the gate control signal generated by the timing controller 408 . In response to a data control signal generated by the timing controller 408, the data driver 406 supplies data voltages for one row to the data lines DL1-DL2j row by row.

The timing controller 408 arranges the R, G, B pixel data provided by the external system in a row-by-row manner, and provides a row of R, G, B pixel data to the data driver 406 in each cycle of the horizontal synchronization signal. Therefore, the data driver 406 converts one row of R, G, B pixel data into an analog data voltage. The data voltages of one row converted by the data driver 406 are simultaneously supplied to the data lines DL1-DL2j.

Similar to the backlight unit 210 of FIG. 4 , the backlight unit 410 includes first to eighth lamps 213A to 213H and first to fourth lamp drivers 215A to 215D horizontally arranged under the liquid crystal panel 402 . The first to fourth lamps 213A to 213D are arranged to correspond to the upper portion A of the liquid crystal panel 402 , and the fifth to eighth lamps 213E to 213H are arranged to correspond to the lower portion B of the liquid crystal panel 402 . The first to fourth lamps 213A to 213D respectively irradiate light to first to fourth subregions defined by dividing the upper portion A of the liquid crystal panel 402 into four. For example, the first lamp 213A irradiates light to the uppermost sub-area A1 in the upper part A of the liquid crystal panel 402 , and the fourth lamp 213D irradiates light to the lowermost sub-area A4 in the upper part A of the liquid crystal panel 402 . Similarly, the fifth to eighth lamps 213E to 213H respectively irradiate light to four sub-regions defined by dividing into four in the lower portion B of the liquid crystal panel 402 . For example, the fifth lamp 213E irradiates light to the uppermost subregion B1 in the lower part B of the liquid crystal panel 402 , and the eighth lamp 213H irradiates light to the lowermost subregion B4 in the lower part B of the liquid crystal panel 402 .

In response to the lamp control signal output by the timing controller 408, the first to fourth lamp drivers 215A to 215D will be used for the first to fourth lamps 213A to 213D of the upper part A of the liquid crystal panel 402 in a cycle of a vertical synchronization signal. Together with the fifth to eighth lamps 213E to 213H for the lower portion B of the liquid crystal panel 402 are simultaneously and sequentially turned on and off twice. In response to the lamp control signal output by the timing controller 408, the first to fourth lamp drivers 215A to 215D are sequentially turned on and off in the manner of shifting the turn-on period by a predetermined interval in each half period of the vertical synchronization signal, that is, each half frame period. Once the first to fourth lamps 213A to 213D. The shift period between the turn-on periods of the first to fourth lamps 213A to 213D may be a period in which the liquid crystal cell Clc on one of the sub-regions A1 to A4 of the liquid crystal panel 402 charges the data voltage. At the same time, the fifth to eighth lamps 213E to 213H for the lower portion B of the liquid crystal panel 202 are turned on and off together with the first to fourth lamps 213A to 213D, respectively. Therefore, the fifth to eighth lamps 213E to 213H are sequentially turned on once in a half period of the vertical synchronization signal, ie, a half frame period, in such a manner that the turn-on period is sequentially shifted by a predetermined interval. In other words, the turn-on periods of the lamps 213A to 213D or 213E to 213H of the sub-regions A1 - A4 or B1 - B4 of the liquid crystal panel 402 can be different. Thus, at least one of the lamp driving voltages generated by the first to fourth lamp drivers 215A to 215D has a different duty factor from the others. Since the first to fourth lamp drivers 215A to 215D and the first to eighth lamps 213A to 213H are similar to the description of FIG. 4 , detailed descriptions thereof are omitted.

As can be seen from the timing diagram of FIG. 5, the LOG type LCD of FIG. The lamps 213A to 213D sequentially turn on and off the first to fourth lamps 213A to 213D and the fifth to eighth lamps 213E to 213H in synchronization with the fifth to eighth lamps 213E to 213H for the lower portion B of the liquid crystal panel 402 twice. That is, video data and black level data are displayed on the liquid crystal panel 202 at a frame frequency (second frame frequency, for example, 120 Hz) twice the frame frequency (for example, a first frame frequency of 60 Hz) of video data generated from an external system. ) are displayed twice alternately. Therefore, the LOG type LCD according to the embodiment of the present invention can quickly respond to video data. Thus, no motion blur phenomenon occurs when displaying moving images. In addition, alternately displaying video data and black level data twice on the liquid crystal panel also prevents unclear images or image sticking, thereby expressing images quickly. Therefore, the LCD according to the embodiment of the present invention improves image quality while minimizing reduction in luminance.

In addition, the lamps for the upper sub-region of the liquid crystal panel and the lamps for the lower sub-region of the liquid crystal panel are turned on and off by the same data driver. Therefore, the circuit for driving the lamp can be simplified.

FIG. 8 is a schematic diagram of an LCD according to a fifth embodiment of the present invention. The LCD according to the fifth embodiment of the present invention is similar to the LCD shown in FIG. 2 except that there is no data converter 110 but a timing controller 108 directly receives a TV signal from a video card such as a computer system or a television receiver. The video data of the decoding module system (not shown). Unlike the LCD in FIG. 2, the liquid crystal panel 102 and lamps 113A to 113H included in the LCD in FIG. 8 operate at the frame frequency (for example, 60 Hz) of the original video data. In addition, the liquid crystal panel 102 and the lamps 113A to 113H can be selectively driven in the first driving mode or the second driving mode. In the first driving mode, the LCD of FIG. 8 is driven according to the timing shown in FIGS. 9A and 9B. In the second driving mode, the LCD of FIG. 8 is driven according to the timing shown in FIGS. 10A and 10B . For convenience, the operation of the LCD in the second driving mode will be referred to as the sixth embodiment of the present invention. The LCD of FIG. 8 will be described in detail below according to driving modes.

Referring to FIG. 9A, the gate driver 104 sequentially enables the gate lines GL1-GLk on the upper part A of the liquid crystal panel 102 once in each frame period of video data, that is, in each period (1/60 second) of a vertical synchronization signal. The gate driver 104 sequentially enables the gate lines GL(k+1)-GL2k once on the lower portion B of the liquid crystal panel 102 to be driven in synchronization with the gate lines GL1-GLk. For example, the gate driver 104 simultaneously enables the first gate line GL1 and the (k+1)th gate line GL(k+1) for two periods of the horizontal synchronizing signal, and simultaneously enables the second gate line GL2 and the (k+1)th gate line GL2 k+2) two periods of the horizontal synchronous signal of the gate line GL (k+2), simultaneously enabling the third gate line GL3 and the horizontal synchronous signal of the (k+3)th gate line GL (k+3) two cycles. In this way, the kth gate line GLk and the 2kth gate line GL2k are simultaneously enabled for the last two periods of the horizontal synchronization signal. That is, the gate driver 104 drives k pairs of the first k gate lines GL1-GLk for the upper part A of the liquid crystal panel 102 and the second k gate lines GL for the lower part B of the liquid crystal panel 102 (k+ 1) - GL2k lasts two cycles of the horizontal sync signal. To this end, as shown in FIG. 9A , the gate driver 104 provides 2k scan signals SGL1-SGL2k to 2k gate lines GL1-GL2k in each period of the vertical synchronization signal, ie, each frame period. The 2k scanning signals SGL1-SGL2k are divided into the first scanning signal group SGL1-SGLk for the first k gate lines GL1-GLk of the upper part A of the liquid crystal panel 102 and the second scanning signal group SGL1-SGLk for the lower part B of the liquid crystal panel 102. The second scanning signal group SGL(k+1)-SGL2k of the k gate lines GL(k+1)-GL2k. The first scan signal group SGL1-SGLk has a gate high voltage VGH pulse having the same pulse and width as the second scan signal group SGL(k+1)-SGL2k. The pulse width of gate high voltage VGH corresponds to two cycles of the horizontal synchronizing signal. As the gate line GL on the upper part A of the liquid crystal panel 102 moves downward, the pulses of the gate high voltage VGH included in the first scanning signal group SGL1-SGLk are sequentially shifted by their own widths (for example, two horizontal synchronization signals cycle). Similarly, as the gate line GL on the lower portion B of the liquid crystal panel 102 moves downward, the pulses of the gate high voltage VGH included in the second scanning signal group SGL(k+1)-SGL2k are sequentially shifted by their own width (eg, two periods of the horizontal sync signal).

The first data driver 106A converts the R, G, B pixel data corresponding to one row into analog data voltages in response to the data control signal, and supplies the data voltages of one row to the upper data lines UDL1-UDLm arranged in part A on the liquid crystal panel 102 . As long as any one of the gate lines GL1-GLk arranged in the part A on the liquid crystal panel 102 is enabled, the first data driver 106A outputs data voltages for one row. The first data driver 106A supplies data voltages for one row to the upper data lines UDL1-UDLm with a cycle equivalent to two cycles of the horizontal synchronizing signal and a width equal to that of the gate lines GL1-GLk arranged on the upper part A of the liquid crystal panel 102. the width of the high pulse.

Similarly, the second data driver 106B converts the R, G, and B pixel data corresponding to one row into analog data voltages in response to the data control signal, and supplies the data voltages of one row to the lower data lines arranged in the lower part B of the liquid crystal panel 102 LDL1-LDLm. As long as any one of the gate lines GL(k+1)-GL2k arranged in the lower portion B of the liquid crystal panel 102 is enabled, the second data driver 106B outputs a row of data voltages. The second data driver 106B supplies data voltages for one row to the lower data lines LDL1-LDLm with a period equivalent to two periods of the horizontal synchronization signal and a width equal to that of the gate lines GL1-GLk arranged on the lower part B of the liquid crystal panel 102. the width of the high pulse.

Since the gate lines GL(k+1)-GL2k are simultaneously enabled together with the gate lines GL1-GLk, a row of data voltages from the first data driver 106A and a row of data voltages from the second data driver 106B are separately and simultaneously The ground is provided to the upper data lines UDL1-UDLm and the lower data lines LDL1-LDLm. Therefore, when a row of liquid crystal cells for the upper portion A of the liquid crystal panel 102 is charged with the data voltage, a row of liquid crystal cells for the lower portion B of the liquid crystal panel 102 is charged with the data voltage. That is to say, the liquid crystal cells on the liquid crystal panel 102 are charged by the first and second data drivers 106A and 106B and the gate driver 104 in two rows at a time for two cycles of the horizontal synchronizing signal of the data voltage. Therefore, the liquid crystal cells Clc on the first sub-regions A1 and B1 of the upper part A and the lower part B of the liquid crystal panel 102 are simultaneously charged with the data voltage. Then, the data voltage is written into the liquid crystal cells Clc on the second sub-regions A2 and B2 of the upper part A and the lower part B of the liquid crystal panel 102 . Then, the data voltage is simultaneously written into the liquid crystal cells Clc on the third sub-regions A3 and B3 of the upper part A and the lower part B of the liquid crystal panel 102 . Finally, the data voltage is simultaneously written into the liquid crystal cells Clc on the fourth sub-regions A4 and B4 of the upper part A and the lower part B of the liquid crystal panel 102 .

When two cycles of the horizontal synchronizing signal of one of the first k gate lines GL1-GLk on the part A of the liquid crystal panel 102 are enabled by the pulse of the gate high voltage VGH, the TFT connected to the enabled gate line is turned on, Thus, the data voltage from the upper data line UDL is transmitted to the corresponding liquid crystal cell Clc. When the scan signal changes from the gate high voltage VGH to the gate low voltage VGL, the TFTs conducting on the upper portion A of the liquid crystal panel 102 are turned off, so that the liquid crystal cell Clc is not electrically connected to the upper data line UDL. During the two periods of the horizontal synchronization signal, that is, the TFT conduction period, the liquid crystal cell Clc is charged with the data voltage provided by the upper data line UDL. Then, the charged data voltage is maintained until the TFT is turned on again in the next frame period.

Similarly, when one of the second k gate lines GL(k+1)-GL2k of the lower part B of the liquid crystal panel 102 is enabled by the pulse of the gate high voltage VGH, the TFT connected to the enabled gate line is turned on, Thus, the data voltage from the lower data line LDL is transmitted to the corresponding liquid crystal cell Clc. When the scan signal changes from the gate high voltage VGH to the gate low voltage VGL, the TFTs conducting on the lower part B of the liquid crystal panel 102 are turned off, so that the liquid crystal cell Clc is not electrically connected to the lower data line UDL. During the two periods of the horizontal synchronization signal, that is, the TFT conduction period, the liquid crystal cell Clc is charged with the data voltage provided by the lower data line LDL. Then, the charged data voltage is maintained until the TFT is turned on again in the next frame period.

The first to fourth lamp drivers 115A to 115D of the backlight unit 112 commonly connected to the timing controller 108 sequentially turn on and off the lamps 113A to 113D of the sub-regions A1 to A4 of the upper part A of the liquid crystal panel 102 to communicate with the lower part of the liquid crystal panel 102. The lamps 113E to 113H of the section B subareas B1 to B4 are synchronized. Each of the lamps 113A to 113D is turned on and off once in each frame period. For example, the frame period corresponds to the period of the vertical synchronization signal. To this end, the first to fourth lamp drivers 115A to 115 control lamp driving voltages to be supplied to the lamps 113A to 113H. The duty cycle (ie, the ratio of on time to off time) of each lamp drive voltage can be different. The operations and effects of the first to fourth lamp drivers 115 will be described in detail below with reference to FIG. 9B.

Referring to FIG. 9B, the waveform "DW113AE" represents the time period for writing the data voltage to the liquid crystal cells Clc in the first sub-regions A1 and B1 of the upper part A and the lower part B of the liquid crystal panel 102, and during DE113AE, in the liquid crystal panel 102 The liquid crystal cells Clc in the first sub-regions A1 and B1 of the upper part A and the lower part B are charged with the data voltage in the first 1/4 period of the frame period, that is, the DWP period, and in the remaining 3/4 period of the frame period The filled data is kept in . The waveform "DW113BF" represents the time period for writing the data voltage to the liquid crystal cells Clc in the second sub-regions A2 and B2 of the upper part A and the lower part B of the liquid crystal panel 102. The liquid crystal cells Clc in the second sub-regions A2 and B2 are charged with the data voltage during the second 1/4 period of the frame period, that is, the DWP period, and are charged with the data voltage during the remaining 1/2 period of the frame period and 1/2 of the next frame period. The charged data is maintained for 4 cycles. The waveform "DW113CG" represents the time period for writing the data voltage to the liquid crystal cells Clc in the third sub-regions A3 and B3 of the upper part A and the lower part B of the liquid crystal panel 102. The liquid crystal cells Clc in the third sub-regions A3 and B3 are charged with the data voltage in the third 1/4 period of the frame period, that is, the DWP period, and are charged with the data voltage in the remaining 1/4 period of the frame period and the first period of the next frame period. The charged data is kept in 1/2 cycle. The waveform "DW113DH" represents the time period for writing the data voltage to the liquid crystal cells Clc in the fourth sub-regions A4 and B4 of the upper part A and the lower part B of the liquid crystal panel 102. The liquid crystal cells Clc in the fourth sub-regions A4 and B4 are charged with data voltage in the fourth 1/4 period of the frame period, ie, the DWP period, and maintain the charged data in the 3/4 period of the next frame period.

The first lamp driver 115A simultaneously supplies the first lamp driving voltage LE113AE of FIG. 9B to the first lamp 113A and the fifth lamp 113E for the first sub-regions A1 and B1 of the liquid crystal panel 102 . The first lamp driving voltage LE113AE generated from the first lamp driver 115A has a low level during the period DWP in which the data voltage is written into the liquid crystal cells Clc on the first sub-regions A1 and B1 of the liquid crystal panel 102 , while in the liquid crystal panel 102 The liquid crystal cells Clc on the first sub-regions A1 and B1 of the first sub-regions A1 and B1 have a high level during the period LEP during which the data voltage is maintained. The high level period LEP of the first lamp driving voltage LE113AE may be shortened according to the brightness of the first sub-regions A1 and B1 of the liquid crystal panel 102 . The first and fifth lamps 113A and 113E, which jointly respond to the first lamp driving voltage LE113AE output by the first lamp driver 115A, are simultaneously turned off during the period in which the liquid crystal cells Clc of the first sub-regions A1 and B1 of the liquid crystal panel 102 charge the data voltage, While the liquid crystal cell Clc on the first sub-regions A1 and B1 of the liquid crystal panel 102 is turned on during the period when the charged data voltage is maintained, so as to irradiate light to the first sub-regions A1 and B1 of the liquid crystal panel 102 .

The second lamp driver 115B simultaneously supplies the second lamp driving voltage LE113BF of FIG. 9B to the second lamp 113B and the sixth lamp 113F for the second sub-regions A2 and B2 of the liquid crystal panel 102 . The second lamp driving voltage LE113BF generated from the second lamp driver 115B has a low level during the period DWP in which the data voltage is written into the liquid crystal cells Clc on the second sub-regions A2 and B2 of the liquid crystal panel 102 , while in the liquid crystal panel 102 The liquid crystal cells Clc on the second sub-regions A2 and B2 maintain a high level during the period LEP of the data voltage. The high level period LEP of the second lamp driving voltage LE113BF may be shortened according to the brightness of the second sub-regions A2 and B2 of the liquid crystal panel 102 . The second and sixth lamps 113B and 113F that jointly respond to the second lamp driving voltage LE113BF output by the second lamp driver 115B are simultaneously turned off during the period of charging the data voltage of the liquid crystal cells Clc in the second sub-regions A2 and B2 of the liquid crystal panel 102, While the liquid crystal cell Clc on the second sub-regions A2 and B2 of the liquid crystal panel 102 is turned on during the period when the charged data voltage is maintained, thereby irradiating light to the second sub-regions A2 and B2 of the liquid crystal panel 102 .

The third lamp driver 115C simultaneously supplies the third lamp driving voltage LE113CG of FIG. 9B to the third lamp 113C and the seventh lamp 113G for the third sub-regions A3 and B3 of the liquid crystal panel 102 . The third lamp driving voltage LE113CG generated from the third lamp driver 115C has a low level during the period DWP in which the data voltage is written into the liquid crystal cells Clc on the third sub-regions A3 and B3 of the liquid crystal panel 102 , while in the liquid crystal panel 102 The liquid crystal cells Clc on the third sub-regions A3 and B3 have a high level during the period LEP during which the data voltage is maintained. The high level period LEP of the third lamp driving voltage LE113CG may be shortened according to the brightness of the third sub-regions A3 and B3 of the liquid crystal panel 102 . The third and seventh lamps 113C and 113G, which jointly respond to the third lamp driving voltage LE113CG output by the third lamp driver 115C, are simultaneously turned off during the period in which the liquid crystal cells Clc of the third sub-regions A3 and B3 of the liquid crystal panel 102 charge the data voltage, While the liquid crystal cell Clc on the third sub-regions A3 and B3 of the liquid crystal panel 102 is turned on during the period when the charged data voltage is maintained, so as to irradiate light to the third sub-regions A3 and B3 of the liquid crystal panel 102 .

The fourth lamp driver 115D simultaneously supplies the fourth lamp driving voltage LE113DH of FIG. 9B to the fourth lamp 113D and the eighth lamp 113H for the fourth areas A4 and B4 of the liquid crystal panel 102 . The fourth lamp driving voltage LE113DH generated from the fourth lamp driver 115D has a low level during the period DWP in which the data voltage is written into the liquid crystal cells Clc on the fourth sub-regions A4 and B4 of the liquid crystal panel 102 , while in the liquid crystal panel 102 The liquid crystal cells Clc on the fourth sub-regions A4 and B4 have a high level during the period LEP for maintaining the data voltage. The high level period LEP of the fourth lamp driving voltage LE113DH may be shortened according to the brightness of the fourth sub-regions A4 and B4 of the liquid crystal panel 102 . The fourth and eighth lamps 113D and 113H jointly responding to the fourth lamp driving voltage LE113DH output by the fourth lamp driver 115D are simultaneously turned off during the cycle of charging the data voltage of the liquid crystal cells Clc in the fourth sub-regions A4 and B4 of the liquid crystal panel 102, While the liquid crystal cell Clc on the fourth sub-regions A4 and B4 of the liquid crystal panel 102 is turned on during the period when the charged data voltage is maintained, so as to irradiate light to the fourth sub-regions A4 and B4 of the liquid crystal panel 102 .

In order to drive the liquid crystal panel 102 and the lamps 113A to 113H as shown in FIGS. 9A and 9B , the timing controller 108 provides a gate control signal to the gate driver 104, a data control signal to the first and second data drivers 106A and 106B, and The lamp control signals are supplied to the first to fourth lamp driving controllers 115A to 115D. In addition, the timing controller 108 divides two lines of pixel data to the first and second data drivers 106A and 106B for two periods of the horizontal synchronization signal. That is, the timing controller 108 provides one row of pixel data to the first data driver 106A and one row of pixel data to the second data driver 106B during two cycles of the horizontal sync cycle signal. To this end, the timing controller 108 responds to vertical/horizontal sync signals (Vsync/Hsync), data enable signals ( DE), clock signal and video data. The timing controller 108 generates a gate control signal for the gate driver 104 for the first and second data drivers 106A and 106B by using a vertical/horizontal synchronous signal (Vsync/Hsync), a data enable signal (DE), and a clock signal. data control signals for the first to fourth lamp drivers 115A to 115D. In addition, the timing controller 108 arranges R, G, and B pixel data supplied from an external system into row-by-row R, G, and B pixel data, and converts one row of R, G, and B pixel data every two cycles of the horizontal synchronization signal. provided to the first and second data drivers 106A and 106B. Accordingly, the first data driver 106A converts one row of R, G, and B pixel data into analog data voltages every two periods of the horizontal sync signal. The data voltages for one row converted by the first data driver 106A are simultaneously supplied to the upper data lines UDL1-UDLm. In synchronization with the first data driver 106A, the second data driver 106B converts one row of R, G, and B pixel data into analog data voltages. The data voltage for one row converted by the second data driver 106B is simultaneously supplied to the lower data lines LDL1-LDLm.

As shown in FIG. 9B, the first to fourth lamp drivers 115A to 115D sequentially turn on and off the liquid crystal panel in synchronization with the first to fourth lamps 113A to 113D and the fifth to eighth lamps 113E to 113H in each frame period. The first to fourth lamps 113A to 113D corresponding to the upper part A of the liquid crystal panel 102 and the fifth to eighth lamps 113E to 113H corresponding to the lower part B of the liquid crystal panel 102 are simultaneously written in the liquid crystal cell Clc once. Thus, video data and black level data are alternately displayed once on the liquid crystal panel 102 at each frame period (for example, 1/60 second) of video data generated by an external system.

Therefore, the LCD according to the embodiment of the present invention can quickly respond to video data. Thus, no motion blur phenomenon occurs when displaying moving images. In addition, simultaneously supplying the charging data voltage to both parts of the liquid crystal panel also prevents unclear images or image sticking, thereby expressing images quickly.

In addition, the plurality of lamps for the upper sub-region of the liquid crystal panel 102 and the plurality of lamps for the lower sub-region of the liquid crystal panel 102 are turned on and off by the same lamp driver. Therefore, the circuit for driving the lamp can be simplified.

Referring to FIG. 10A, the gate driver 104 sequentially enables the gate lines GL1-GLk for the upper portion A of the liquid crystal panel 102 once in half of each frame period (eg, 1/60 second) of video data. The gate driver 104 sequentially enables the gate lines GL(k+1)-GL2k once for the lower portion B of the liquid crystal panel 102 to be driven in synchronization with the gate lines GL1-GLk. For example, the gate driver 104 simultaneously enables the first gate line GL1 and the (k+1)th gate line GL(k+1) for one cycle of the horizontal synchronization signal, and simultaneously enables the second gate line GL2 and the ( The k+2) gate line GL(k+2) lasts another period of the horizontal synchronization signal, and simultaneously enables the third gate line GL3 and the (k+3)th gate line GL(k+3) to continue horizontal synchronization Another cycle of the signal. In this way, the k-th gate line GLk and the 2k-th gate line GL2k are simultaneously enabled for the last two periods of the horizontal synchronization signal. That is, the gate driver 104 drives k pairs of the first k gate lines GL1-GLk for the upper part A of the liquid crystal panel 102 and the second k gate lines GL for the lower part B of the liquid crystal panel 102 (k+ 1) - GL2k lasts every cycle of the horizontal sync signal. In addition, the gate driver 104 is in an idle mode so that no gate lines are enabled during the remaining half frame periods of each frame period of video data.

To this end, as shown in FIG. 10A , the gate driver 104 provides 2k scan signals SGL1-SGL2k to 2k gate lines GL1-GL2k in each half period of the vertical synchronization signal. The 2k scanning signals SGL1-SGL2k are divided into the first scanning signal group SGL1-SGLk provided to the first k gate lines GL1-GLk of the upper part A of the liquid crystal panel 102 and the second k gate lines of the lower part B of the liquid crystal panel 102 The second scanning signal group SGL(k+1)-SGL2k of GL(k+1)-GL2k. The first scan signal group SGL1-SGLk has a gate high voltage VGH pulse having the same pulse and width as the second scan signal group SGL(k+1)-SGL2k. The pulse width of gate high voltage VGH corresponds to one cycle of the horizontal synchronization signal. As the gate line GL on the upper part A of the liquid crystal panel 102 moves downward, the pulses of the gate high voltage VGH contained in the first scanning signal group SGL1-SGLk are sequentially shifted by their own width (for example, one of the horizontal synchronization signals cycle). Similarly, as the gate lines on the lower portion B of the liquid crystal panel 102 move downward, the pulses of the gate high voltage VGH included in the second scanning signal group SGL(k+1)-SGL2k are sequentially shifted by their own width ( For example, one cycle of the horizontal sync signal). In addition, the gate driver 104 maintains the scan signal at the gate low voltage VGL for 2k scan signals in each cycle of the vertical synchronous signal, so as not to perform the operation of writing the data voltage.

As the gate driver 104 sequentially enables the gate lines GL1-GLk of the part A on the liquid crystal panel 102 in each period of the horizontal synchronous signal, the first data driver 106A supplies the liquid crystals of the part A on the liquid crystal panel 102 with half periods of the vertical synchronous signal. The cells Clc are sequentially charged with data voltages in a row-by-row manner. Then, the first data driver 106A is set to an idle mode in the second half cycle of a vertical sync signal. During a half cycle of a vertical sync signal, that is, a data voltage writing cycle, the data voltages of one row provided by the first data driver 106A to the data lines UDL1-UDLm are updated in each cycle of the horizontal sync signal.

Similarly, as the gate driver 104 sequentially enables the gate lines GL(k+1)-GL2k of the lower part B of the liquid crystal panel 102 in each period of the horizontal synchronous signal, the second data driver 106B sequentially enables the gate lines GL(k+1)-GL2k in the half period of the vertical synchronous signal. The liquid crystal cells Clc of the lower portion B of the liquid crystal panel 102 are sequentially charged with data voltages in a row-by-row manner. Then, the second data driver 106B is set to an idle mode in the second half period of a vertical synchronous signal. The data voltages for one row supplied by the second data driver 106B to the data lines LDL1-LDLm are updated in synchronization with the data voltages for one row supplied by the first data driver 106A in each period of the horizontal synchronization signal.

The first data drivers 106A and 106B and the gate driver 104 charge data voltages to the liquid crystal cells in the subregion of the upper part A of the liquid crystal panel 102 and the liquid crystal cells in the subregion of the lower part B of the liquid crystal panel 102 during the half cycle of the vertical synchronous signal, thereby They are synchronized with each other respectively. For example, the liquid crystal cells in the sub-region A1 of the upper part A of the liquid crystal panel 102 and the liquid crystal cells in the sub-region B1 of the lower part B of the liquid crystal panel 102 DWP charge the data voltage in the first 1/8 cycle of a vertical synchronous signal, and in The remaining 7/8 period of a vertical sync signal maintains the charged data voltage. The liquid crystal cells in the sub-region A2 of the upper part A of the liquid crystal panel 102 and the liquid crystal cells in the sub-region B2 of the lower part B of the liquid crystal panel 102 charge the data voltage in the second 1/8 cycle DWP of a vertical synchronous signal, and in a vertical The remaining 6/8 period of the sync signal and the first 1/8 period of the next vertical sync signal maintain the charged data voltage. The liquid crystal cells in the subregion A3 of the upper part A of the liquid crystal panel 102 and the liquid crystal cells in the subregion B3 of the lower part B of the liquid crystal panel 102 charge the data voltage in the third 1/8 cycle DWP of a vertical synchronous signal, and in a vertical The remaining 5/8 cycle of the sync signal and the first 1/4 cycle of the next vertical sync signal maintain the charged data voltage. The liquid crystal cells in the sub-region A4 of the upper part A of the liquid crystal panel 102 and the liquid crystal cells in the sub-region B4 of the lower part B of the liquid crystal panel 102 charge the data voltage in the fourth 1/8 cycle DWP of a vertical synchronous signal, and in a vertical The remaining 1/2 cycle of the sync signal and 3/8 cycle of the next vertical sync signal maintain the charged data voltage.

The first to fourth lamp drivers 115A to 115D of the backlight unit 112 commonly controlled by the timing controller 108 sequentially turn on and off the lamps 113A to 113H in each period of the vertical synchronization signal, that is, each frame period. Each of the lamps 113A to 113H is turned on and off once in each frame period. The lamps 113A-113D of the sub-regions A1-A4 and the sub-regions 113E-113H of the sub-regions B1-B4 are turned on after the alignment saturation period elapses after the liquid crystal cells are charged with the data voltage. Therefore, the lamp driving voltages supplied from the first to fourth lamp drivers 115A to 115D to the corresponding lamps 113A to 113H can be effective after the alignment saturation period elapses after the end of the data voltage writing period, and when writing to the sub-regions of the liquid crystal panel 102 Invalid at data voltage. The effective period of the lamp driving voltages generated by the lamp drivers 115A to 115D is adjusted in a period other than the data writing period and the orientation saturation period of the sub-area in the period of a vertical synchronizing signal. The operation and influence of the first to fourth lamps 115A to 115D generating the above-mentioned lamp driving voltages will be described below with reference to FIG. 10B.

Referring to FIG. 10B , a waveform “DW113AE” represents a time period for writing a data voltage to the liquid crystal cells Clc in the first sub-regions A1 and B1 of the upper portion A and the lower portion B of the liquid crystal panel 102 . The waveform "LE113AE" represents the time period during which the first lamp driver 115A outputs the first lamp driving signal valid. According to the time periods DW113AE and LE113AE, in the first 1/8 period DWP of the vertical synchronous signal including charging the data voltage to the liquid crystal cell Clc of the first sub-regions A1 and B1 of the liquid crystal panel 102 and with the vertical synchronous signal 3/8 The period corresponds to the half period of the vertical synchronizing signal oriented to the saturation period ASP, and the first lamp driving voltage LE113AE from the first lamp driver 115A has a low level. On the other hand, in the period (ASP_LEP) in which the liquid crystal cells Clc in the first subregions A1 and B1 of the liquid crystal panel 102 hold the data voltage, except for the alignment saturation period ASP in which the liquid crystal molecules are rearranged in an alignment direction corresponding to the data voltage period (light irradiation period LEP), the first lamp driving voltage LE113AE has a high level. The light irradiation period LEP corresponds to a half period of a vertical sync signal, and can be shortened according to the brightness values of the first sub-regions A1 and B1 of the liquid crystal panel 102 . When the light irradiation period LEP is shortened, the alignment saturation period ASP is extended by as much as the reduction value of the light irradiation period LEP. After the data voltage is written or charged into the liquid crystal cells Clc of the first sub-regions A1 and B1 of the liquid crystal panel 102, the vertical synchronous signal from when the orientation saturation period ASP corresponding to 3/8 period of the vertical synchronous signal elapses In the half cycle of , the first lamp 113A and the fifth lamp 113E are turned on simultaneously in response to the first lamp driving voltage LE113AE output from the first lamp driver 115A. Accordingly, light is irradiated onto the first sub-regions A1 and B1 of the liquid crystal panel 102 . Since the first lamp 113A and the fifth lamp 113E irradiate light after the liquid crystal cells Clc on the first sub-regions A1 and B1 of the liquid crystal panel 102 are aligned in a direction corresponding to the data voltage, pixel data can be correctly displayed. In addition, black level data is displayed on the first sub-regions A1 and B1 of the liquid crystal panel 102 while the first lamp 113A and the fifth lamp 113E are off. Therefore, the influence of the pseudo-pulse display is greatest on the first sub-regions A1 and B1 of the liquid crystal panel 102 .

In FIG. 10B , a waveform "DW113BF" represents a time period for writing a data voltage to the liquid crystal cells Clc in the second sub-regions A2 and B2 of the upper portion A and the lower portion B of the liquid crystal panel 102 . The waveform "LE113BF" represents a time period during which the second lamp driving signal output by the second lamp driver 115B is valid. According to the time periods DW113BF and LE113BF, in the second 1/8 period DWP of the vertical synchronous signal including charging the data voltage to the liquid crystal cells Clc of the second sub-regions A2 and B2 of the liquid crystal panel 102 and corresponding to the vertical synchronous signal 3/ The second lamp driving voltage LE113BF from the second lamp driver 115B has a low level for a half cycle of the vertical synchronizing signal of the orientation saturation period ASP of 8 cycles. On the other hand, in the period (ASP_LEP) in which the liquid crystal cells Clc in the second sub-regions A2 and B2 of the liquid crystal panel 102 hold the data voltage, except for the alignment saturation period ASP in which the liquid crystal molecules are rearranged in an alignment direction corresponding to the data voltage period (light irradiation period LEP), the second lamp driving voltage LE113BF has a high level. The light irradiation period LEP corresponds to a half period of a vertical sync signal, and can be shortened according to the brightness values of the second sub-regions A2 and B2 of the liquid crystal panel 102 . When the light irradiation period LEP is shortened, the alignment saturation period ASP is extended by as much as the light irradiation period LEP decreases. The vertical synchronous signal from when the orientation saturation period ASP corresponding to 3/8 period of the vertical synchronous signal elapses after the data voltage is written or charged into the liquid crystal cells Clc of the second subregions A2 and B2 of the liquid crystal panel 102 In a half period, the second lamp 113B and the sixth lamp 113F are turned on simultaneously in response to the second lamp driving voltage LE113BF output from the second lamp driver 115B. Accordingly, light is irradiated onto the second sub-regions A2 and B2 of the liquid crystal panel 102 . Since the second lamp 113B and the sixth lamp 113F irradiate light after the liquid crystal cells Clc on the second sub-regions A2 and B2 of the liquid crystal panel 102 are aligned in a direction corresponding to the data voltage, pixel data can be correctly displayed. In addition, black level data is displayed on the second sub-regions A2 and B2 of the liquid crystal panel 102 while the second lamp 113B and the sixth lamp 113F are turned off. Therefore, the influence of the pseudo-pulse display is greatest on the second sub-regions A2 and B2 of the liquid crystal panel 102 .

In FIG. 10B , a waveform "DW113CG" represents a time period for writing a data voltage to the liquid crystal cells Clc in the third sub-regions A3 and B3 of the upper portion A and the lower portion B of the liquid crystal panel 102 . The waveform "LE113CG" represents a time period during which the third lamp driving signal output by the third lamp driving 115C is valid. According to the time periods DW113CG and LE113CG, in the third 1/8 period DWP of the vertical synchronous signal including charging the data voltage to the liquid crystal cells Clc of the third sub-regions A3 and B3 of the liquid crystal panel 102 and corresponding to the vertical synchronous signal 3/ The third lamp driving voltage LE113CG from the third lamp driver 115C has a low level for a half cycle of the vertical synchronizing signal of the orientation saturation period ASP of 8 cycles. On the other hand, in the period (ASP_LEP) in which the liquid crystal cells Clc in the third subregions A3 and B3 of the liquid crystal panel 102 hold the data voltage, except for the alignment saturation period ASP in which the liquid crystal molecules are rearranged in an alignment direction corresponding to the data voltage period (light irradiation period LEP), the third lamp driving voltage LE113CG has a high level. The light irradiation period LEP corresponds to a half period of a vertical sync signal, and can be shortened according to the brightness values of the third sub-regions A3 and B3 of the liquid crystal panel 102 . When the light irradiation period LEP is shortened, the alignment saturation period ASP is extended, and its extension value is as large as the light irradiation period LEP decrease value. Half of the vertical synchronous signal from when the orientation saturation period ASP corresponding to 3/8 period of the vertical synchronous signal elapses after the data voltage is written or charged into the liquid crystal cells Clc of the third subregions A3 and B3 of the liquid crystal panel 102 During the period, the third lamp 113C and the seventh lamp 113G are simultaneously turned on in response to the third lamp driving voltage LE113CG output by the third lamp driver 115C. Accordingly, light is irradiated onto the third sub-regions A3 and B3 of the liquid crystal panel 102 . Since the third lamp 113C and the seventh lamp 113G irradiate light after the liquid crystal cells Clc on the third sub-regions A3 and B3 of the liquid crystal panel 102 are aligned in a direction corresponding to the data voltage, pixel data can be correctly displayed. In addition, black level data is displayed on the third sub-regions A3 and B3 of the liquid crystal panel 102 while the third lamp 113C and the seventh lamp 113G are turned off. Therefore, the influence of the pseudo-pulse display is greatest on the third sub-regions A3 and B3 of the liquid crystal panel 102 .

In FIG. 10B , a waveform "DW113DH" represents a time period for writing a data voltage to the liquid crystal cells Clc in the fourth sub-regions A4 and B4 of the upper part A and the lower part B of the liquid crystal panel 102 . The waveform "LE113DH" represents a time period during which the fourth lamp driving signal output by the fourth lamp driver 115D is valid. According to the time periods DW113DH and LE113, in the fourth 1/8 period DWP of the vertical synchronous signal including charging the data voltage into the liquid crystal cells Clc of the fourth sub-regions A4 and B4 of the liquid crystal panel 102 and corresponding to the vertical synchronous signal 3/ The fourth lamp driving voltage LE113DH from the fourth lamp driver 115D has a low level during a half period of the vertical synchronization signal of the orientation saturation period ASP of 8 periods. On the other hand, in the period (ASP_LEP) in which the liquid crystal cells Clc in the fourth subregions A4 and B4 of the liquid crystal panel 102 hold the data voltage, except for the alignment saturation period ASP in which the liquid crystal molecules are rearranged in an alignment direction corresponding to the data voltage period (light irradiation period LEP), the fourth lamp driving voltage LE113DH has a high level. The light irradiation period LEP corresponds to a half period of a vertical sync signal, and can be shortened according to the brightness values of the fourth sub-regions A4 and B4 of the liquid crystal panel 102 . When the light irradiation period LEP is shortened, the alignment saturation period ASP is extended by as much as the light irradiation period LEP decreases. Half a vertical sync from when the orientation saturation period ASP corresponding to 3/8 period of the vertical sync signal elapses after the data voltage is written or charged into the liquid crystal cells Clc of the fourth sub-regions A4 and B4 of the liquid crystal panel 102 During the signal period, the fourth lamp 113D and the eighth lamp 113H are simultaneously turned on in response to the fourth lamp driving voltage LE113DH output from the fourth lamp driver 115D. Accordingly, light is irradiated onto the fourth sub-regions A4 and B4 of the liquid crystal panel 102 . Because the fourth lamp 113D and the eighth lamp 113H irradiate light after the liquid crystal cells Clc on the fourth sub-regions A4 and B4 of the liquid crystal panel 102 are arranged in a direction corresponding to the data voltage, pixel data can be correctly displayed. In addition, black level data is displayed on the fourth sub-regions A4 and B4 of the liquid crystal panel 102 while the fourth lamp 113D and the eighth lamp 113H are turned off. Therefore, the influence of the pseudo-pulse display is greatest on the fourth sub-regions A4 and B4 of the liquid crystal panel 102 .

As shown in FIGS. 10A and 10B , the timing controller 108 controls the gate driver 104 and the first and second data drivers 106A and 106B to write data voltages to the liquid crystal cells of the liquid crystal panel 102 within half frame periods. At the same time, controlled by the timing controller 108 , the lamp driver drives the lamps 113A to 113H to be sequentially turned on and off once in each frame period. To this end, the timing controller 108 provides gate control signals to the gate driver 104, data control signals to the first and second data drivers 106A and 106B, and lamp control signals to the first to fourth lamp drivers 115A to 115D. In addition, the timing controller 108 provides two rows of pixel data to the first and second data drivers 106A and 106B within one period of a horizontal synchronization signal. That is to say, within a period of the horizontal synchronization signal, the timing controller 108 provides one row of pixel data to the first data driver 106A, and provides one row of pixel data to the second data driver 106B. To this end, the timing controller 108 responds to vertical/horizontal sync signals (Vsync/Hsync), data enable signals ( DE), clock signal and video data. The timing controller 108 generates a gate control signal for the gate driver 104 for the first and second data drivers 106A and 106B by using a vertical/horizontal synchronous signal (Vsync/Hsync), a data enable signal (DE), and a clock signal. data control signals for the first to fourth lamp drivers 113A to 113D. In addition, the timing controller 108 arranges R, G, and B pixel data supplied from an external system into row-by-row R, G, and B pixel data, and supplies one row of R, G, and B pixel data every period of the horizontal synchronization signal. to the first and second data drivers 106A and 106B.

Accordingly, the first data driver 106A converts one row of R, G, and B pixel data into analog data voltages every period of the horizontal synchronization signal. The data voltages for one row converted by the first data driver 106A are simultaneously supplied to the upper data lines UDL1-UDLm. In synchronization with the first data driver 106A, the second data driver 106B converts one row of R, G, and B pixel data into analog data voltages. The data voltage for one row converted by the second data driver 106B is simultaneously supplied to the lower data lines LDL1-LDLm. As shown in FIG. 10B , after the alignment saturation period ASP passes after the data voltage is written to the sub-regions A1 to A4 of the liquid crystal panel 102 to the time when the data voltage is written to the sub-regions A1 to A4 of the liquid crystal panel 102, by The first to fourth lamp drivers 115A to 115D controlled by the timing controller 108 turn on the first to fourth lamps 113A to 113D. In addition, the first to fourth lamp drivers 115A to 115D turn on and off the fifth to eighth lamps 113E to 113H in synchronization (simultaneously) with the first to fourth lamps 113A to 113D. Therefore, from the time after the alignment saturation period ASP elapses after writing the data voltages to the subregions B1 to B4 of the liquid crystal panel 102 to the start of writing the data voltages to the subregions B1 to B4 of the liquid crystal panel 102, the fifth to eighth The lamps 113E to 113H are turned on.

After writing the data voltages to the lamps 113A to 113H, the liquid crystal molecules are aligned in a direction corresponding to the data voltages, and the timing controller 108 controls the first to fourth lamp drivers to irradiate light onto sub-regions of the liquid crystal panel 102 . Therefore, when the lamps 113A to 113H are turned on, the liquid crystal panel 102 correctly displays an image corresponding to the video data (data voltage) on the sub-area. On the other hand, when the lamps 113A to 113H are turned off, black level data is displayed on the sub-regions corresponding to the lamps 113A to 113H.

In this way, since the lamps 113A and 113H are turned on and off once each frame, the black level image and the image corresponding to the video data are each correctly displayed once, thereby minimizing the influence of spurious impulsive driving. Therefore, the LCD according to the embodiment of the present invention can quickly respond to video data. In addition, motion blur does not occur when displaying moving images. In addition, it is possible to prevent unclear images or image retention. Therefore, the LCD according to the embodiment of the present invention can display high-quality images.

In addition, the plurality of lamps for the upper sub-region of the liquid crystal panel and the plurality of lamps for the lower sub-region of the liquid crystal panel are turned on and off by the same lamp driver. Therefore, the circuit for driving the lamp can be simplified.

Thus, video data and black level data are alternately displayed on the liquid crystal panel 102 at a frame frequency (for example, a second frame frequency of 120 Hz) twice that of video data generated by an external system (for example, a first frame frequency of 60 Hz). Shown twice. Therefore, the LCD according to the embodiment of the present invention can quickly respond to video data. Thus, no motion blur phenomenon occurs when displaying moving images. In addition, since the charging data voltage is simultaneously supplied to both parts of the liquid crystal panel, it is also possible to prevent unclear images or image sticking, thereby expressing images quickly.

In addition, the plurality of lamps for the upper sub-region of the liquid crystal panel and the plurality of lamps for the lower sub-region of the liquid crystal panel are turned on and off by the same lamp driver. Therefore, the circuit for driving the lamp can be simplified.

As described above, in the LCD and its driving method according to the embodiment of the present invention, the frame frequency (for example, the first frame frequency 60 Hz) twice the frame frequency (for example, the first frame frequency 60 Hz) of the video data generated by the external system is displayed on the liquid crystal panel. For example, the second frame frequency (120 Hz) alternately displays the video data and the black level data at least once. Therefore, the LCD according to the embodiment of the present invention can quickly respond to video data. Thus, no motion blur phenomenon occurs when displaying moving images. In addition, alternately displaying video data and black level data on the LCD panel during each frame period also prevents image blurring or image sticking, allowing images to be displayed quickly while minimizing brightness reduction.

In addition, the plurality of lamps for the upper sub-region of the liquid crystal panel and the plurality of lamps for the lower sub-region of the liquid crystal panel are turned on and off by the same lamp driver. Therefore, the circuit for driving the lamp can be simplified.

It is obvious that various modifications and improvements can be made to the present invention by those skilled in the art. Accordingly, it is intended that the present invention includes all modifications and improvements of this invention that come within the scope of the appended claims and their equivalents.

Claims (40)

1, a kind of liquid crystal display device comprises:

Liquid crystal panel, second data line that has first data line that intersects in the first area of liquid crystal panel with grid line and intersect at the second area of liquid crystal panel with grid line;

Data converter is used for first video data with first frame rate is converted to second video data with second frame rate that is higher than first frame rate;

Back light unit has and comprises at least and be used for respectively in the first lamp group of two lamps of irradiates light on the subregion of first area and comprise the second lamp group that is used for two lamps of irradiates light on the subregion at second area respectively at least; And

Driver is used for according to the second video data driven grid line, first data line and second data line and is used for driving the first and second lamp groups at second frame rate, thus the synchronously order opening and closing of the lamp of the lamp of the first lamp group and the second lamp group.

2, liquid crystal display device according to claim 1 is characterized in that, described driver comprises:

Gate driver, thus the grid line and the grid line on the first area that are used for driving simultaneously on the grid line second area on first and second zones are enabled synchronously in proper order;

First data driver is used to drive first data line on the first area;

Second data driver is used to drive second data line on the second area;

Time schedule controller, in response to second video data, the lamp that is used for control gate driver, first data driver and second data driver and enables the first and second lamp groups is with synchronously with one another by the order opening and closing.

3, liquid crystal display device according to claim 2, it is characterized in that, described back light unit comprises at least two lamp drivers, and this at least two lamp driver is by time schedule controller control and produce the lamp that is used to enable the first and second lamp groups with synchronously with one another by the lamp driving voltage of order opening and closing.

4, liquid crystal display device according to claim 3 is characterized in that, described lamp driving voltage has different duty factors.

5, liquid crystal display device according to claim 4 is characterized in that, second frame rate is the twice of first frame rate at least.

6, a kind of liquid crystal display device comprises:

Liquid crystal panel has grid line intersected with each other and data line;

Back light unit has and comprises and be used for subregion in the first lamp group of at least two lamps of irradiates light on the first area of liquid crystal panel with comprise the second lamp group of at least two lamps that are used for irradiates light on the second area of subregion at liquid crystal panel; And

Driver, be used for according to video data driven grid line with first frame rate and data line and be used to control the first lamp group and the second lamp group is driven simultaneously being higher than under second frame rate of first frame rate, thereby the lamp of the lamp of the first lamp group and the second lamp group is synchronously by the order opening and closing.

7, liquid crystal display device according to claim 6 is characterized in that, described driver comprises:

Gate driver is used for driven grid line;

Data driver is used for driving data lines; And

Time schedule controller, response has the video data response of first frame rate, and the lamp that is used for control gate driver and data driver and enables the first and second lamp groups is with synchronously with one another by the order opening and closing.

8, liquid crystal display device according to claim 7, it is characterized in that, described back light unit comprises at least two lamp drivers, and described at least two lamp drivers are by time schedule controller control and produce the lamp that is used to enable the first and second lamp groups with synchronously with one another by the lamp driving voltage of order opening and closing.

9, liquid crystal display device according to claim 8 is characterized in that, lamp driving voltage has different duty factors.

10, liquid crystal display device according to claim 6 is characterized in that, second frame rate is the twice of first frame rate at least.

11, liquid crystal display device according to claim 6 is characterized in that, described grid line comprises:

First grid line intersects on the 3rd zone that takies part first and second zones with data line; And

Second grid line intersects taking on the 4th zone of the first and second regional remainders with data line.

12, liquid crystal display device according to claim 11 is characterized in that, described driver comprises:

First grid driver is used to drive first grid line;

Second gate driver is used for driving second grid line with first grid line locking ground;

Data driver is used for driving data lines; And

Time schedule controller, response has the video data of first frame rate, is used to the lamp controlling first and second gate drivers and data driver and enable the first and second lamp groups with synchronously with one another by the order opening and closing.

13, liquid crystal display device according to claim 12, it is characterized in that, described back light unit comprises at least two lamp drivers, and described at least two lamp drivers are by time schedule controller control and produce the lamp driving voltage of lamp to be driven in proper order synchronously with one another that is used to enable the first and second lamp groups.

14, liquid crystal display device according to claim 13 is characterized in that, lamp driving voltage has different duty factors.

15, liquid crystal display device according to claim 11 is characterized in that, second frame rate is the twice of first frame rate at least.

16, a kind of liquid crystal display device comprises:

Liquid crystal panel, second data line that has first data line that intersects in the first area of liquid crystal panel with grid line and intersect at the second area of liquid crystal panel with grid line;

Back light unit has and comprises and be used for respectively in the first lamp group of at least two lamps of irradiates light on the subregion of first area and comprise the second lamp group that is used at least two lamps of irradiates light on the subregion at second area respectively; And

Driver, be used for driven grid line and data line the data voltage of video data is write the liquid crystal cells of first area and the liquid crystal cells of second area simultaneously in line by line mode at each frame, and be used to drive the first and second lamp groups, thereby at least two lamps of at least two lamps of the first lamp group and the second lamp group are opened in proper order or are closed synchronously with one another.

17, liquid crystal display device according to claim 16 is characterized in that, grid line on the first area and the grid line on the second area were enabled synchronously with one another in proper order in per two cycles of horizontal-drive signal.

18, liquid crystal display device according to claim 17 is characterized in that, described driver comprises:

Gate driver be used for driving simultaneously the grid line on first and second zones, thereby the grid line on grid line on the second area and the first area is enabled in proper order synchronously;

First data driver is used to drive first data line on the first area;

Second data driver is used to drive second data line on the second area; And

Time schedule controller, in response to video data, the lamp that is used for control gate driver, first data driver and second data driver and enables the first and second lamp groups is with synchronously with one another by the order opening and closing.

19, liquid crystal display device according to claim 18, it is characterized in that, described back light unit comprises at least two lamp drivers, and described at least two lamp drivers are by time schedule controller control and produce the lamp driving voltage of lamp to be driven in proper order synchronously with one another that is used to enable the first and second lamp groups.

20, liquid crystal display device according to claim 18 is characterized in that, lamp driving voltage has different duty factors.

21, a kind of liquid crystal display device comprises:

Liquid crystal panel, second data line that has first data line that intersects in the first area of liquid crystal panel with grid line and intersect at the second area of liquid crystal panel with grid line;

Back light unit has and comprises and be used for respectively in the first lamp group of at least two lamps of irradiates light on the subregion of first area and comprise the second lamp group that is used at least two lamps of irradiates light on the subregion at second area respectively; And

Driver, be used to operate grid line and data line the data voltage of video data is write the liquid crystal cells of first area and the liquid crystal cells of second area simultaneously in line by line mode at each frame, and be used to drive the first and second lamp groups, thereby the lamp of the first and second lamp groups writes at data voltage and is unlocked after the saturated period expires of orientation behind the liquid crystal cells of corresponding subregion or closes.

22, liquid crystal display device according to claim 21 is characterized in that, grid line on the first area and the grid line on the second area were enabled synchronously with one another in proper order in each cycle of a horizontal-drive signal.

23, liquid crystal display device according to claim 22 is characterized in that, grid line on the first area and the grid line on the second area are enabled once during the field cycle of each frame synchronously with one another in proper order.

24, liquid crystal display device according to claim 23 is characterized in that, described driver comprises:

Gate driver be used for driving simultaneously the grid line on first and second zones, thereby the grid line on grid line on the second area and the first area is enabled in proper order synchronously;

First data driver is used to drive first data line on the first area;

Second data driver is used to drive second data line on the second area; And

Time schedule controller, in response to video data, the lamp that is used for control gate driver, first data driver and second data driver and enables the first and second lamp groups is with synchronously with one another by the order opening and closing.

25, liquid crystal display device according to claim 24, it is characterized in that, described back light unit comprises at least two lamp drivers, and described at least two lamp drivers are by time schedule controller control and produce the lamp driving voltage of lamp to be driven in proper order synchronously with one another that is used to enable the first and second lamp groups.

26, liquid crystal display device according to claim 25 is characterized in that, lamp driving voltage has different duty factors.

27, a kind of liquid crystal display device comprises:

Liquid crystal panel has grid line intersected with each other and data line;

Back light unit has and comprises and be used for subregion in the first lamp group of at least two lamps of irradiates light on the first area of liquid crystal panel with comprise the second lamp group of at least two lamps that are used for irradiates light on the second area of subregion at liquid crystal panel; And

Driver is used for driven grid line and data line at each frame the data voltage of video data sequentially being write the liquid crystal cells of liquid crystal panel in mode line by line, and is used to control the first and second lamp groups to be opened in proper order or to close synchronously with one another.

28, liquid crystal display device according to claim 27 is characterized in that, described driver comprises:

Gate driver is used in each frame sequential ground driven grid line;

Data driver is used for driving data lines; And

Time schedule controller, in response to video data, the lamp that is used for control gate driver and data driver and enables the first and second lamp groups is with synchronously with one another by the order opening and closing.

29, liquid crystal display device according to claim 28, it is characterized in that, described back light unit comprises at least two lamp drivers, and described at least two lamp drivers are by time schedule controller control and produce the lamp driving voltage of lamp to be driven in proper order synchronously with one another that is used to enable the first and second lamp groups.

30, liquid crystal display device according to claim 29 is characterized in that, lamp driving voltage has different duty factors.

31, first data line that a kind of driving method of liquid crystal display device, this liquid crystal display device have liquid crystal panel, intersect on the first area of liquid crystal panel with grid line, and with second data line that grid line intersects on the second area of liquid crystal panel, comprising:

First video data that conversion has first frame rate is second video data with second frame rate that is higher than first frame rate;

According to the second video data driven grid line, first and second data lines; And

Control the first and second lamp groups with in the opening and closing side by side of second frame rate, the first lamp group has at least two lamps and the second lamp group that are used for the first area and has at least two lamps that are used for second area.

32, method according to claim 31 is characterized in that, second frame rate is the twice of first frame rate at least.

33, a kind of driving method of liquid crystal display device, this liquid crystal display device have grid line and data line liquid crystal panel intersected with each other, comprising:

According to video data driven grid line and data line with first frame rate; And

Control the first and second lamp groups with second frame rate that is higher than first frame rate by the while opening and closing, the first lamp group has at least two lamps of the first area that is used for liquid crystal panel and at least two lamps that the second lamp group has the second area that is used for liquid crystal panel.

34, method according to claim 33 is characterized in that, second frame rate is the twice of first frame rate at least.

35, method according to claim 33 is characterized in that, described grid line comprises:

First grid line intersects in the 3rd zone that takies part first and second zones with data line; And

Second grid line intersects in the 4th zone that takies the first and second regional remainders with data line.

36, a kind of control method of liquid crystal display device, this liquid crystal display device has liquid crystal panel, first data line that intersects in the first area with grid line and second data line that intersects at second area with grid line, at least two of the first area of corresponding liquid crystal panel first lamps partly, and at least two second lamps of the second area of corresponding liquid crystal panel partly, this method comprises:

Driven grid line and data line are side by side to write the liquid crystal cells of first area and the liquid crystal cells of second area to the data voltage of video data with row-by-row system; And

Make first lamp and second lamp together at every turn by opening and closing over the ground.

37, method according to claim 36 is characterized in that, grid line on the first area and the grid line on the second area per two cycles of horizontal-drive signal to be enabled in proper order synchronously with one another.

38, a kind of control method of liquid crystal display device, this liquid crystal display device has liquid crystal panel, first data line that intersects in the first area with grid line and second data line that intersects at second area with grid line, at least two of the first area of corresponding liquid crystal panel first lamps partly, and at least two second lamps of the second area of corresponding liquid crystal panel partly, this method comprises:

Driven grid line and data line are to write the liquid crystal cells of first area and the liquid crystal cells of second area to the data voltage of video data simultaneously with row-by-row system; And

Drive first and second lamps, thereby the lamp of the first and second lamp groups after writing liquid crystal cells on the liquid crystal panel, data voltage is unlocked side by side when the saturated period expires of orientation or closes.

39, according to the described method of claim 38, it is characterized in that, the step of described driven grid line and data line is included in each cycle of horizontal-drive signal, order enables grid line on the first area and the grid line on the second area synchronously with one another, and the lamp step of described driving is included in each frame opening and closing first and second lamp once.

According to the described method of claim 39, it is characterized in that 40, grid line on the first area and the grid line on the second area are enabled once synchronously with one another in proper order during the field cycle of each frame.

Images